Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.60	100.00	94.44		95.95	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.60	100.00	94.44		95.95	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	94.44		95.95	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T17,T76
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T11,T15
1	1	Covered	T10,T7,T11

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T32

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T32

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T32

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	71	95.95
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T10,T11,T15
AutoCaptGenCnt	143	Covered	T10,T11,T15
AutoCaptReseedCnt	141	Covered	T10,T11,T15
AutoDispatch	125	Covered	T10,T11,T15
AutoFirstAckWait	119	Covered	T10,T11,T15
AutoLoadIns	69	Covered	T10,T7,T11
AutoSendGenCmd	150	Covered	T10,T11,T15
AutoSendReseedCmd	162	Covered	T10,T11,T15
BootDone	98	Covered	T1,T2,T4
BootGenAckWait	90	Covered	T1,T2,T3
BootInsAckWait	80	Covered	T1,T2,T3
BootLoadGen	85	Covered	T1,T2,T3
BootLoadIns	65	Covered	T1,T2,T3
BootLoadUni	102	Covered	T1,T2,T38
BootPulse	94	Covered	T1,T2,T3
BootUniAckWait	107	Covered	T1,T2,T38
Error	188	Covered	T4,T7,T32
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T2,T3
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T10,T11,T15
AutoAckWait->Error	188	Not Covered
AutoAckWait->Idle	211	Covered	T15,T69,T54
AutoAckWait->RejectCsrngEntropy	188	Covered	T11,T56,T86
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T10,T11,T15
AutoCaptGenCnt->Error	188	Covered	T113,T114,T115
AutoCaptGenCnt->Idle	211	Covered	T116
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T117,T118,T119
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T10,T11,T15
AutoCaptReseedCnt->Error	188	Covered	T8,T120
AutoCaptReseedCnt->Idle	211	Covered	T121,T122,T123
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T124,T125,T126
AutoDispatch->AutoCaptGenCnt	143	Covered	T10,T11,T15
AutoDispatch->AutoCaptReseedCnt	141	Covered	T10,T11,T15
AutoDispatch->Error	188	Not Covered
AutoDispatch->Idle	138	Covered	T10,T15,T20
AutoDispatch->RejectCsrngEntropy	188	Covered	T127,T128,T129
AutoFirstAckWait->AutoDispatch	125	Covered	T10,T11,T15
AutoFirstAckWait->Error	188	Covered	T9,T61,T130
AutoFirstAckWait->Idle	211	Covered	T54,T131,T132
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T133,T134,T135
AutoLoadIns->AutoFirstAckWait	119	Covered	T10,T11,T15
AutoLoadIns->Error	188	Covered	T136,T137,T138
AutoLoadIns->Idle	211	Covered	T7,T45,T8
AutoLoadIns->RejectCsrngEntropy	188	Covered	T139,T91,T80
AutoSendGenCmd->AutoAckWait	156	Covered	T10,T11,T15
AutoSendGenCmd->Error	188	Covered	T140,T141
AutoSendGenCmd->Idle	211	Covered	T142,T143,T144
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T106,T145,T108
AutoSendReseedCmd->AutoAckWait	168	Covered	T10,T11,T15
AutoSendReseedCmd->Error	188	Covered	T63,T146,T147
AutoSendReseedCmd->Idle	211	Covered	T69,T148,T149
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T107,T150,T151
BootDone->BootLoadUni	102	Covered	T1,T2,T38
BootDone->Error	188	Covered	T4,T152,T153
BootDone->Idle	211	Covered	T154,T155,T156
BootDone->RejectCsrngEntropy	188	Covered	T55,T45,T104
BootGenAckWait->BootPulse	94	Covered	T1,T2,T3
BootGenAckWait->Error	188	Covered	T157,T158,T159
BootGenAckWait->Idle	211	Covered	T160,T161,T162
BootGenAckWait->RejectCsrngEntropy	188	Covered	T1,T2,T87
BootInsAckWait->BootLoadGen	85	Covered	T1,T2,T3
BootInsAckWait->Error	188	Covered	T58,T163,T164
BootInsAckWait->Idle	211	Covered	T4,T17,T58
BootInsAckWait->RejectCsrngEntropy	188	Covered	T76,T165,T166
BootLoadGen->BootGenAckWait	90	Covered	T1,T2,T3
BootLoadGen->Error	188	Covered	T167
BootLoadGen->Idle	211	Covered	T168,T169,T170
BootLoadGen->RejectCsrngEntropy	188	Covered	T171,T172,T173
BootLoadIns->BootInsAckWait	80	Covered	T1,T2,T3
BootLoadIns->Error	188	Covered	T17,T174,T161
BootLoadIns->Idle	211	Covered	T77,T175,T176
BootLoadIns->RejectCsrngEntropy	188	Covered	T177,T178,T179
BootLoadUni->BootUniAckWait	107	Covered	T1,T2,T38
BootLoadUni->Error	188	Covered	T180,T181,T182
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T183,T184,T185
BootPulse->BootDone	98	Covered	T1,T2,T4
BootPulse->Error	188	Covered	T186
BootPulse->Idle	211	Covered	T187,T188,T189
BootPulse->RejectCsrngEntropy	188	Covered	T3,T190,T191
BootUniAckWait->Error	188	Covered	T192,T193,T194
BootUniAckWait->Idle	112	Covered	T1,T2,T44
BootUniAckWait->RejectCsrngEntropy	188	Covered	T38,T84,T195
Idle->AutoLoadIns	69	Covered	T10,T7,T11
Idle->BootLoadIns	65	Covered	T1,T2,T3
Idle->Error	188	Covered	T16,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T3,T38,T11
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T196,T197,T198
RejectCsrngEntropy->Idle	211	Covered	T1,T2,T3
SWPortMode->Error	188	Covered	T16,T59,T199
SWPortMode->Idle	211	Covered	T3,T5,T6
SWPortMode->RejectCsrngEntropy	188	Covered	T1,T2,T45

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T7,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T38
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T38
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T38,T44,T74
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T38
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T11,T15
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T10,T7,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T10,T11,T15
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T10,T11,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T11,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T10,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T20,T105
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T10,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T10,T11,T15
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T10,T11,T15
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T11,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T15,T20
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T32
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T32,T16

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T7,T32
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T2,T3
0	-	-	1	Covered	T1,T2,T3
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	234015551	144815	0	0
FpvSecCmErrorStEscalate_A	234015551	145856	0	0
u_state_regs_A	233978788	233802050	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	144815	0	0
T4	1597	921	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	300	0	0
T8	0	1030	0	0
T9	0	350	0	0
T10	2699	0	0	0
T16	0	9173	0	0
T17	0	622	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1018	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	352	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	267	0	0
T200	0	200	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	145856	0	0
T4	1597	922	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	301	0	0
T8	0	1031	0	0
T9	0	351	0	0
T10	2699	0	0	0
T16	0	9303	0	0
T17	0	623	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1019	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	353	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	268	0	0
T200	0	201	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233978788	233802050	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1382	1255	0	0
T5	1075	944	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1884	1749	0	0