Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T24,T10
DataWait	75	Covered	T3,T24,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T7,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T187,T189,T201
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T24,T10
DataWait->AckPls	80	Covered	T3,T24,T10
DataWait->Disabled	107	Covered	T79,T202,T203
DataWait->Error	99	Covered	T4,T157,T204
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T77,T205,T206
EndPointClear->Error	99	Covered	T7,T16,T17
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T24,T4
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T32,T16

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T24,T10
Idle	-	1	0	-	Covered	T3,T24,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T24,T10
DataWait	-	-	-	0	Covered	T3,T24,T4
AckPls	-	-	-	-	Covered	T3,T24,T10
Error	-	-	-	-	Covered	T4,T7,T32
default	-	-	-	-	Covered	T16,T8,T9

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1638108857	1027155	0	0
FpvSecCmErrorStEscalate_A	1638108857	1034442	0	0
u_state_regs_A	1638072094	1636834928	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1638108857	1027155	0	0
T4	11179	6447	0	0
T5	7623	0	0	0
T6	6964062	0	0	0
T7	0	2450	0	0
T8	0	7160	0	0
T9	0	2400	0	0
T10	18893	0	0	0
T16	0	64211	0	0
T17	0	4354	0	0
T25	9541	0	0	0
T26	13286	0	0	0
T32	0	7476	0	0
T38	15911	0	0	0
T44	23492	0	0	0
T58	0	2464	0	0
T64	13713	0	0	0
T65	6559	0	0	0
T196	0	1819	0	0
T200	0	1750	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1638108857	1034442	0	0
T4	11179	6454	0	0
T5	7623	0	0	0
T6	6964062	0	0	0
T7	0	2457	0	0
T8	0	7167	0	0
T9	0	2407	0	0
T10	18893	0	0	0
T16	0	65121	0	0
T17	0	4361	0	0
T25	9541	0	0	0
T26	13286	0	0	0
T32	0	7483	0	0
T38	15911	0	0	0
T44	23492	0	0	0
T58	0	2471	0	0
T64	13713	0	0	0
T65	6559	0	0	0
T196	0	1826	0	0
T200	0	1757	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1638072094	1636834928	0	0
T1	12733	12194	0	0
T2	12502	11928	0	0
T3	12530	11879	0	0
T4	10964	10075	0	0
T5	7609	6692	0	0
T6	6964062	6963992	0	0
T10	18893	18445	0	0
T24	9226	8631	0	0
T25	9541	9030	0	0
T26	13272	12327	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T38,T41,T15
DataWait	75	Covered	T4,T38,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T7,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T38,T41,T15
DataWait->AckPls	80	Covered	T38,T41,T15
DataWait->Disabled	107	Covered	T79,T207
DataWait->Error	99	Covered	T4,T157,T61
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T77,T205,T206
EndPointClear->Error	99	Covered	T7,T16,T17
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T4,T38,T41
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T32,T16,T58

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T38,T41,T15
Idle	-	1	0	-	Covered	T4,T38,T41
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T38,T41,T15
DataWait	-	-	-	0	Covered	T4,T41,T15
AckPls	-	-	-	-	Covered	T38,T41,T15
Error	-	-	-	-	Covered	T4,T7,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	234015551	147065	0	0
FpvSecCmErrorStEscalate_A	234015551	148106	0	0
u_state_regs_A	234015551	233838813	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	147065	0	0
T4	1597	921	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	350	0	0
T8	0	1030	0	0
T9	0	350	0	0
T10	2699	0	0	0
T16	0	9173	0	0
T17	0	622	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1068	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	352	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	267	0	0
T200	0	250	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	148106	0	0
T4	1597	922	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	351	0	0
T8	0	1031	0	0
T9	0	351	0	0
T10	2699	0	0	0
T16	0	9303	0	0
T17	0	623	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1069	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	353	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	268	0	0
T200	0	251	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T41,T42,T47
DataWait	75	Covered	T41,T42,T47
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T7,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T41,T42,T47
DataWait->AckPls	80	Covered	T41,T42,T47
DataWait->Disabled	107	Covered	T208,T209,T210
DataWait->Error	99	Covered	T9,T211,T181
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T77,T205,T206
EndPointClear->Error	99	Covered	T7,T16,T17
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T41,T42,T47
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T32,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T41,T42,T47
Idle	-	1	0	-	Covered	T41,T42,T47
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T41,T42,T47
DataWait	-	-	-	0	Covered	T41,T42,T47
AckPls	-	-	-	-	Covered	T41,T42,T47
Error	-	-	-	-	Covered	T4,T7,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	234015551	147065	0	0
FpvSecCmErrorStEscalate_A	234015551	148106	0	0
u_state_regs_A	234015551	233838813	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	147065	0	0
T4	1597	921	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	350	0	0
T8	0	1030	0	0
T9	0	350	0	0
T10	2699	0	0	0
T16	0	9173	0	0
T17	0	622	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1068	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	352	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	267	0	0
T200	0	250	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	148106	0	0
T4	1597	922	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	351	0	0
T8	0	1031	0	0
T9	0	351	0	0
T10	2699	0	0	0
T16	0	9303	0	0
T17	0	623	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1069	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	353	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	268	0	0
T200	0	251	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T24
DataWait	75	Covered	T1,T2,T24
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T7,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T24
DataWait->AckPls	80	Covered	T1,T2,T24
DataWait->Disabled	107	Covered	T144,T169,T212
DataWait->Error	99	Covered	T213,T214
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T77,T205,T206
EndPointClear->Error	99	Covered	T7,T16,T17
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T24
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T32,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T24
Idle	-	1	0	-	Covered	T1,T2,T24
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T24
DataWait	-	-	-	0	Covered	T1,T2,T24
AckPls	-	-	-	-	Covered	T1,T2,T24
Error	-	-	-	-	Covered	T4,T7,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	234015551	147065	0	0
FpvSecCmErrorStEscalate_A	234015551	148106	0	0
u_state_regs_A	234015551	233838813	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	147065	0	0
T4	1597	921	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	350	0	0
T8	0	1030	0	0
T9	0	350	0	0
T10	2699	0	0	0
T16	0	9173	0	0
T17	0	622	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1068	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	352	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	267	0	0
T200	0	250	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	148106	0	0
T4	1597	922	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	351	0	0
T8	0	1031	0	0
T9	0	351	0	0
T10	2699	0	0	0
T16	0	9303	0	0
T17	0	623	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1069	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	353	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	268	0	0
T200	0	251	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T43,T42
DataWait	75	Covered	T24,T43,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T7,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T43,T42
DataWait->AckPls	80	Covered	T24,T43,T42
DataWait->Disabled	107	Covered	T215,T216
DataWait->Error	99	Covered	T200,T217,T218
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T77,T205,T206
EndPointClear->Error	99	Covered	T7,T16,T17
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T24,T43,T42
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T32,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T24,T43,T42
Idle	-	1	0	-	Covered	T24,T43,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T24,T43,T42
DataWait	-	-	-	0	Covered	T24,T43,T42
AckPls	-	-	-	-	Covered	T24,T43,T42
Error	-	-	-	-	Covered	T4,T7,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	234015551	147065	0	0
FpvSecCmErrorStEscalate_A	234015551	148106	0	0
u_state_regs_A	234015551	233838813	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	147065	0	0
T4	1597	921	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	350	0	0
T8	0	1030	0	0
T9	0	350	0	0
T10	2699	0	0	0
T16	0	9173	0	0
T17	0	622	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1068	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	352	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	267	0	0
T200	0	250	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	148106	0	0
T4	1597	922	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	351	0	0
T8	0	1031	0	0
T9	0	351	0	0
T10	2699	0	0	0
T16	0	9303	0	0
T17	0	623	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1069	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	353	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	268	0	0
T200	0	251	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T5,T41,T43
DataWait	75	Covered	T5,T41,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T7,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T5,T41,T43
DataWait->AckPls	80	Covered	T5,T41,T43
DataWait->Disabled	107	Covered	T143,T219,T220
DataWait->Error	99	Covered	T221,T182,T153
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T77,T205,T206
EndPointClear->Error	99	Covered	T7,T16,T17
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T5,T41,T43
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T32,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T5,T41,T43
Idle	-	1	0	-	Covered	T5,T41,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T5,T41,T43
DataWait	-	-	-	0	Covered	T41,T43,T42
AckPls	-	-	-	-	Covered	T5,T41,T43
Error	-	-	-	-	Covered	T4,T7,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	234015551	147065	0	0
FpvSecCmErrorStEscalate_A	234015551	148106	0	0
u_state_regs_A	234015551	233838813	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	147065	0	0
T4	1597	921	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	350	0	0
T8	0	1030	0	0
T9	0	350	0	0
T10	2699	0	0	0
T16	0	9173	0	0
T17	0	622	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1068	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	352	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	267	0	0
T200	0	250	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	148106	0	0
T4	1597	922	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	351	0	0
T8	0	1031	0	0
T9	0	351	0	0
T10	2699	0	0	0
T16	0	9303	0	0
T17	0	623	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1069	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	353	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	268	0	0
T200	0	251	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T24,T10
DataWait	75	Covered	T3,T24,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T7,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T187,T189,T201
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T24,T10
DataWait->AckPls	80	Covered	T3,T24,T10
DataWait->Disabled	107	Covered	T202,T203,T116
DataWait->Error	99	Covered	T204,T222,T62
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T77,T205,T206
EndPointClear->Error	99	Covered	T7,T16,T17
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T24,T10
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T32,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T24,T10
Idle	-	1	0	-	Covered	T3,T24,T10
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T24,T10
DataWait	-	-	-	0	Covered	T3,T24,T10
AckPls	-	-	-	-	Covered	T3,T24,T10
Error	-	-	-	-	Covered	T4,T7,T32
default	-	-	-	-	Covered	T16,T8,T9

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	234015551	144765	0	0
FpvSecCmErrorStEscalate_A	234015551	145806	0	0
u_state_regs_A	233978788	233802050	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	144765	0	0
T4	1597	921	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	350	0	0
T8	0	980	0	0
T9	0	300	0	0
T10	2699	0	0	0
T16	0	9173	0	0
T17	0	622	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1068	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	352	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	217	0	0
T200	0	250	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	145806	0	0
T4	1597	922	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	351	0	0
T8	0	981	0	0
T9	0	301	0	0
T10	2699	0	0	0
T16	0	9303	0	0
T17	0	623	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1069	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	353	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	218	0	0
T200	0	251	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233978788	233802050	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1382	1255	0	0
T5	1075	944	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1884	1749	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T38,T39,T40
DataWait	75	Covered	T38,T39,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T7,T32
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T223
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T38,T39,T40
DataWait->AckPls	80	Covered	T38,T39,T40
DataWait->Disabled	107	Covered	T160,T224,T168
DataWait->Error	99	Covered	T114,T225,T152
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T18,T19
EndPointClear->Disabled	107	Covered	T77,T205,T206
EndPointClear->Error	99	Covered	T7,T16,T17
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T38,T39,T40
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T32,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T38,T39,T40
Idle	-	1	0	-	Covered	T38,T39,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T38,T39,T40
DataWait	-	-	-	0	Covered	T38,T39,T40
AckPls	-	-	-	-	Covered	T38,T39,T40
Error	-	-	-	-	Covered	T4,T7,T32
default	-	-	-	-	Covered	T16,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T32
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	234015551	147065	0	0
FpvSecCmErrorStEscalate_A	234015551	148106	0	0
u_state_regs_A	234015551	233838813	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	147065	0	0
T4	1597	921	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	350	0	0
T8	0	1030	0	0
T9	0	350	0	0
T10	2699	0	0	0
T16	0	9173	0	0
T17	0	622	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1068	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	352	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	267	0	0
T200	0	250	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	148106	0	0
T4	1597	922	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	351	0	0
T8	0	1031	0	0
T9	0	351	0	0
T10	2699	0	0	0
T16	0	9303	0	0
T17	0	623	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T32	0	1069	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T58	0	353	0	0
T64	1959	0	0	0
T65	937	0	0	0
T196	0	268	0	0
T200	0	251	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0