Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T10,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T89,T90
1	1	0	Not Covered
1	1	1	Covered	T4,T10,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T34,T35
1	0	1	Covered	T4,T10,T7
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T15

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	467324694	604987	0	0
DepthKnown_A	468031102	467677626	0	0
RvalidKnown_A	468031102	467677626	0	0
WreadyKnown_A	468031102	467677626	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	467685566	686289	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	467324694	604987	0	0
T5	524	0	0	0
T6	1989732	0	0	0
T7	232	61	0	0
T8	0	83	0	0
T10	5398	2292	0	0
T11	0	831	0	0
T15	0	2388	0	0
T20	0	2133	0	0
T25	2726	0	0	0
T26	694	0	0	0
T38	4546	0	0	0
T44	6712	0	0	0
T45	0	241	0	0
T54	0	1871	0	0
T56	0	545	0	0
T64	3918	0	0	0
T65	1874	0	0	0
T69	0	3969	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468031102	467677626	0	0
T1	3638	3484	0	0
T2	3572	3408	0	0
T3	3580	3394	0	0
T4	3194	2940	0	0
T5	2178	1916	0	0
T6	1989732	1989712	0	0
T10	5398	5270	0	0
T24	2636	2466	0	0
T25	2726	2580	0	0
T26	3796	3526	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468031102	467677626	0	0
T1	3638	3484	0	0
T2	3572	3408	0	0
T3	3580	3394	0	0
T4	3194	2940	0	0
T5	2178	1916	0	0
T6	1989732	1989712	0	0
T10	5398	5270	0	0
T24	2636	2466	0	0
T25	2726	2580	0	0
T26	3796	3526	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468031102	467677626	0	0
T1	3638	3484	0	0
T2	3572	3408	0	0
T3	3580	3394	0	0
T4	3194	2940	0	0
T5	2178	1916	0	0
T6	1989732	1989712	0	0
T10	5398	5270	0	0
T24	2636	2466	0	0
T25	2726	2580	0	0
T26	3796	3526	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	467685566	686289	0	0
T4	3194	321	0	0
T5	2178	0	0	0
T6	1989732	0	0	0
T7	0	630	0	0
T10	5398	2292	0	0
T11	0	831	0	0
T15	0	2388	0	0
T17	0	220	0	0
T20	0	2133	0	0
T25	2726	0	0	0
T26	3796	0	0	0
T31	0	7	0	0
T38	4546	0	0	0
T44	6712	0	0	0
T45	0	241	0	0
T56	0	279	0	0
T64	3918	0	0	0
T65	1874	0	0	0
T69	0	3969	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T91,T92,T93
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T10,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T10,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35
1	0	1	Covered	T4,T10,T7
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	233662347	296960	0	0
DepthKnown_A	234015551	233838813	0	0
RvalidKnown_A	234015551	233838813	0	0
WreadyKnown_A	234015551	233838813	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	233842783	337381	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233662347	296960	0	0
T5	262	0	0	0
T6	994866	0	0	0
T7	116	19	0	0
T8	0	35	0	0
T10	2699	1124	0	0
T11	0	373	0	0
T15	0	1174	0	0
T20	0	1064	0	0
T25	1363	0	0	0
T26	347	0	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T45	0	85	0	0
T54	0	920	0	0
T56	0	279	0	0
T64	1959	0	0	0
T65	937	0	0	0
T69	0	1910	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	233842783	337381	0	0
T4	1597	164	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	302	0	0
T10	2699	1124	0	0
T11	0	373	0	0
T15	0	1174	0	0
T17	0	111	0	0
T20	0	1064	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T45	0	85	0	0
T56	0	279	0	0
T64	1959	0	0	0
T65	937	0	0	0
T69	0	1910	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T7,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T10,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T89,T90
1	1	0	Not Covered
1	1	1	Covered	T4,T10,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T34,T94
1	0	1	Covered	T4,T10,T7
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T10,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	233662347	308027	0	0
DepthKnown_A	234015551	233838813	0	0
RvalidKnown_A	234015551	233838813	0	0
WreadyKnown_A	234015551	233838813	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	233842783	348908	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233662347	308027	0	0
T5	262	0	0	0
T6	994866	0	0	0
T7	116	42	0	0
T8	0	48	0	0
T10	2699	1168	0	0
T11	0	458	0	0
T15	0	1214	0	0
T20	0	1069	0	0
T25	1363	0	0	0
T26	347	0	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T45	0	156	0	0
T54	0	951	0	0
T56	0	266	0	0
T64	1959	0	0	0
T65	937	0	0	0
T69	0	2059	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	234015551	233838813	0	0
T1	1819	1742	0	0
T2	1786	1704	0	0
T3	1790	1697	0	0
T4	1597	1470	0	0
T5	1089	958	0	0
T6	994866	994856	0	0
T10	2699	2635	0	0
T24	1318	1233	0	0
T25	1363	1290	0	0
T26	1898	1763	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	233842783	348908	0	0
T4	1597	157	0	0
T5	1089	0	0	0
T6	994866	0	0	0
T7	0	328	0	0
T10	2699	1168	0	0
T11	0	458	0	0
T15	0	1214	0	0
T17	0	109	0	0
T20	0	1069	0	0
T25	1363	0	0	0
T26	1898	0	0	0
T31	0	7	0	0
T38	2273	0	0	0
T44	3356	0	0	0
T45	0	156	0	0
T64	1959	0	0	0
T65	937	0	0	0
T69	0	2059	0	0