Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T24 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T15 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T24,T10 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T24,T10 |
| 1 | 0 | Covered | T3,T24,T10 |
| 1 | 1 | Covered | T3,T24,T10 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T10 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T3,T24,T10 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T3,T24,T10 |
| 1 | 1 | Covered | T3,T24,T10 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T10 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T10 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T10 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T10 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T24,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T38,T11 |
| 1 | 1 | Covered | T3,T24,T10 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T24,T10 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_packer_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T3,T24,T10 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T24,T10 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_packer_fifo
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1872124408 |
209560760 |
0 |
7712 |
| T3 |
1790 |
1152 |
0 |
1 |
| T4 |
1597 |
0 |
0 |
1 |
| T5 |
1089 |
0 |
0 |
1 |
| T6 |
994866 |
992280 |
0 |
1 |
| T7 |
1572 |
0 |
0 |
2 |
| T8 |
0 |
1036 |
0 |
0 |
| T10 |
2699 |
1398 |
0 |
1 |
| T11 |
2012 |
0 |
0 |
1 |
| T24 |
1318 |
964 |
0 |
1 |
| T25 |
1363 |
1087 |
0 |
1 |
| T26 |
1898 |
0 |
0 |
1 |
| T31 |
3796 |
974 |
0 |
2 |
| T32 |
2063 |
0 |
0 |
1 |
| T38 |
6819 |
1292 |
0 |
3 |
| T39 |
5697 |
1256 |
0 |
3 |
| T40 |
0 |
1426 |
0 |
0 |
| T41 |
10314 |
2062 |
0 |
3 |
| T42 |
0 |
2845 |
0 |
0 |
| T44 |
6712 |
1706 |
0 |
2 |
| T45 |
0 |
1041 |
0 |
0 |
| T46 |
0 |
1328 |
0 |
0 |
| T47 |
0 |
4174 |
0 |
0 |
| T49 |
0 |
4235 |
0 |
0 |
| T64 |
1959 |
0 |
0 |
1 |
| T65 |
1874 |
765 |
0 |
2 |
| T73 |
3790 |
1573 |
0 |
2 |
| T74 |
9268 |
2803 |
0 |
2 |
| T75 |
3480 |
0 |
0 |
3 |
| T76 |
0 |
802 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1872124408 |
209560760 |
0 |
0 |
| T3 |
1790 |
1152 |
0 |
0 |
| T4 |
1597 |
0 |
0 |
0 |
| T5 |
1089 |
0 |
0 |
0 |
| T6 |
994866 |
992280 |
0 |
0 |
| T7 |
1572 |
0 |
0 |
0 |
| T8 |
0 |
1036 |
0 |
0 |
| T10 |
2699 |
1398 |
0 |
0 |
| T11 |
2012 |
0 |
0 |
0 |
| T24 |
1318 |
964 |
0 |
0 |
| T25 |
1363 |
1087 |
0 |
0 |
| T26 |
1898 |
0 |
0 |
0 |
| T31 |
3796 |
974 |
0 |
0 |
| T32 |
2063 |
0 |
0 |
0 |
| T38 |
6819 |
1292 |
0 |
0 |
| T39 |
5697 |
1256 |
0 |
0 |
| T40 |
0 |
1426 |
0 |
0 |
| T41 |
10314 |
2062 |
0 |
0 |
| T42 |
0 |
2845 |
0 |
0 |
| T44 |
6712 |
1706 |
0 |
0 |
| T45 |
0 |
1041 |
0 |
0 |
| T46 |
0 |
1328 |
0 |
0 |
| T47 |
0 |
4174 |
0 |
0 |
| T49 |
0 |
4235 |
0 |
0 |
| T64 |
1959 |
0 |
0 |
0 |
| T65 |
1874 |
765 |
0 |
0 |
| T73 |
3790 |
1573 |
0 |
0 |
| T74 |
9268 |
2803 |
0 |
0 |
| T75 |
3480 |
0 |
0 |
0 |
| T76 |
0 |
802 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T24 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T15 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
12 |
85.71 |
| TERNARY |
142 |
4 |
3 |
75.00 |
| TERNARY |
147 |
3 |
2 |
66.67 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Not Covered |
|
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
81691 |
0 |
964 |
| T2 |
1786 |
6 |
0 |
1 |
| T3 |
1790 |
24 |
0 |
1 |
| T4 |
1597 |
0 |
0 |
1 |
| T5 |
1089 |
41 |
0 |
1 |
| T6 |
994866 |
0 |
0 |
1 |
| T10 |
2699 |
0 |
0 |
1 |
| T24 |
1318 |
6 |
0 |
1 |
| T25 |
1363 |
0 |
0 |
1 |
| T26 |
1898 |
42 |
0 |
1 |
| T31 |
0 |
13 |
0 |
0 |
| T38 |
0 |
209 |
0 |
0 |
| T44 |
0 |
75 |
0 |
0 |
| T64 |
1959 |
0 |
0 |
1 |
| T73 |
0 |
44 |
0 |
0 |
| T74 |
0 |
12 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
81691 |
0 |
0 |
| T2 |
1786 |
6 |
0 |
0 |
| T3 |
1790 |
24 |
0 |
0 |
| T4 |
1597 |
0 |
0 |
0 |
| T5 |
1089 |
41 |
0 |
0 |
| T6 |
994866 |
0 |
0 |
0 |
| T10 |
2699 |
0 |
0 |
0 |
| T24 |
1318 |
6 |
0 |
0 |
| T25 |
1363 |
0 |
0 |
0 |
| T26 |
1898 |
42 |
0 |
0 |
| T31 |
0 |
13 |
0 |
0 |
| T38 |
0 |
209 |
0 |
0 |
| T44 |
0 |
75 |
0 |
0 |
| T64 |
1959 |
0 |
0 |
0 |
| T73 |
0 |
44 |
0 |
0 |
| T74 |
0 |
12 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T24,T10 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T24,T10 |
| 1 | 0 | Covered | T3,T24,T10 |
| 1 | 1 | Covered | T3,T24,T10 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T10 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T3,T24,T10 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T3,T24,T10 |
| 1 | 1 | Covered | T3,T24,T10 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T10 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T10 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T10 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T24,T10 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T24,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T11,T84 |
| 1 | 1 | Covered | T3,T24,T10 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T24,T10 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T3,T24,T10 |
| 0 |
0 |
1 |
Covered |
T3,T24,T10 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T24,T10 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T24,T10 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
208126772 |
0 |
964 |
| T3 |
1790 |
1152 |
0 |
1 |
| T4 |
1597 |
0 |
0 |
1 |
| T5 |
1089 |
0 |
0 |
1 |
| T6 |
994866 |
992280 |
0 |
1 |
| T10 |
2699 |
1398 |
0 |
1 |
| T24 |
1318 |
964 |
0 |
1 |
| T25 |
1363 |
1087 |
0 |
1 |
| T26 |
1898 |
0 |
0 |
1 |
| T31 |
0 |
974 |
0 |
0 |
| T38 |
2273 |
0 |
0 |
1 |
| T44 |
0 |
1706 |
0 |
0 |
| T64 |
1959 |
0 |
0 |
1 |
| T65 |
0 |
765 |
0 |
0 |
| T73 |
0 |
1573 |
0 |
0 |
| T74 |
0 |
2803 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
208126772 |
0 |
0 |
| T3 |
1790 |
1152 |
0 |
0 |
| T4 |
1597 |
0 |
0 |
0 |
| T5 |
1089 |
0 |
0 |
0 |
| T6 |
994866 |
992280 |
0 |
0 |
| T10 |
2699 |
1398 |
0 |
0 |
| T24 |
1318 |
964 |
0 |
0 |
| T25 |
1363 |
1087 |
0 |
0 |
| T26 |
1898 |
0 |
0 |
0 |
| T31 |
0 |
974 |
0 |
0 |
| T38 |
2273 |
0 |
0 |
0 |
| T44 |
0 |
1706 |
0 |
0 |
| T64 |
1959 |
0 |
0 |
0 |
| T65 |
0 |
765 |
0 |
0 |
| T73 |
0 |
1573 |
0 |
0 |
| T74 |
0 |
2803 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T38,T39,T40 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T39,T40 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T38,T39,T40 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T39,T40 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T39,T40 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T39,T40 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T39,T40 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T39,T40 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T45,T226,T183 |
| 1 | 1 | Covered | T38,T39,T40 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T39,T40 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T38,T39,T40 |
| 0 |
0 |
1 |
Covered |
T38,T39,T40 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T38,T39,T40 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T38,T39,T40 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
281765 |
0 |
964 |
| T7 |
786 |
0 |
0 |
1 |
| T8 |
0 |
1036 |
0 |
0 |
| T31 |
1898 |
0 |
0 |
1 |
| T38 |
2273 |
1160 |
0 |
1 |
| T39 |
1899 |
1256 |
0 |
1 |
| T40 |
0 |
1426 |
0 |
0 |
| T41 |
3438 |
0 |
0 |
1 |
| T42 |
0 |
1493 |
0 |
0 |
| T44 |
3356 |
0 |
0 |
1 |
| T45 |
0 |
1041 |
0 |
0 |
| T46 |
0 |
1328 |
0 |
0 |
| T47 |
0 |
1981 |
0 |
0 |
| T49 |
0 |
2658 |
0 |
0 |
| T65 |
937 |
0 |
0 |
1 |
| T73 |
1895 |
0 |
0 |
1 |
| T74 |
4634 |
0 |
0 |
1 |
| T75 |
1160 |
0 |
0 |
1 |
| T76 |
0 |
802 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
281765 |
0 |
0 |
| T7 |
786 |
0 |
0 |
0 |
| T8 |
0 |
1036 |
0 |
0 |
| T31 |
1898 |
0 |
0 |
0 |
| T38 |
2273 |
1160 |
0 |
0 |
| T39 |
1899 |
1256 |
0 |
0 |
| T40 |
0 |
1426 |
0 |
0 |
| T41 |
3438 |
0 |
0 |
0 |
| T42 |
0 |
1493 |
0 |
0 |
| T44 |
3356 |
0 |
0 |
0 |
| T45 |
0 |
1041 |
0 |
0 |
| T46 |
0 |
1328 |
0 |
0 |
| T47 |
0 |
1981 |
0 |
0 |
| T49 |
0 |
2658 |
0 |
0 |
| T65 |
937 |
0 |
0 |
0 |
| T73 |
1895 |
0 |
0 |
0 |
| T74 |
4634 |
0 |
0 |
0 |
| T75 |
1160 |
0 |
0 |
0 |
| T76 |
0 |
802 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T38,T41,T15 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T41,T15 |
| 1 | 0 | Covered | T38,T41,T15 |
| 1 | 1 | Covered | T38,T41,T15 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T41,T15 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T38,T41,T15 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T38,T41,T15 |
| 1 | 1 | Covered | T38,T41,T15 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T41,T15 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T41,T15 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T41,T15 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T38,T41,T15 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T38,T41,T15 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T38,T195,T227 |
| 1 | 1 | Covered | T38,T41,T15 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T38,T41,T15 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T38,T41,T15 |
| 0 |
0 |
1 |
Covered |
T38,T41,T15 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T38,T41,T15 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T38,T41,T15 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
248394 |
0 |
964 |
| T7 |
786 |
0 |
0 |
1 |
| T15 |
0 |
518 |
0 |
0 |
| T21 |
0 |
2433 |
0 |
0 |
| T31 |
1898 |
0 |
0 |
1 |
| T38 |
2273 |
132 |
0 |
1 |
| T39 |
1899 |
0 |
0 |
1 |
| T41 |
3438 |
2062 |
0 |
1 |
| T42 |
0 |
1352 |
0 |
0 |
| T44 |
3356 |
0 |
0 |
1 |
| T47 |
0 |
2193 |
0 |
0 |
| T49 |
0 |
1577 |
0 |
0 |
| T65 |
937 |
0 |
0 |
1 |
| T73 |
1895 |
0 |
0 |
1 |
| T74 |
4634 |
0 |
0 |
1 |
| T75 |
1160 |
0 |
0 |
1 |
| T77 |
0 |
1145 |
0 |
0 |
| T78 |
0 |
1388 |
0 |
0 |
| T79 |
0 |
728 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
248394 |
0 |
0 |
| T7 |
786 |
0 |
0 |
0 |
| T15 |
0 |
518 |
0 |
0 |
| T21 |
0 |
2433 |
0 |
0 |
| T31 |
1898 |
0 |
0 |
0 |
| T38 |
2273 |
132 |
0 |
0 |
| T39 |
1899 |
0 |
0 |
0 |
| T41 |
3438 |
2062 |
0 |
0 |
| T42 |
0 |
1352 |
0 |
0 |
| T44 |
3356 |
0 |
0 |
0 |
| T47 |
0 |
2193 |
0 |
0 |
| T49 |
0 |
1577 |
0 |
0 |
| T65 |
937 |
0 |
0 |
0 |
| T73 |
1895 |
0 |
0 |
0 |
| T74 |
4634 |
0 |
0 |
0 |
| T75 |
1160 |
0 |
0 |
0 |
| T77 |
0 |
1145 |
0 |
0 |
| T78 |
0 |
1388 |
0 |
0 |
| T79 |
0 |
728 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T41,T42,T47 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T47 |
| 1 | 0 | Covered | T41,T42,T47 |
| 1 | 1 | Covered | T41,T42,T47 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T41,T42,T47 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T41,T42,T47 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T41,T42,T47 |
| 1 | 1 | Covered | T41,T42,T47 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T41,T42,T47 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T41,T42,T47 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T41,T42,T47 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T41,T42,T47 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T47 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T188,T162 |
| 1 | 1 | Covered | T41,T42,T47 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T47 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T41,T42,T47 |
| 0 |
0 |
1 |
Covered |
T41,T42,T47 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T41,T42,T47 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T41,T42,T47 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
251953 |
0 |
964 |
| T11 |
2012 |
0 |
0 |
1 |
| T15 |
1906 |
0 |
0 |
1 |
| T21 |
0 |
1261 |
0 |
0 |
| T22 |
0 |
2286 |
0 |
0 |
| T32 |
2063 |
0 |
0 |
1 |
| T39 |
1899 |
0 |
0 |
1 |
| T40 |
1589 |
0 |
0 |
1 |
| T41 |
3438 |
2047 |
0 |
1 |
| T42 |
0 |
1458 |
0 |
0 |
| T47 |
0 |
1855 |
0 |
0 |
| T50 |
0 |
2826 |
0 |
0 |
| T51 |
0 |
794 |
0 |
0 |
| T75 |
1160 |
0 |
0 |
1 |
| T80 |
0 |
1355 |
0 |
0 |
| T81 |
0 |
1290 |
0 |
0 |
| T82 |
0 |
1491 |
0 |
0 |
| T83 |
2246 |
0 |
0 |
1 |
| T84 |
2348 |
0 |
0 |
1 |
| T85 |
1137 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
251953 |
0 |
0 |
| T11 |
2012 |
0 |
0 |
0 |
| T15 |
1906 |
0 |
0 |
0 |
| T21 |
0 |
1261 |
0 |
0 |
| T22 |
0 |
2286 |
0 |
0 |
| T32 |
2063 |
0 |
0 |
0 |
| T39 |
1899 |
0 |
0 |
0 |
| T40 |
1589 |
0 |
0 |
0 |
| T41 |
3438 |
2047 |
0 |
0 |
| T42 |
0 |
1458 |
0 |
0 |
| T47 |
0 |
1855 |
0 |
0 |
| T50 |
0 |
2826 |
0 |
0 |
| T51 |
0 |
794 |
0 |
0 |
| T75 |
1160 |
0 |
0 |
0 |
| T80 |
0 |
1355 |
0 |
0 |
| T81 |
0 |
1290 |
0 |
0 |
| T82 |
0 |
1491 |
0 |
0 |
| T83 |
2246 |
0 |
0 |
0 |
| T84 |
2348 |
0 |
0 |
0 |
| T85 |
1137 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T24 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T24 |
| 1 | 0 | Covered | T1,T2,T24 |
| 1 | 1 | Covered | T1,T2,T24 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T24 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T24 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T24 |
| 1 | 1 | Covered | T1,T2,T24 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T24 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T24 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T24 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T24 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T24 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T81,T154,T155 |
| 1 | 1 | Covered | T1,T2,T24 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T24 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T24 |
| 0 |
0 |
1 |
Covered |
T1,T2,T24 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T24 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T24 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
220076 |
0 |
964 |
| T1 |
1819 |
1104 |
0 |
1 |
| T2 |
1786 |
899 |
0 |
1 |
| T3 |
1790 |
0 |
0 |
1 |
| T4 |
1597 |
0 |
0 |
1 |
| T5 |
1089 |
0 |
0 |
1 |
| T6 |
994866 |
0 |
0 |
1 |
| T10 |
2699 |
0 |
0 |
1 |
| T21 |
0 |
1219 |
0 |
0 |
| T24 |
1318 |
962 |
0 |
1 |
| T25 |
1363 |
0 |
0 |
1 |
| T26 |
1898 |
975 |
0 |
1 |
| T41 |
0 |
1855 |
0 |
0 |
| T42 |
0 |
1453 |
0 |
0 |
| T48 |
0 |
1183 |
0 |
0 |
| T50 |
0 |
2985 |
0 |
0 |
| T86 |
0 |
1253 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
220076 |
0 |
0 |
| T1 |
1819 |
1104 |
0 |
0 |
| T2 |
1786 |
899 |
0 |
0 |
| T3 |
1790 |
0 |
0 |
0 |
| T4 |
1597 |
0 |
0 |
0 |
| T5 |
1089 |
0 |
0 |
0 |
| T6 |
994866 |
0 |
0 |
0 |
| T10 |
2699 |
0 |
0 |
0 |
| T21 |
0 |
1219 |
0 |
0 |
| T24 |
1318 |
962 |
0 |
0 |
| T25 |
1363 |
0 |
0 |
0 |
| T26 |
1898 |
975 |
0 |
0 |
| T41 |
0 |
1855 |
0 |
0 |
| T42 |
0 |
1453 |
0 |
0 |
| T48 |
0 |
1183 |
0 |
0 |
| T50 |
0 |
2985 |
0 |
0 |
| T86 |
0 |
1253 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T24,T43,T42 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T24,T43,T42 |
| 1 | 0 | Covered | T24,T43,T42 |
| 1 | 1 | Covered | T24,T43,T42 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T24,T43,T42 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T24,T43,T42 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T24,T43,T42 |
| 1 | 1 | Covered | T24,T43,T42 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T24,T43,T42 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T24,T43,T42 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T24,T43,T42 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T24,T43,T42 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T24,T43,T42 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T52,T190,T228 |
| 1 | 1 | Covered | T24,T43,T42 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T24,T43,T42 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T24,T43,T42 |
| 0 |
0 |
1 |
Covered |
T24,T43,T42 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T24,T43,T42 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T24,T43,T42 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
174673 |
0 |
964 |
| T4 |
1597 |
0 |
0 |
1 |
| T5 |
1089 |
0 |
0 |
1 |
| T6 |
994866 |
0 |
0 |
1 |
| T10 |
2699 |
0 |
0 |
1 |
| T21 |
0 |
1367 |
0 |
0 |
| T22 |
0 |
2277 |
0 |
0 |
| T24 |
1318 |
859 |
0 |
1 |
| T25 |
1363 |
0 |
0 |
1 |
| T26 |
1898 |
0 |
0 |
1 |
| T38 |
2273 |
0 |
0 |
1 |
| T42 |
0 |
1439 |
0 |
0 |
| T43 |
0 |
1515 |
0 |
0 |
| T47 |
0 |
2149 |
0 |
0 |
| T50 |
0 |
3202 |
0 |
0 |
| T52 |
0 |
1363 |
0 |
0 |
| T64 |
1959 |
0 |
0 |
1 |
| T65 |
937 |
0 |
0 |
1 |
| T82 |
0 |
1624 |
0 |
0 |
| T87 |
0 |
1127 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
174673 |
0 |
0 |
| T4 |
1597 |
0 |
0 |
0 |
| T5 |
1089 |
0 |
0 |
0 |
| T6 |
994866 |
0 |
0 |
0 |
| T10 |
2699 |
0 |
0 |
0 |
| T21 |
0 |
1367 |
0 |
0 |
| T22 |
0 |
2277 |
0 |
0 |
| T24 |
1318 |
859 |
0 |
0 |
| T25 |
1363 |
0 |
0 |
0 |
| T26 |
1898 |
0 |
0 |
0 |
| T38 |
2273 |
0 |
0 |
0 |
| T42 |
0 |
1439 |
0 |
0 |
| T43 |
0 |
1515 |
0 |
0 |
| T47 |
0 |
2149 |
0 |
0 |
| T50 |
0 |
3202 |
0 |
0 |
| T52 |
0 |
1363 |
0 |
0 |
| T64 |
1959 |
0 |
0 |
0 |
| T65 |
937 |
0 |
0 |
0 |
| T82 |
0 |
1624 |
0 |
0 |
| T87 |
0 |
1127 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 82 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
| ALWAYS | 127 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 147 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 89 |
1 |
1 |
| 94 |
1 |
1 |
| 96 |
1 |
1 |
| 127 |
1 |
1 |
| 128 |
1 |
1 |
| 130 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 140 |
1 |
1 |
| 142 |
1 |
1 |
| 147 |
1 |
1 |
| 151 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 158 |
1 |
1 |
| 163 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 137
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T41,T43,T42 |
LINE 137
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T43,T42 |
| 1 | 0 | Covered | T5,T41,T43 |
| 1 | 1 | Covered | T41,T43,T42 |
LINE 137
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T41,T43,T42 |
LINE 138
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 139
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T5,T41,T43 |
LINE 140
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T5,T41,T43 |
| 1 | 1 | Covered | T5,T41,T43 |
LINE 142
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 142
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T41,T43 |
LINE 142
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - DepthOne)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T41,T43 |
LINE 147
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 147
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + DepthOne)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T41,T43 |
LINE 151
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 151
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T41,T43 |
LINE 156
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T41,T43 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 156
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 158
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T229,T230,T231 |
| 1 | 1 | Covered | T5,T41,T43 |
LINE 158
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T41,T43 |
| 1 | Covered | T1,T2,T3 |
LINE 158
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
142 |
4 |
4 |
100.00 |
| TERNARY |
147 |
3 |
3 |
100.00 |
| TERNARY |
151 |
3 |
3 |
100.00 |
| IF |
82 |
2 |
2 |
100.00 |
| IF |
127 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 142 (clear_status) ?
-2-: 142 (load_data) ?
-3-: 142 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T5,T41,T43 |
| 0 |
0 |
1 |
Covered |
T5,T41,T43 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 147 (clear_status) ?
-2-: 147 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T41,T43 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 151 (clear_data) ?
-2-: 151 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T5,T41,T43 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 82 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 127 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
175436 |
0 |
964 |
| T5 |
1089 |
495 |
0 |
1 |
| T6 |
994866 |
0 |
0 |
1 |
| T7 |
786 |
0 |
0 |
1 |
| T21 |
0 |
1343 |
0 |
0 |
| T22 |
0 |
1520 |
0 |
0 |
| T25 |
1363 |
0 |
0 |
1 |
| T26 |
1898 |
0 |
0 |
1 |
| T38 |
2273 |
0 |
0 |
1 |
| T41 |
0 |
1803 |
0 |
0 |
| T42 |
0 |
1436 |
0 |
0 |
| T43 |
0 |
1495 |
0 |
0 |
| T44 |
3356 |
0 |
0 |
1 |
| T47 |
0 |
2144 |
0 |
0 |
| T48 |
0 |
1062 |
0 |
0 |
| T54 |
0 |
717 |
0 |
0 |
| T64 |
1959 |
0 |
0 |
1 |
| T65 |
937 |
0 |
0 |
1 |
| T73 |
1895 |
0 |
0 |
1 |
| T88 |
0 |
2401 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
234015551 |
175436 |
0 |
0 |
| T5 |
1089 |
495 |
0 |
0 |
| T6 |
994866 |
0 |
0 |
0 |
| T7 |
786 |
0 |
0 |
0 |
| T21 |
0 |
1343 |
0 |
0 |
| T22 |
0 |
1520 |
0 |
0 |
| T25 |
1363 |
0 |
0 |
0 |
| T26 |
1898 |
0 |
0 |
0 |
| T38 |
2273 |
0 |
0 |
0 |
| T41 |
0 |
1803 |
0 |
0 |
| T42 |
0 |
1436 |
0 |
0 |
| T43 |
0 |
1495 |
0 |
0 |
| T44 |
3356 |
0 |
0 |
0 |
| T47 |
0 |
2144 |
0 |
0 |
| T48 |
0 |
1062 |
0 |
0 |
| T54 |
0 |
717 |
0 |
0 |
| T64 |
1959 |
0 |
0 |
0 |
| T65 |
937 |
0 |
0 |
0 |
| T73 |
1895 |
0 |
0 |
0 |
| T88 |
0 |
2401 |
0 |
0 |