SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
16.67 | 16.67 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
edn_cs_cmd_response_cg | 16.67 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
16.67 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 5 | 1 | 16.67 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_csrng_rsp_sts_cg | 6 | 5 | 1 | 16.67 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 6 | 5 | 1 | 16.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[CMD_STS_INVALID_ACMD] | 0 | 1 | 1 | |
auto[CMD_STS_INVALID_GEN_CMD] | 0 | 1 | 1 | |
auto[CMD_STS_INVALID_CMD_SEQ] | 0 | 1 | 1 | |
auto[CMD_STS_RESEED_CNT_EXCEEDED] | 0 | 1 | 1 | |
auto[CMD_STS_UNDRIVEN] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[CMD_STS_SUCCESS] | 12208 | 1 | T1 | 7 | T2 | 7 | T23 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |