Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	602130	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4748451

1

T1

32

T2

31

T3

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1425330	1			T1	120		T2	125		T3	27
values[0x0]	1815588	1			T1	14		T2	15		T3	25
values[0x1]	2109663	1			T1	16		T2	15		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	301606	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5048975

1

T1

65

T2

75

T3

52

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21743	1			T2	1		T24	1		T11	1
valid_sources[0x01]	19756	1			T24	3		T4	21		T82	1
valid_sources[0x02]	20479	1			T2	2		T23	30		T4	19
valid_sources[0x03]	21073	1			T2	1		T24	3		T4	1
valid_sources[0x04]	19452	1			T3	1		T4	1		T26	9
valid_sources[0x05]	22849	1			T4	9		T82	1		T15	1
valid_sources[0x06]	22482	1			T2	2		T3	1		T5	24
valid_sources[0x07]	21367	1			T3	6		T24	2		T45	3
valid_sources[0x08]	20701	1			T3	7		T24	3		T4	10
valid_sources[0x09]	20807	1			T2	1		T4	2		T82	1
valid_sources[0x0a]	21949	1			T24	1		T45	2		T15	1
valid_sources[0x0b]	21905	1			T24	1		T50	3		T72	4
valid_sources[0x0c]	19865	1			T2	3		T45	1		T15	1
valid_sources[0x0d]	21016	1			T82	1		T45	1		T40	1
valid_sources[0x0e]	20671	1			T24	2		T82	1		T40	10
valid_sources[0x0f]	20104	1			T24	1		T45	3		T40	5
valid_sources[0x10]	19891	1			T24	1		T4	4		T82	1
valid_sources[0x11]	21588	1			T82	1		T45	1		T40	5
valid_sources[0x12]	17217	1			T2	2		T24	2		T4	5
valid_sources[0x13]	20842	1			T24	1		T82	1		T45	2
valid_sources[0x14]	20378	1			T3	2		T4	2		T82	1
valid_sources[0x15]	19623	1			T3	1		T24	1		T45	2
valid_sources[0x16]	23529	1			T24	1		T45	1		T15	1
valid_sources[0x17]	20436	1			T3	1		T24	1		T82	1
valid_sources[0x18]	19969	1			T4	5		T45	1		T40	1
valid_sources[0x19]	20714	1			T2	1		T4	7		T45	2
valid_sources[0x1a]	19011	1			T45	5		T15	1		T40	2
valid_sources[0x1b]	20990	1			T4	15		T11	2		T15	2
valid_sources[0x1c]	20162	1			T2	1		T3	1		T82	1
valid_sources[0x1d]	20000	1			T82	2		T45	4		T15	1
valid_sources[0x1e]	21747	1			T24	2		T82	1		T40	2
valid_sources[0x1f]	21211	1			T2	2		T24	1		T82	1
valid_sources[0x20]	20623	1			T4	9		T82	2		T45	2
valid_sources[0x21]	22272	1			T24	1		T4	1		T82	2
valid_sources[0x22]	20281	1			T24	1		T4	3		T11	1
valid_sources[0x23]	21062	1			T3	1		T24	1		T4	6
valid_sources[0x24]	21227	1			T4	13		T82	1		T45	2
valid_sources[0x25]	21291	1			T2	2		T24	1		T40	2
valid_sources[0x26]	19724	1			T4	5		T45	1		T50	3
valid_sources[0x27]	20720	1			T2	3		T24	1		T4	2
valid_sources[0x28]	20640	1			T2	2		T6	277		T45	5
valid_sources[0x29]	20777	1			T24	3		T40	2		T16	2
valid_sources[0x2a]	22675	1			T2	1		T24	3		T45	2
valid_sources[0x2b]	19055	1			T4	8		T41	2		T82	1
valid_sources[0x2c]	22119	1			T2	1		T24	1		T11	1
valid_sources[0x2d]	20244	1			T41	2		T45	1		T40	1
valid_sources[0x2e]	22545	1			T2	1		T24	2		T4	27
valid_sources[0x2f]	21008	1			T3	1		T24	4		T4	1
valid_sources[0x30]	22335	1			T24	1		T82	1		T45	1
valid_sources[0x31]	20127	1			T2	1		T24	2		T82	1
valid_sources[0x32]	20583	1			T24	2		T15	1		T338	2
valid_sources[0x33]	19657	1			T3	1		T4	2		T11	2
valid_sources[0x34]	20793	1			T4	5		T72	1		T21	2
valid_sources[0x35]	21977	1			T2	1		T72	1		T21	3
valid_sources[0x36]	20280	1			T82	1		T21	1		T16	1
valid_sources[0x37]	22218	1			T3	2		T4	4		T45	1
valid_sources[0x38]	20689	1			T4	2		T11	1		T82	1
valid_sources[0x39]	20078	1			T24	4		T82	1		T45	1
valid_sources[0x3a]	20704	1			T2	1		T4	18		T45	1
valid_sources[0x3b]	22605	1			T24	2		T50	7		T72	1
valid_sources[0x3c]	20301	1			T10	94		T24	3		T4	4
valid_sources[0x3d]	20307	1			T3	2		T4	7		T45	1
valid_sources[0x3e]	19864	1			T24	3		T82	1		T45	2
valid_sources[0x3f]	20891	1			T2	4		T24	3		T45	1
valid_sources[0x40]	21335	1			T24	1		T4	5		T45	2
valid_sources[0x41]	19966	1			T2	2		T45	2		T15	1
valid_sources[0x42]	19076	1			T45	2		T40	2		T72	5
valid_sources[0x43]	21518	1			T24	1		T11	3		T45	1
valid_sources[0x44]	22070	1			T24	2		T4	11		T45	3
valid_sources[0x45]	19683	1			T82	3		T45	1		T15	1
valid_sources[0x46]	21007	1			T2	6		T45	4		T40	7
valid_sources[0x47]	20977	1			T2	2		T45	1		T40	1
valid_sources[0x48]	21160	1			T45	1		T40	1		T50	1
valid_sources[0x49]	21876	1			T3	1		T24	3		T4	6
valid_sources[0x4a]	22240	1			T3	1		T82	3		T50	1
valid_sources[0x4b]	21166	1			T2	4		T45	3		T40	1
valid_sources[0x4c]	21563	1			T2	1		T3	1		T45	3
valid_sources[0x4d]	22025	1			T2	4		T4	1		T11	1
valid_sources[0x4e]	22219	1			T26	56		T40	9		T50	2
valid_sources[0x4f]	20037	1			T2	1		T3	1		T24	4
valid_sources[0x50]	22156	1			T2	3		T82	2		T45	2
valid_sources[0x51]	19741	1			T24	2		T11	2		T82	1
valid_sources[0x52]	19094	1			T2	1		T4	7		T45	2
valid_sources[0x53]	18594	1			T2	1		T24	1		T82	1
valid_sources[0x54]	20166	1			T24	2		T12	97		T45	1
valid_sources[0x55]	19841	1			T4	5		T45	2		T15	1
valid_sources[0x56]	20793	1			T4	4		T45	1		T15	1
valid_sources[0x57]	19314	1			T24	1		T11	2		T50	2
valid_sources[0x58]	20052	1			T2	1		T24	1		T4	1
valid_sources[0x59]	22458	1			T82	1		T45	1		T40	1
valid_sources[0x5a]	19641	1			T4	3		T40	4		T50	1
valid_sources[0x5b]	21034	1			T24	1		T50	3		T21	1
valid_sources[0x5c]	19646	1			T15	1		T40	1		T50	2
valid_sources[0x5d]	20514	1			T2	1		T24	4		T11	2
valid_sources[0x5e]	20830	1			T2	2		T3	3		T45	2
valid_sources[0x5f]	22273	1			T24	1		T45	1		T40	1
valid_sources[0x60]	20012	1			T4	28		T82	1		T45	1
valid_sources[0x61]	22012	1			T40	1		T50	8		T16	1
valid_sources[0x62]	20846	1			T2	2		T24	1		T11	1
valid_sources[0x63]	21320	1			T45	2		T40	4		T50	11
valid_sources[0x64]	22307	1			T2	3		T24	3		T4	24
valid_sources[0x65]	22296	1			T4	8		T82	1		T45	3
valid_sources[0x66]	21803	1			T3	14		T24	3		T4	10
valid_sources[0x67]	22475	1			T2	2		T24	2		T45	1
valid_sources[0x68]	20183	1			T24	1		T4	7		T82	1
valid_sources[0x69]	20769	1			T40	2		T16	2		T283	2
valid_sources[0x6a]	19200	1			T2	1		T11	1		T40	3
valid_sources[0x6b]	21329	1			T3	1		T24	2		T82	1
valid_sources[0x6c]	20223	1			T2	1		T24	2		T82	1
valid_sources[0x6d]	22193	1			T45	2		T16	1		T57	1
valid_sources[0x6e]	20789	1			T24	1		T4	2		T45	2
valid_sources[0x6f]	20780	1			T24	4		T45	1		T15	1
valid_sources[0x70]	21147	1			T15	1		T40	3		T16	1
valid_sources[0x71]	21972	1			T24	2		T4	8		T82	2
valid_sources[0x72]	20789	1			T2	4		T24	3		T45	1
valid_sources[0x73]	22478	1			T2	1		T24	1		T4	8
valid_sources[0x74]	19409	1			T4	24		T11	2		T40	2
valid_sources[0x75]	21143	1			T2	2		T40	1		T47	5
valid_sources[0x76]	21410	1			T82	1		T45	2		T71	11
valid_sources[0x77]	21687	1			T4	42		T25	70		T11	2
valid_sources[0x78]	20038	1			T4	1		T45	2		T71	7
valid_sources[0x79]	20516	1			T2	1		T4	10		T45	1
valid_sources[0x7a]	22173	1			T2	2		T82	1		T45	2
valid_sources[0x7b]	20704	1			T2	6		T3	1		T15	1
valid_sources[0x7c]	21163	1			T82	2		T45	2		T21	1
valid_sources[0x7d]	20873	1			T24	2		T4	1		T11	1
valid_sources[0x7e]	21166	1			T2	2		T24	1		T4	4
valid_sources[0x7f]	22878	1			T24	1		T4	1		T40	2
valid_sources[0x80]	20601	1			T45	1		T40	3		T72	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1198039

1

T1

3

T2

6

T3

14

values[0x0]

all_enables

biggest_size

1776648

1

T1

13

T2

14

T3

17

values[0x1]

all_enables

biggest_size

1773764

1

T1

16

T2

11

T3

17