Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2599	1			T1	2		T2	2		T10	3
non_zero_bins[1]	1821	1			T1	1		T2	1		T10	1
zero	9166	1			T1	4		T2	4		T3	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	465	1			T1	1		T24	1		T4	1
uni	3608	1			T1	2		T2	2		T23	1
gen	4299	1			T1	2		T2	2		T3	3
res	858	1			T2	1		T10	2		T4	1
ins	4356	1			T1	2		T2	2		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8896

1

T1

3

T2

4

T3

2

mubi_true

4690

1

T1

4

T2

3

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

39

1

T94

1

T89

1

T100

1

pass

13547

1

T1

7

T2

7

T3

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	102	1			T281	1		T96	2		T37	2
upd	non_zero_bins[0]	pass	mubi_true	123	1			T1	1		T50	1		T60	1
upd	non_zero_bins[1]	pass	mubi_false	59	1			T24	1		T97	1		T282	1
upd	non_zero_bins[1]	pass	mubi_true	89	1			T283	1		T37	5		T39	2
upd	zero	pass	mubi_false	40	1			T70	1		T39	1		T99	1
upd	zero	pass	mubi_true	52	1			T4	1		T37	2		T38	2
uni	zero	pass	mubi_false	2628	1			T1	2		T2	2		T10	1
uni	zero	pass	mubi_true	980	1			T23	1		T4	7		T50	1
gen	non_zero_bins[0]	pass	mubi_false	456	1			T4	1		T71	1		T15	4
gen	non_zero_bins[0]	pass	mubi_true	525	1			T2	1		T10	1		T4	1
gen	non_zero_bins[1]	pass	mubi_false	362	1			T1	1		T24	1		T4	1
gen	non_zero_bins[1]	pass	mubi_true	308	1			T6	1		T50	1		T58	1
gen	zero	fail	mubi_false	33	1			T94	1		T89	1		T100	1
gen	zero	pass	mubi_false	1861	1			T2	1		T3	1		T23	1
gen	zero	pass	mubi_true	754	1			T1	1		T3	2		T26	2
res	non_zero_bins[0]	pass	mubi_false	185	1			T45	1		T40	1		T72	1
res	non_zero_bins[0]	pass	mubi_true	175	1			T10	2		T4	1		T25	1
res	non_zero_bins[1]	pass	mubi_false	152	1			T2	1		T82	1		T15	1
res	non_zero_bins[1]	pass	mubi_true	160	1			T12	2		T15	3		T97	1
res	zero	fail	mubi_false	6	1			T158	1		T159	1		T160	1
res	zero	pass	mubi_false	102	1			T71	1		T48	1		T37	3
res	zero	pass	mubi_true	78	1			T97	1		T37	1		T284	2
ins	non_zero_bins[0]	pass	mubi_false	533	1			T4	1		T40	1		T50	1
ins	non_zero_bins[0]	pass	mubi_true	500	1			T1	1		T2	1		T4	1
ins	non_zero_bins[1]	pass	mubi_false	334	1			T4	1		T25	1		T6	1
ins	non_zero_bins[1]	pass	mubi_true	357	1			T10	1		T4	1		T82	1
ins	zero	pass	mubi_false	2043	1			T3	1		T23	1		T24	1
ins	zero	pass	mubi_true	589	1			T1	1		T2	1		T3	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded