Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T86,T32
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T61,T7
1	1	Covered	T3,T10,T11

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T26,T11
1	0	Covered	T16,T7,T32

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T3,T26,T11
1	Covered	T16,T7,T32

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T3,T26,T11
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T3,T26,T11
1	Covered	T16,T7,T32

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T26,T11

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T10,T12,T15
AutoCaptGenCnt	143	Covered	T10,T11,T12
AutoCaptReseedCnt	141	Covered	T10,T12,T15
AutoDispatch	125	Covered	T10,T11,T12
AutoFirstAckWait	119	Covered	T10,T11,T12
AutoLoadIns	69	Covered	T3,T10,T11
AutoSendGenCmd	150	Covered	T10,T12,T15
AutoSendReseedCmd	162	Covered	T10,T12,T15
BootDone	98	Covered	T1,T2,T3
BootGenAckWait	90	Covered	T1,T2,T3
BootInsAckWait	80	Covered	T1,T2,T3
BootLoadGen	85	Covered	T1,T2,T3
BootLoadIns	65	Covered	T1,T2,T3
BootLoadUni	102	Covered	T1,T2,T3
BootPulse	94	Covered	T1,T2,T3
BootUniAckWait	107	Covered	T1,T2,T26
Error	188	Covered	T16,T7,T32
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T3,T26,T11
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T10,T12,T15
AutoAckWait->Error	188	Covered	T116
AutoAckWait->Idle	211	Covered	T15,T61,T22
AutoAckWait->RejectCsrngEntropy	188	Covered	T48,T100,T117
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T10,T12,T15
AutoCaptGenCnt->Error	188	Covered	T9,T118
AutoCaptGenCnt->Idle	211	Covered	T119,T120,T121
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T11,T122,T123
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T10,T12,T15
AutoCaptReseedCnt->Error	188	Covered	T56,T124,T125
AutoCaptReseedCnt->Idle	211	Covered	T126,T127,T128
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T129,T130,T131
AutoDispatch->AutoCaptGenCnt	143	Covered	T10,T11,T12
AutoDispatch->AutoCaptReseedCnt	141	Covered	T10,T12,T15
AutoDispatch->Error	188	Covered	T132,T133,T134
AutoDispatch->Idle	138	Covered	T10,T12,T21
AutoDispatch->RejectCsrngEntropy	188	Covered	T105,T135,T136
AutoFirstAckWait->AutoDispatch	125	Covered	T10,T11,T12
AutoFirstAckWait->Error	188	Covered	T137,T138,T139
AutoFirstAckWait->Idle	211	Covered	T61,T88,T140
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T83,T141,T142
AutoLoadIns->AutoFirstAckWait	119	Covered	T10,T11,T12
AutoLoadIns->Error	188	Covered	T143,T144,T145
AutoLoadIns->Idle	211	Covered	T3,T7,T83
AutoLoadIns->RejectCsrngEntropy	188	Covered	T47,T78,T146
AutoSendGenCmd->AutoAckWait	156	Covered	T10,T12,T15
AutoSendGenCmd->Error	188	Covered	T147,T111,T148
AutoSendGenCmd->Idle	211	Covered	T149,T150,T151
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T106,T109,T152
AutoSendReseedCmd->AutoAckWait	168	Covered	T10,T12,T15
AutoSendReseedCmd->Error	188	Covered	T153,T154
AutoSendReseedCmd->Idle	211	Covered	T155,T156,T157
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T158,T159,T160
BootDone->BootLoadUni	102	Covered	T1,T2,T3
BootDone->Error	188	Covered	T161,T162,T163
BootDone->Idle	211	Covered	T164,T165,T166
BootDone->RejectCsrngEntropy	188	Covered	T167,T168,T169
BootGenAckWait->BootPulse	94	Covered	T1,T2,T3
BootGenAckWait->Error	188	Covered	T170,T171,T172
BootGenAckWait->Idle	211	Covered	T41,T84,T81
BootGenAckWait->RejectCsrngEntropy	188	Covered	T26,T94,T103
BootInsAckWait->BootLoadGen	85	Covered	T1,T2,T3
BootInsAckWait->Error	188	Covered	T69,T173,T174
BootInsAckWait->Idle	211	Covered	T32,T67,T173
BootInsAckWait->RejectCsrngEntropy	188	Covered	T104,T112,T175
BootLoadGen->BootGenAckWait	90	Covered	T1,T2,T3
BootLoadGen->Error	188	Covered	T176,T177,T178
BootLoadGen->Idle	211	Covered	T77,T69,T179
BootLoadGen->RejectCsrngEntropy	188	Covered	T180,T107,T181
BootLoadIns->BootInsAckWait	80	Covered	T1,T2,T3
BootLoadIns->Error	188	Covered	T67,T182,T183
BootLoadIns->Idle	211	Covered	T86,T184,T185
BootLoadIns->RejectCsrngEntropy	188	Covered	T80,T186,T187
BootLoadUni->BootUniAckWait	107	Covered	T1,T2,T26
BootLoadUni->Error	188	Covered	T188,T189
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T3,T98,T190
BootPulse->BootDone	98	Covered	T1,T2,T3
BootPulse->Error	188	Covered	T32,T191,T192
BootPulse->Idle	211	Covered	T193,T194,T195
BootPulse->RejectCsrngEntropy	188	Covered	T196,T197,T198
BootUniAckWait->Error	188	Not Covered
BootUniAckWait->Idle	112	Covered	T1,T2,T26
BootUniAckWait->RejectCsrngEntropy	188	Covered	T87,T101,T199
Idle->AutoLoadIns	69	Covered	T3,T10,T11
Idle->BootLoadIns	65	Covered	T1,T2,T3
Idle->Error	188	Covered	T16,T19,T20
Idle->RejectCsrngEntropy	188	Covered	T98,T48,T80
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T200,T201
RejectCsrngEntropy->Idle	211	Covered	T3,T26,T11
SWPortMode->Error	188	Covered	T16,T17,T18
SWPortMode->Idle	211	Covered	T4,T11,T5
SWPortMode->RejectCsrngEntropy	188	Covered	T3,T26,T11

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T26,T41,T47
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T70
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T26
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T10,T11,T12
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T10,T11,T12
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T10,T11,T12
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T10,T12,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T10,T12,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T12,T21
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T10,T12,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T10,T11,T12
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T10,T12,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T10,T12,T15
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T12,T15
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T12,T15
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T26,T11
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T32
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T7,T68

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T16,T7,T32
1	0	1	-	Not Covered
1	0	0	-	Covered	T3,T26,T11
0	-	-	1	Covered	T3,T26,T11
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	191912577	151162	0	0
FpvSecCmErrorStEscalate_A	191912577	152205	0	0
u_state_regs_A	191868999	191689376	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	151162	0	0
T7	2270	1051	0	0
T8	0	314	0	0
T16	27785	9812	0	0
T17	0	632	0	0
T18	0	1110	0	0
T32	0	200	0	0
T42	2073	0	0	0
T51	0	602	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T67	0	1110	0	0
T68	0	181	0	0
T69	0	1117	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	152205	0	0
T7	2270	1052	0	0
T8	0	315	0	0
T16	27785	9942	0	0
T17	0	633	0	0
T18	0	1111	0	0
T32	0	201	0	0
T42	2073	0	0	0
T51	0	603	0	0
T57	1161	0	0	0
T58	2264	0	0	0
T59	1673	0	0	0
T60	4123	0	0	0
T61	2312	0	0	0
T62	1161	0	0	0
T63	1253	0	0	0
T67	0	1111	0	0
T68	0	182	0	0
T69	0	1118	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191868999	191689376	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0