Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T35,T91
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T30,T36
1	0	1	Covered	T3,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	383062076	1545865	0	0
DepthKnown_A	383825154	383465908	0	0
RvalidKnown_A	383825154	383465908	0	0
WreadyKnown_A	383825154	383465908	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	383434932	1641331	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383062076	1545865	0	0
T3	5000	267	0	0
T4	39116	0	0	0
T7	0	238	0	0
T10	8098	3692	0	0
T11	4296	562	0	0
T12	0	2222	0	0
T15	0	3453	0	0
T21	0	2857	0	0
T23	3520	0	0	0
T24	7998	0	0	0
T25	4820	0	0	0
T26	3712	0	0	0
T41	2004	0	0	0
T47	0	337	0	0
T48	0	589	0	0
T61	0	2314	0	0
T82	4492	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383825154	383465908	0	0
T1	5718	5548	0	0
T2	4584	4402	0	0
T3	5000	4802	0	0
T4	39116	38044	0	0
T10	8098	7924	0	0
T11	4296	4166	0	0
T23	3520	3400	0	0
T24	7998	7834	0	0
T25	4820	4652	0	0
T26	3712	3542	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383825154	383465908	0	0
T1	5718	5548	0	0
T2	4584	4402	0	0
T3	5000	4802	0	0
T4	39116	38044	0	0
T10	8098	7924	0	0
T11	4296	4166	0	0
T23	3520	3400	0	0
T24	7998	7834	0	0
T25	4820	4652	0	0
T26	3712	3542	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383825154	383465908	0	0
T1	5718	5548	0	0
T2	4584	4402	0	0
T3	5000	4802	0	0
T4	39116	38044	0	0
T10	8098	7924	0	0
T11	4296	4166	0	0
T23	3520	3400	0	0
T24	7998	7834	0	0
T25	4820	4652	0	0
T26	3712	3542	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	383434932	1641331	0	0
T3	5000	267	0	0
T4	39116	0	0	0
T7	0	1785	0	0
T10	8098	3692	0	0
T11	4296	562	0	0
T12	0	2222	0	0
T15	0	3453	0	0
T21	0	2857	0	0
T23	3520	0	0	0
T24	7998	0	0	0
T25	4820	0	0	0
T26	3712	0	0	0
T41	2004	0	0	0
T47	0	337	0	0
T48	0	589	0	0
T61	0	2314	0	0
T82	4492	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T22,T88
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T36
1	0	1	Covered	T3,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T10,T12,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	191531038	767182	0	0
DepthKnown_A	191912577	191732954	0	0
RvalidKnown_A	191912577	191732954	0	0
WreadyKnown_A	191912577	191732954	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	191717466	814797	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191531038	767182	0	0
T3	2500	127	0	0
T4	19558	0	0	0
T7	0	104	0	0
T10	4049	1839	0	0
T11	2148	286	0	0
T12	0	1092	0	0
T15	0	1706	0	0
T21	0	1430	0	0
T23	1760	0	0	0
T24	3999	0	0	0
T25	2410	0	0	0
T26	1856	0	0	0
T41	1002	0	0	0
T47	0	174	0	0
T48	0	299	0	0
T61	0	1133	0	0
T82	2246	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	191717466	814797	0	0
T3	2500	127	0	0
T4	19558	0	0	0
T7	0	841	0	0
T10	4049	1839	0	0
T11	2148	286	0	0
T12	0	1092	0	0
T15	0	1706	0	0
T21	0	1430	0	0
T23	1760	0	0	0
T24	3999	0	0	0
T25	2410	0	0	0
T26	1856	0	0	0
T41	1002	0	0	0
T47	0	174	0	0
T48	0	299	0	0
T61	0	1133	0	0
T82	2246	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T91
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T92,T93
1	0	1	Covered	T3,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T10,T11,T12

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	191531038	778683	0	0
DepthKnown_A	191912577	191732954	0	0
RvalidKnown_A	191912577	191732954	0	0
WreadyKnown_A	191912577	191732954	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	191717466	826534	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191531038	778683	0	0
T3	2500	140	0	0
T4	19558	0	0	0
T7	0	134	0	0
T10	4049	1853	0	0
T11	2148	276	0	0
T12	0	1130	0	0
T15	0	1747	0	0
T21	0	1427	0	0
T23	1760	0	0	0
T24	3999	0	0	0
T25	2410	0	0	0
T26	1856	0	0	0
T41	1002	0	0	0
T47	0	163	0	0
T48	0	290	0	0
T61	0	1181	0	0
T82	2246	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191912577	191732954	0	0
T1	2859	2774	0	0
T2	2292	2201	0	0
T3	2500	2401	0	0
T4	19558	19022	0	0
T10	4049	3962	0	0
T11	2148	2083	0	0
T23	1760	1700	0	0
T24	3999	3917	0	0
T25	2410	2326	0	0
T26	1856	1771	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	191717466	826534	0	0
T3	2500	140	0	0
T4	19558	0	0	0
T7	0	944	0	0
T10	4049	1853	0	0
T11	2148	276	0	0
T12	0	1130	0	0
T15	0	1747	0	0
T21	0	1427	0	0
T23	1760	0	0	0
T24	3999	0	0	0
T25	2410	0	0	0
T26	1856	0	0	0
T41	1002	0	0	0
T47	0	163	0	0
T48	0	290	0	0
T61	0	1181	0	0
T82	2246	0	0	0