Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148980	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

316273

1

T1

27

T2

68

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	196743	1			T1	49		T2	22		T3	20
values[0x0]	126773	1			T1	12		T2	35		T3	4
values[0x1]	141737	1			T1	14		T2	36		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	99799	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

365454

1

T1

43

T2

80

T3

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1485	1			T46	2		T43	3		T69	3
valid_sources[0x01]	2086	1			T1	3		T3	2		T47	3
valid_sources[0x02]	1431	1			T31	2		T30	2		T47	2
valid_sources[0x03]	1842	1			T2	2		T4	1		T43	2
valid_sources[0x04]	2005	1			T1	1		T31	1		T38	163
valid_sources[0x05]	2822	1			T2	1		T46	1		T39	69
valid_sources[0x06]	1805	1			T43	1		T47	1		T205	4
valid_sources[0x07]	1880	1			T2	1		T47	1		T39	93
valid_sources[0x08]	1629	1			T2	1		T46	1		T43	1
valid_sources[0x09]	1562	1			T24	3		T43	1		T39	65
valid_sources[0x0a]	1518	1			T2	1		T4	1		T46	1
valid_sources[0x0b]	1486	1			T2	1		T3	1		T30	1
valid_sources[0x0c]	1867	1			T85	1		T83	5		T46	1
valid_sources[0x0d]	1514	1			T3	1		T4	1		T85	8
valid_sources[0x0e]	2248	1			T46	3		T5	1		T43	1
valid_sources[0x0f]	1681	1			T3	1		T4	1		T31	1
valid_sources[0x10]	1709	1			T2	2		T3	1		T24	3
valid_sources[0x11]	1510	1			T2	1		T83	2		T43	1
valid_sources[0x12]	1370	1			T2	1		T29	1		T84	1
valid_sources[0x13]	1813	1			T44	8		T38	1		T39	71
valid_sources[0x14]	1637	1			T2	2		T3	1		T4	1
valid_sources[0x15]	1591	1			T46	1		T43	1		T47	6
valid_sources[0x16]	1595	1			T43	3		T47	4		T205	1
valid_sources[0x17]	1459	1			T2	1		T4	1		T92	2
valid_sources[0x18]	1521	1			T2	1		T85	2		T42	4
valid_sources[0x19]	1724	1			T42	1		T84	1		T46	1
valid_sources[0x1a]	2191	1			T24	1		T30	3		T38	255
valid_sources[0x1b]	1930	1			T47	1		T205	1		T38	285
valid_sources[0x1c]	1909	1			T30	2		T47	2		T69	1
valid_sources[0x1d]	1333	1			T2	1		T30	1		T43	1
valid_sources[0x1e]	1830	1			T3	1		T30	2		T47	2
valid_sources[0x1f]	2187	1			T4	1		T46	3		T69	1
valid_sources[0x20]	1634	1			T2	1		T3	2		T85	1
valid_sources[0x21]	2457	1			T4	1		T26	4		T43	2
valid_sources[0x22]	1369	1			T86	1		T43	1		T47	2
valid_sources[0x23]	1572	1			T1	1		T2	1		T82	1
valid_sources[0x24]	1933	1			T47	1		T39	95		T33	1
valid_sources[0x25]	1622	1			T25	2		T30	1		T84	1
valid_sources[0x26]	1907	1			T4	1		T42	2		T46	2
valid_sources[0x27]	2487	1			T25	1		T46	1		T43	1
valid_sources[0x28]	1670	1			T86	1		T47	7		T39	67
valid_sources[0x29]	1913	1			T4	2		T82	1		T39	96
valid_sources[0x2a]	1440	1			T4	1		T42	1		T46	3
valid_sources[0x2b]	1659	1			T46	1		T47	2		T15	28
valid_sources[0x2c]	2577	1			T46	1		T43	1		T47	4
valid_sources[0x2d]	1821	1			T2	1		T92	2		T86	1
valid_sources[0x2e]	1547	1			T3	2		T68	2		T69	2
valid_sources[0x2f]	1713	1			T30	5		T47	8		T39	71
valid_sources[0x30]	1497	1			T43	1		T47	1		T69	3
valid_sources[0x31]	1737	1			T2	1		T3	2		T43	1
valid_sources[0x32]	1553	1			T46	1		T47	1		T39	73
valid_sources[0x33]	1811	1			T3	1		T46	1		T43	2
valid_sources[0x34]	2142	1			T46	1		T43	1		T47	1
valid_sources[0x35]	1532	1			T47	2		T39	67		T302	1
valid_sources[0x36]	1461	1			T1	4		T30	2		T5	1
valid_sources[0x37]	2777	1			T2	2		T114	1		T39	74
valid_sources[0x38]	1644	1			T30	1		T6	2		T38	92
valid_sources[0x39]	2244	1			T2	1		T85	1		T43	1
valid_sources[0x3a]	1941	1			T2	1		T4	1		T31	5
valid_sources[0x3b]	2667	1			T2	2		T42	1		T43	2
valid_sources[0x3c]	1304	1			T82	2		T30	1		T46	2
valid_sources[0x3d]	1408	1			T4	1		T44	5		T64	1
valid_sources[0x3e]	1523	1			T1	1		T2	2		T85	3
valid_sources[0x3f]	1770	1			T46	3		T47	4		T39	68
valid_sources[0x40]	1704	1			T46	1		T47	1		T205	1
valid_sources[0x41]	1778	1			T46	2		T6	1		T43	1
valid_sources[0x42]	1664	1			T4	1		T25	1		T30	1
valid_sources[0x43]	1357	1			T30	1		T43	3		T47	2
valid_sources[0x44]	1541	1			T2	2		T25	1		T42	1
valid_sources[0x45]	2225	1			T2	1		T25	1		T92	1
valid_sources[0x46]	1950	1			T43	1		T69	1		T39	74
valid_sources[0x47]	1544	1			T1	3		T24	4		T25	1
valid_sources[0x48]	1654	1			T30	5		T42	7		T43	2
valid_sources[0x49]	2066	1			T2	1		T30	4		T42	1
valid_sources[0x4a]	1868	1			T25	1		T46	1		T43	3
valid_sources[0x4b]	1877	1			T43	1		T47	4		T205	1
valid_sources[0x4c]	1322	1			T47	1		T69	2		T39	72
valid_sources[0x4d]	1833	1			T85	2		T43	1		T47	4
valid_sources[0x4e]	2494	1			T46	1		T5	1		T43	1
valid_sources[0x4f]	1553	1			T84	1		T46	1		T5	1
valid_sources[0x50]	1524	1			T46	1		T47	4		T39	49
valid_sources[0x51]	1828	1			T82	1		T41	1		T47	1
valid_sources[0x52]	1841	1			T1	1		T2	1		T26	1
valid_sources[0x53]	1686	1			T4	1		T25	1		T45	67
valid_sources[0x54]	2055	1			T46	2		T47	9		T205	5
valid_sources[0x55]	1879	1			T85	2		T31	1		T39	65
valid_sources[0x56]	1993	1			T1	1		T43	1		T47	1
valid_sources[0x57]	1551	1			T4	1		T84	2		T46	1
valid_sources[0x58]	1826	1			T2	1		T3	1		T42	1
valid_sources[0x59]	1489	1			T2	1		T47	2		T39	72
valid_sources[0x5a]	1655	1			T2	1		T4	1		T6	2
valid_sources[0x5b]	1539	1			T25	1		T31	1		T43	1
valid_sources[0x5c]	1552	1			T24	3		T42	5		T5	1
valid_sources[0x5d]	1638	1			T31	3		T46	1		T92	1
valid_sources[0x5e]	2308	1			T43	1		T47	1		T69	1
valid_sources[0x5f]	1615	1			T2	2		T42	1		T43	2
valid_sources[0x60]	1861	1			T46	1		T92	7		T43	2
valid_sources[0x61]	2097	1			T25	1		T5	1		T39	79
valid_sources[0x62]	1771	1			T4	2		T205	3		T39	78
valid_sources[0x63]	1566	1			T4	1		T25	1		T92	2
valid_sources[0x64]	1945	1			T1	1		T4	1		T86	1
valid_sources[0x65]	1849	1			T31	4		T30	1		T84	1
valid_sources[0x66]	2628	1			T24	3		T30	1		T42	1
valid_sources[0x67]	2688	1			T2	1		T4	1		T46	1
valid_sources[0x68]	2022	1			T43	1		T64	10		T39	91
valid_sources[0x69]	1700	1			T29	1		T38	128		T39	53
valid_sources[0x6a]	1590	1			T31	1		T46	1		T47	2
valid_sources[0x6b]	2264	1			T1	1		T3	1		T30	2
valid_sources[0x6c]	2299	1			T4	1		T84	1		T47	1
valid_sources[0x6d]	1463	1			T4	1		T6	1		T43	4
valid_sources[0x6e]	1289	1			T4	1		T46	1		T39	75
valid_sources[0x6f]	1618	1			T2	1		T30	2		T46	1
valid_sources[0x70]	1275	1			T85	6		T30	2		T43	1
valid_sources[0x71]	2704	1			T1	1		T2	1		T92	2
valid_sources[0x72]	1889	1			T43	2		T38	167		T39	74
valid_sources[0x73]	2060	1			T2	1		T11	190		T46	1
valid_sources[0x74]	1861	1			T2	1		T3	1		T43	2
valid_sources[0x75]	2031	1			T5	1		T47	10		T39	71
valid_sources[0x76]	1823	1			T2	1		T84	2		T43	2
valid_sources[0x77]	1599	1			T25	1		T39	84		T118	1
valid_sources[0x78]	1577	1			T4	1		T46	3		T68	1
valid_sources[0x79]	2180	1			T1	1		T2	1		T30	3
valid_sources[0x7a]	1969	1			T2	1		T30	2		T46	2
valid_sources[0x7b]	1493	1			T1	2		T24	2		T46	1
valid_sources[0x7c]	1480	1			T30	1		T42	1		T47	2
valid_sources[0x7d]	1782	1			T2	2		T82	4		T85	4
valid_sources[0x7e]	1815	1			T1	1		T31	1		T30	2
valid_sources[0x7f]	2482	1			T24	1		T26	1		T46	2
valid_sources[0x80]	1696	1			T3	1		T85	1		T31	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

85792

1

T1

10

T2

1

T3

4

values[0x0]

all_enables

biggest_size

116078

1

T1

9

T2

32

T3

3

values[0x1]

all_enables

biggest_size

114403

1

T1

8

T2

35

T3

3