Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
60.94	60.94	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	60.94	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
60.94	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	25	27	51.92

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	25	27	51.92	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1701	1			T2	3		T24	2		T11	14
non_zero_bins[1]	1222	1			T2	1		T14	6		T11	1
zero	6093	1			T1	4		T2	5		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	270	1			T30	1		T46	1		T205	1
uni	2119	1			T3	1		T24	2		T11	1
gen	3095	1			T1	2		T2	3		T3	1
res	655	1			T2	5		T24	1		T10	1
ins	2877	1			T1	2		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5722

1

T1

1

T2

5

T3

3

mubi_true

3294

1

T1

3

T2

4

T24

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

35

1

T300

1

T301

1

T116

1

pass

8981

1

T1

4

T2

9

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	25	27	51.92	25
Automatically Generated Cross Bins	52	25	27	51.92	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4
[res , ins]	*	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen]	[zero]	[fail]	[mubi_true]	0	1	1

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	67	1			T46	1		T67	1		T39	2
upd	non_zero_bins[0]	pass	mubi_true	66	1			T30	1		T205	1		T38	3
upd	non_zero_bins[1]	pass	mubi_false	34	1			T39	2		T112	1		T75	1
upd	non_zero_bins[1]	pass	mubi_true	59	1			T69	1		T39	2		T302	1
upd	zero	pass	mubi_false	19	1			T75	1		T76	2		T254	1
upd	zero	pass	mubi_true	25	1			T39	2		T40	2		T112	1
uni	zero	pass	mubi_false	1601	1			T3	1		T24	2		T11	1
uni	zero	pass	mubi_true	518	1			T45	1		T86	1		T43	1
gen	non_zero_bins[0]	pass	mubi_false	304	1			T24	1		T11	1		T205	1
gen	non_zero_bins[0]	pass	mubi_true	364	1			T2	3		T11	13		T46	1
gen	non_zero_bins[1]	pass	mubi_false	276	1			T14	3		T38	1		T39	3
gen	non_zero_bins[1]	pass	mubi_true	212	1			T30	1		T47	1		T38	2
gen	zero	fail	mubi_false	35	1			T300	1		T301	1		T116	1
gen	zero	pass	mubi_false	1214	1			T3	1		T4	1		T24	1
gen	zero	pass	mubi_true	690	1			T1	2		T10	2		T31	2
res	non_zero_bins[0]	pass	mubi_false	135	1			T24	1		T38	1		T39	1
res	non_zero_bins[0]	pass	mubi_true	141	1			T38	1		T39	1		T119	2
res	non_zero_bins[1]	pass	mubi_false	104	1			T14	3		T39	1		T21	2
res	non_zero_bins[1]	pass	mubi_true	97	1			T38	2		T40	1		T303	1
res	zero	pass	mubi_false	104	1			T2	5		T10	1		T29	1
res	zero	pass	mubi_true	74	1			T11	2		T65	2		T40	1
ins	non_zero_bins[0]	pass	mubi_false	322	1			T30	1		T46	1		T43	1
ins	non_zero_bins[0]	pass	mubi_true	302	1			T43	1		T47	1		T38	7
ins	non_zero_bins[1]	pass	mubi_false	217	1			T11	1		T38	4		T39	8
ins	non_zero_bins[1]	pass	mubi_true	223	1			T2	1		T47	1		T38	3
ins	zero	pass	mubi_false	1290	1			T1	1		T3	1		T4	1
ins	zero	pass	mubi_true	523	1			T1	1		T24	1		T10	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded