Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T41,T5,T6
1	1	Covered	T24,T29,T30

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T14,T7
1	1	Covered	T1,T2,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T31
1	0	Covered	T5,T6,T15

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T1,T10,T31
1	Covered	T5,T6,T15

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T10,T31
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T10,T31
1	Covered	T5,T6,T15

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T10,T14
AutoCaptGenCnt	143	Covered	T1,T2,T10
AutoCaptReseedCnt	141	Covered	T2,T10,T14
AutoDispatch	125	Covered	T1,T2,T10
AutoFirstAckWait	119	Covered	T1,T2,T10
AutoLoadIns	69	Covered	T1,T2,T10
AutoSendGenCmd	150	Covered	T2,T10,T14
AutoSendReseedCmd	162	Covered	T2,T10,T14
BootDone	98	Covered	T24,T29,T30
BootGenAckWait	90	Covered	T24,T29,T30
BootInsAckWait	80	Covered	T24,T29,T30
BootLoadGen	85	Covered	T24,T29,T30
BootLoadIns	65	Covered	T24,T29,T30
BootLoadUni	102	Covered	T24,T29,T30
BootPulse	94	Covered	T24,T29,T30
BootUniAckWait	107	Covered	T24,T29,T30
Error	188	Covered	T5,T6,T15
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T1,T10,T31
SWPortMode	74	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T2,T10,T14
AutoAckWait->Error	188	Covered	T122,T123,T124
AutoAckWait->Idle	211	Covered	T2,T14,T21
AutoAckWait->RejectCsrngEntropy	188	Covered	T10,T29,T56
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T10,T14
AutoCaptGenCnt->Error	188	Covered	T8,T125,T126
AutoCaptGenCnt->Idle	211	Covered	T127,T128,T129
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T1,T130,T131
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T2,T10,T14
AutoCaptReseedCnt->Error	188	Covered	T132
AutoCaptReseedCnt->Idle	211	Covered	T133,T134,T135
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T136,T137,T138
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T2,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T2,T10,T14
AutoDispatch->Error	188	Covered	T139
AutoDispatch->Idle	138	Covered	T11,T65,T119
AutoDispatch->RejectCsrngEntropy	188	Covered	T140,T141,T142
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T2,T10
AutoFirstAckWait->Error	188	Covered	T143,T144,T145
AutoFirstAckWait->Idle	211	Covered	T2,T14,T22
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T31,T146,T147
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T2,T10
AutoLoadIns->Error	188	Covered	T9,T148,T149
AutoLoadIns->Idle	211	Covered	T105,T7,T117
AutoLoadIns->RejectCsrngEntropy	188	Covered	T150,T151,T152
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T10,T14
AutoSendGenCmd->Error	188	Covered	T153,T154,T155
AutoSendGenCmd->Idle	211	Covered	T156,T157,T158
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T44,T90,T159
AutoSendReseedCmd->AutoAckWait	168	Covered	T2,T10,T14
AutoSendReseedCmd->Error	188	Not Covered
AutoSendReseedCmd->Idle	211	Covered	T21,T160,T161
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T42,T104
BootDone->BootLoadUni	102	Covered	T24,T29,T30
BootDone->Error	188	Covered	T162,T163,T164
BootDone->Idle	211	Covered	T41,T94,T165
BootDone->RejectCsrngEntropy	188	Covered	T166,T98,T91
BootGenAckWait->BootPulse	94	Covered	T24,T29,T30
BootGenAckWait->Error	188	Covered	T167,T168
BootGenAckWait->Idle	211	Covered	T169,T54,T170
BootGenAckWait->RejectCsrngEntropy	188	Covered	T105,T114,T117
BootInsAckWait->BootLoadGen	85	Covered	T24,T29,T30
BootInsAckWait->Error	188	Covered	T171,T172,T173
BootInsAckWait->Idle	211	Covered	T5,T6,T52
BootInsAckWait->RejectCsrngEntropy	188	Covered	T92,T99,T174
BootLoadGen->BootGenAckWait	90	Covered	T24,T29,T30
BootLoadGen->Error	188	Covered	T175,T176
BootLoadGen->Idle	211	Covered	T177,T178,T179
BootLoadGen->RejectCsrngEntropy	188	Covered	T118,T100,T180
BootLoadIns->BootInsAckWait	80	Covered	T24,T29,T30
BootLoadIns->Error	188	Covered	T169,T181,T182
BootLoadIns->Idle	211	Covered	T102,T103
BootLoadIns->RejectCsrngEntropy	188	Covered	T183,T184,T185
BootLoadUni->BootUniAckWait	107	Covered	T24,T29,T30
BootLoadUni->Error	188	Covered	T170,T186
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T187,T188,T189
BootPulse->BootDone	98	Covered	T24,T29,T30
BootPulse->Error	188	Covered	T16,T190,T191
BootPulse->Idle	211	Covered	T192,T193,T194
BootPulse->RejectCsrngEntropy	188	Covered	T195,T196,T197
BootUniAckWait->Error	188	Covered	T198,T199,T200
BootUniAckWait->Idle	112	Covered	T24,T29,T30
BootUniAckWait->RejectCsrngEntropy	188	Covered	T58,T115,T201
Idle->AutoLoadIns	69	Covered	T1,T2,T10
Idle->BootLoadIns	65	Covered	T24,T29,T30
Idle->Error	188	Covered	T18,T19,T20
Idle->RejectCsrngEntropy	188	Covered	T31,T42,T114
Idle->SWPortMode	74	Covered	T1,T3,T4
RejectCsrngEntropy->Error	188	Covered	T202,T203,T204
RejectCsrngEntropy->Idle	211	Covered	T1,T10,T31
SWPortMode->Error	188	Covered	T15,T17,T57
SWPortMode->Idle	211	Covered	T1,T4,T10
SWPortMode->RejectCsrngEntropy	188	Covered	T1,T10,T29

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T29,T30
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T29,T30
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T29,T30
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T24,T29,T30
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T29,T30
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T24,T29,T30
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T24,T29,T30
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T29,T30
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T29,T30
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T29,T41,T58
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T29,T30
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T24,T30,T46
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T24,T29,T30
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T10,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T11,T65,T119
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T2,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T10,T14
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T10,T14
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T31
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T66

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T5,T6,T15
1	0	1	-	Not Covered
1	0	0	-	Covered	T1,T10,T31
0	-	-	1	Covered	T1,T2,T4
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	11672832	145935	0	0
FpvSecCmErrorStEscalate_A	11672832	146853	0	0
u_state_regs_A	11634446	11469776	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	145935	0	0
T5	1233	603	0	0
T6	1070	560	0	0
T7	0	1108	0	0
T15	1440	650	0	0
T16	0	602	0	0
T17	0	598	0	0
T43	1746	0	0	0
T47	2088	0	0	0
T52	847	0	0	0
T57	0	487	0	0
T64	939	0	0	0
T66	0	400	0	0
T87	0	1082	0	0
T102	876	0	0	0
T105	2948	0	0	0
T108	0	610	0	0
T205	1932	0	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	146853	0	0
T5	1233	604	0	0
T6	1070	561	0	0
T7	0	1109	0	0
T15	1440	651	0	0
T16	0	603	0	0
T17	0	599	0	0
T43	1746	0	0	0
T47	2088	0	0	0
T52	847	0	0	0
T57	0	488	0	0
T64	939	0	0	0
T66	0	401	0	0
T87	0	1083	0	0
T102	876	0	0	0
T105	2948	0	0	0
T108	0	611	0	0
T205	1932	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11634446	11469776	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	1990	1847	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0