Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.20	100.00	90.59			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T35
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T36,T37
1	0	1	Covered	T1,T2,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	22572522	1065790	0	0
DepthKnown_A	23345664	23016324	0	0
RvalidKnown_A	23345664	23016324	0	0
WreadyKnown_A	23345664	23016324	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	22934592	1156609	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22572522	1065790	0	0
T1	4438	470	0	0
T2	7054	5113	0	0
T3	3930	0	0	0
T4	752	0	0	0
T10	4692	621	0	0
T11	4658	1768	0	0
T14	4912	2200	0	0
T24	4006	0	0	0
T25	2920	0	0	0
T26	3042	0	0	0
T29	0	543	0	0
T31	0	622	0	0
T42	0	429	0	0
T44	0	261	0	0
T105	0	462	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23345664	23016324	0	0
T1	4438	4302	0	0
T2	7054	6932	0	0
T3	3930	3736	0	0
T4	4008	3722	0	0
T10	4692	4516	0	0
T11	4658	4484	0	0
T14	4912	4734	0	0
T24	4006	3860	0	0
T25	2920	2724	0	0
T26	3042	2930	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23345664	23016324	0	0
T1	4438	4302	0	0
T2	7054	6932	0	0
T3	3930	3736	0	0
T4	4008	3722	0	0
T10	4692	4516	0	0
T11	4658	4484	0	0
T14	4912	4734	0	0
T24	4006	3860	0	0
T25	2920	2724	0	0
T26	3042	2930	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23345664	23016324	0	0
T1	4438	4302	0	0
T2	7054	6932	0	0
T3	3930	3736	0	0
T4	4008	3722	0	0
T10	4692	4516	0	0
T11	4658	4484	0	0
T14	4912	4734	0	0
T24	4006	3860	0	0
T25	2920	2724	0	0
T26	3042	2930	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	22934592	1156609	0	0
T1	4438	470	0	0
T2	7054	5113	0	0
T3	3930	0	0	0
T4	4008	0	0	0
T5	0	323	0	0
T10	4692	621	0	0
T11	4658	1768	0	0
T14	4912	2200	0	0
T24	4006	0	0	0
T25	2920	0	0	0
T26	3042	0	0	0
T29	0	543	0	0
T31	0	622	0	0
T42	0	429	0	0
T44	0	261	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T106,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T107
1	0	1	Covered	T1,T2,T10
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	11286261	526819	0	0
DepthKnown_A	11672832	11508162	0	0
RvalidKnown_A	11672832	11508162	0	0
WreadyKnown_A	11672832	11508162	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	11467296	572029	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11286261	526819	0	0
T1	2219	236	0	0
T2	3527	2469	0	0
T3	1965	0	0	0
T4	376	0	0	0
T10	2346	311	0	0
T11	2329	870	0	0
T14	2456	1063	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T29	0	272	0	0
T31	0	316	0	0
T42	0	140	0	0
T44	0	207	0	0
T105	0	217	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	11467296	572029	0	0
T1	2219	236	0	0
T2	3527	2469	0	0
T3	1965	0	0	0
T4	2004	0	0	0
T5	0	166	0	0
T10	2346	311	0	0
T11	2329	870	0	0
T14	2456	1063	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T29	0	272	0	0
T31	0	316	0	0
T42	0	140	0	0
T44	0	207	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T34,T35
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T36,T37
1	0	1	Covered	T1,T2,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	11286261	538971	0	0
DepthKnown_A	11672832	11508162	0	0
RvalidKnown_A	11672832	11508162	0	0
WreadyKnown_A	11672832	11508162	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	11467296	584580	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11286261	538971	0	0
T1	2219	234	0	0
T2	3527	2644	0	0
T3	1965	0	0	0
T4	376	0	0	0
T10	2346	310	0	0
T11	2329	898	0	0
T14	2456	1137	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T29	0	271	0	0
T31	0	306	0	0
T42	0	289	0	0
T44	0	54	0	0
T105	0	245	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11672832	11508162	0	0
T1	2219	2151	0	0
T2	3527	3466	0	0
T3	1965	1868	0	0
T4	2004	1861	0	0
T10	2346	2258	0	0
T11	2329	2242	0	0
T14	2456	2367	0	0
T24	2003	1930	0	0
T25	1460	1362	0	0
T26	1521	1465	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	11467296	584580	0	0
T1	2219	234	0	0
T2	3527	2644	0	0
T3	1965	0	0	0
T4	2004	0	0	0
T5	0	157	0	0
T10	2346	310	0	0
T11	2329	898	0	0
T14	2456	1137	0	0
T24	2003	0	0	0
T25	1460	0	0	0
T26	1521	0	0	0
T29	0	271	0	0
T31	0	306	0	0
T42	0	289	0	0
T44	0	54	0	0