Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
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Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cs_cmds_cg 100.00 1 100 1 64 64



Group Instance : edn_cs_cmds_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance edn_cs_cmds_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 19 0 19 100.00
Crosses 34 0 34 100.00


Variables for Group Instance edn_cs_cmds_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acmd 5 0 5 100.00 100 1 1 0
cp_clen 2 0 2 100.00 100 1 1 0
cp_cmd_src 5 0 5 100.00 100 1 1 0
cp_flags 2 0 2 100.00 100 1 1 0
cp_glen 2 0 2 100.00 100 1 1 0
cp_mode 3 0 3 100.00 100 1 1 0


Crosses for Group Instance edn_cs_cmds_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_generate_intended 9 0 9 100.00 100 1 1 0
cr_instantiate_intended 9 0 9 100.00 100 1 1 0
cr_reseed_intended 8 0 8 100.00 100 1 1 0
cr_update_intended 2 0 2 100.00 100 1 1 0
cr_uninstantiate_intended 1 0 1 100.00 100 1 1 0
cr_acmd_mode_cmd_src_unintended 5 0 5 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAMECOUNTSTATUS
auto[INV] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] 3461 1 T1 1 T2 1 T3 8
auto[RES] 962 1 T1 1 T2 1 T3 2
auto[GEN] 3691 1 T1 1 T2 1 T3 8
auto[UPD] 414 1 T3 1 T4 6 T84 1
auto[UNI] 2679 1 T1 1 T2 1 T3 8


Summary for Variable cp_clen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_clen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
some_cmd_data 3543 1 T1 2 T2 2 T3 7
no_cmd_data 7670 1 T1 2 T2 2 T3 20


Summary for Variable cp_cmd_src

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_cmd_src

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_cmd_req 9402 1 T1 4 T2 4 T3 27
reseed_cmd 575 1 T9 1 T10 2 T11 1
generate_cmd 535 1 T9 1 T10 2 T11 1
boot_gen_cmd 403 1 T24 2 T25 2 T26 2
boot_ins_cmd 298 1 T24 1 T25 1 T26 1


Summary for Variable cp_flags

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_flags

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
true 3901 1 T1 2 T3 8 T24 3
false 7312 1 T1 2 T2 4 T3 19


Summary for Variable cp_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_glen

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 1415 1 T1 2 T2 2 T24 1
one 2272 1 T3 5 T24 3 T25 3


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sw_mode 8442 1 T1 4 T2 4 T3 27
boot_mode 777 1 T24 3 T25 3 T26 3
auto_mode 1994 1 T24 3 T25 3 T26 3


Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 9 0 9 100.00
Automatically Generated Cross Bins 9 0 9 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_generate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [multiple , one] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_glencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[GEN] some_cmd_data multiple sw_mode sw_cmd_req 177 1 T2 1 T84 1 T43 1
auto[GEN] some_cmd_data multiple auto_mode generate_cmd 130 1 T82 1 T219 1 T94 1
auto[GEN] some_cmd_data one sw_mode sw_cmd_req 57 1 T86 1 T22 1 T274 1
auto[GEN] some_cmd_data one auto_mode generate_cmd 133 1 T10 1 T15 1 T22 1
auto[GEN] no_cmd_data multiple sw_mode sw_cmd_req 43 1 T1 1 T21 1 T48 1
auto[GEN] no_cmd_data multiple boot_mode boot_gen_cmd 78 1 T43 1 T50 1 T274 1
auto[GEN] no_cmd_data multiple auto_mode generate_cmd 44 1 T21 1 T82 1 T94 1
auto[GEN] no_cmd_data one sw_mode sw_cmd_req 1127 1 T3 5 T4 6 T85 1
auto[GEN] no_cmd_data one auto_mode generate_cmd 168 1 T9 1 T10 1 T11 1


User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_gen 0 Excluded
gen_auto_wrong_src 0 Excluded
gen_boot_wrong_src 0 Excluded
gen_boot_seq_wrong_clen 0 Excluded
gen_boot_seq_wrong_glen 0 Excluded
gen_sw_wrong_src 0 Excluded


Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 9 0 9 100.00
Automatically Generated Cross Bins 9 0 9 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] some_cmd_data true sw_mode sw_cmd_req 611 1 T3 2 T4 7 T84 1
auto[INS] some_cmd_data true auto_mode sw_cmd_req 77 1 T82 1 T94 1 T23 1
auto[INS] some_cmd_data false sw_mode sw_cmd_req 615 1 T1 1 T2 1 T3 1
auto[INS] some_cmd_data false auto_mode sw_cmd_req 78 1 T21 1 T22 1 T82 1
auto[INS] no_cmd_data true sw_mode sw_cmd_req 161 1 T4 1 T43 1 T41 4
auto[INS] no_cmd_data true auto_mode sw_cmd_req 227 1 T24 1 T25 1 T26 1
auto[INS] no_cmd_data false sw_mode sw_cmd_req 1251 1 T3 5 T4 7 T85 1
auto[INS] no_cmd_data false boot_mode boot_ins_cmd 156 1 T24 1 T25 1 T26 1
auto[INS] no_cmd_data false auto_mode sw_cmd_req 143 1 T9 1 T10 1 T11 1


User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_ins 0 Excluded
ins_auto_wrong_src 0 Excluded
ins_boot_wrong_src 0 Excluded
ins_boot_seq_wrong_clen 0 Excluded
ins_boot_seq_wrong_flag0 0 Excluded
ins_sw_wrong_src 0 Excluded


Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 8 0 8 100.00
Automatically Generated Cross Bins 8 0 8 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_reseed_intended

Excluded/Illegal bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [true , false] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (120 bins)


Covered bins
cp_acmdcp_clencp_flagscp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[RES] some_cmd_data true sw_mode sw_cmd_req 148 1 T1 1 T86 1 T43 1
auto[RES] some_cmd_data true auto_mode reseed_cmd 130 1 T15 1 T21 1 T22 1
auto[RES] some_cmd_data false sw_mode sw_cmd_req 139 1 T3 1 T4 1 T41 3
auto[RES] some_cmd_data false auto_mode reseed_cmd 142 1 T17 1 T6 1 T7 1
auto[RES] no_cmd_data true sw_mode sw_cmd_req 41 1 T42 2 T199 3 T114 2
auto[RES] no_cmd_data true auto_mode reseed_cmd 35 1 T10 1 T104 1 T7 1
auto[RES] no_cmd_data false sw_mode sw_cmd_req 43 1 T2 1 T3 1 T4 1
auto[RES] no_cmd_data false auto_mode reseed_cmd 208 1 T9 1 T10 1 T11 1


User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_res 0 Excluded
res_auto_wrong_src 0 Excluded
res_boot_wrong_src 0 Excluded
res_sw_wrong_src 0 Excluded


Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_update_intended

Excluded/Illegal bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)
[auto[GENB] , auto[GENU]] [some_cmd_data , no_cmd_data] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (60 bins)


Covered bins
cp_acmdcp_clencp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UPD] some_cmd_data sw_mode sw_cmd_req 309 1 T4 3 T84 1 T41 4
auto[UPD] no_cmd_data sw_mode sw_cmd_req 84 1 T3 1 T4 3 T41 1


User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_upd 0 Excluded
upd_auto_wrong_src 0 Excluded
upd_boot_wrong_src 0 Excluded
upd_sw_wrong_src 0 Excluded


Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 1 0 1 100.00
Automatically Generated Cross Bins 1 0 1 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[UNI] sw_mode sw_cmd_req 2657 1 T1 1 T2 1 T3 8


User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_uni 0 Excluded
uni_auto_wrong_src 0 Excluded
uni_boot_wrong_src 0 Excluded
uni_sw_wrong_src 0 Excluded


Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 5 0 5 100.00
Automatically Generated Cross Bins 5 0 5 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
cp_acmdcp_modecp_cmd_srcCOUNTSTATUS
[auto[INV]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (15 bins)
[auto[GENB] , auto[GENU]] [sw_mode , boot_mode , auto_mode] [sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd] -- Excluded (30 bins)


Covered bins
cp_acmdcp_modecp_cmd_srcCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[INS] auto_mode sw_cmd_req 525 1 T24 1 T25 1 T26 1
auto[RES] auto_mode sw_cmd_req 16 1 T219 1 T12 1 T336 1
auto[GEN] auto_mode sw_cmd_req 414 1 T24 2 T25 2 T26 2
auto[UPD] auto_mode sw_cmd_req 21 1 T15 1 T21 1 T334 1
auto[UNI] auto_mode sw_cmd_req 22 1 T22 1 T337 1 T338 1


User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins
NAMECOUNTSTATUS
not_sw_cmd 0 Excluded
not_auto_mode 0 Excluded

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