Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156524	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

328653

1

T1

23

T2

23

T3

177

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	205754	1			T1	144		T2	44		T3	552
values[0x0]	132086	1			T1	11		T2	14		T3	94
values[0x1]	147337	1			T1	13		T2	8		T3	103

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	104490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

380687

1

T1

74

T2

37

T3

351

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2026	1			T24	3		T4	36		T41	3
valid_sources[0x01]	2005	1			T4	36		T44	2		T62	1
valid_sources[0x02]	1730	1			T4	27		T27	6		T41	77
valid_sources[0x03]	1772	1			T4	26		T10	1		T41	19
valid_sources[0x04]	2065	1			T4	36		T9	1		T5	1
valid_sources[0x05]	1395	1			T4	21		T41	32		T42	50
valid_sources[0x06]	1726	1			T4	30		T84	1		T15	1
valid_sources[0x07]	2379	1			T24	7		T25	1		T4	29
valid_sources[0x08]	1574	1			T4	35		T41	19		T42	18
valid_sources[0x09]	1597	1			T4	20		T15	1		T41	59
valid_sources[0x0a]	1473	1			T25	1		T4	39		T84	1
valid_sources[0x0b]	1426	1			T4	26		T5	1		T15	1
valid_sources[0x0c]	2148	1			T4	24		T28	1		T84	3
valid_sources[0x0d]	1842	1			T4	37		T11	1		T17	1
valid_sources[0x0e]	1943	1			T4	33		T84	1		T60	9
valid_sources[0x0f]	1819	1			T25	1		T4	32		T9	1
valid_sources[0x10]	1351	1			T25	1		T4	36		T84	1
valid_sources[0x11]	1402	1			T4	25		T41	19		T21	1
valid_sources[0x12]	1743	1			T25	1		T4	42		T15	2
valid_sources[0x13]	1722	1			T4	32		T5	1		T11	1
valid_sources[0x14]	1855	1			T4	19		T86	5		T41	32
valid_sources[0x15]	1932	1			T4	31		T86	3		T41	57
valid_sources[0x16]	1599	1			T25	1		T26	10		T4	32
valid_sources[0x17]	2155	1			T4	36		T10	2		T42	69
valid_sources[0x18]	2092	1			T4	24		T41	13		T42	33
valid_sources[0x19]	2050	1			T4	28		T9	3		T11	1
valid_sources[0x1a]	1757	1			T24	4		T4	40		T9	1
valid_sources[0x1b]	1810	1			T24	4		T4	38		T86	3
valid_sources[0x1c]	1727	1			T4	24		T9	2		T41	3
valid_sources[0x1d]	1454	1			T4	25		T80	1		T15	2
valid_sources[0x1e]	1713	1			T4	37		T84	1		T41	16
valid_sources[0x1f]	1915	1			T4	35		T41	12		T42	31
valid_sources[0x20]	1462	1			T4	27		T44	1		T60	3
valid_sources[0x21]	1610	1			T24	1		T4	31		T10	1
valid_sources[0x22]	2100	1			T4	34		T84	1		T5	1
valid_sources[0x23]	1645	1			T4	22		T22	2		T42	31
valid_sources[0x24]	1345	1			T4	37		T41	68		T42	20
valid_sources[0x25]	2420	1			T4	23		T41	24		T22	1
valid_sources[0x26]	1983	1			T4	27		T27	1		T41	29
valid_sources[0x27]	1975	1			T4	30		T84	1		T9	1
valid_sources[0x28]	1894	1			T4	22		T62	1		T80	1
valid_sources[0x29]	1484	1			T4	22		T27	2		T11	1
valid_sources[0x2a]	1844	1			T25	1		T4	28		T27	8
valid_sources[0x2b]	1566	1			T4	40		T41	26		T42	45
valid_sources[0x2c]	1358	1			T4	19		T41	12		T42	49
valid_sources[0x2d]	1891	1			T4	21		T5	1		T41	42
valid_sources[0x2e]	1548	1			T4	31		T11	3		T15	1
valid_sources[0x2f]	1672	1			T4	34		T62	2		T15	2
valid_sources[0x30]	1768	1			T4	20		T27	5		T86	5
valid_sources[0x31]	2664	1			T4	24		T15	1		T41	28
valid_sources[0x32]	1417	1			T4	42		T10	1		T11	1
valid_sources[0x33]	1628	1			T25	1		T4	32		T41	17
valid_sources[0x34]	1944	1			T4	28		T27	2		T41	69
valid_sources[0x35]	1473	1			T4	27		T9	1		T11	1
valid_sources[0x36]	1407	1			T4	44		T84	1		T41	1
valid_sources[0x37]	1763	1			T4	18		T84	2		T62	1
valid_sources[0x38]	1449	1			T4	28		T9	1		T5	1
valid_sources[0x39]	1665	1			T4	35		T80	1		T11	1
valid_sources[0x3a]	2991	1			T4	11		T86	1		T45	43
valid_sources[0x3b]	1851	1			T25	3		T4	33		T11	1
valid_sources[0x3c]	2287	1			T4	37		T21	1		T42	37
valid_sources[0x3d]	2980	1			T25	1		T4	26		T41	36
valid_sources[0x3e]	1414	1			T4	21		T41	2		T21	1
valid_sources[0x3f]	2525	1			T24	2		T4	21		T86	3
valid_sources[0x40]	2134	1			T4	24		T41	46		T21	1
valid_sources[0x41]	2684	1			T4	24		T5	1		T41	16
valid_sources[0x42]	1667	1			T4	32		T42	30		T7	2
valid_sources[0x43]	1795	1			T4	40		T27	1		T11	2
valid_sources[0x44]	2973	1			T4	31		T84	1		T9	3
valid_sources[0x45]	1541	1			T4	25		T9	1		T41	63
valid_sources[0x46]	2900	1			T4	27		T10	1		T41	50
valid_sources[0x47]	2124	1			T4	27		T84	3		T62	1
valid_sources[0x48]	1915	1			T4	31		T41	17		T42	20
valid_sources[0x49]	1760	1			T4	28		T62	1		T41	47
valid_sources[0x4a]	1798	1			T4	42		T5	1		T17	16
valid_sources[0x4b]	1889	1			T4	32		T41	11		T42	38
valid_sources[0x4c]	1583	1			T4	24		T84	1		T61	8
valid_sources[0x4d]	1633	1			T24	1		T4	34		T84	2
valid_sources[0x4e]	2128	1			T4	22		T84	1		T85	69
valid_sources[0x4f]	2139	1			T4	27		T9	1		T41	15
valid_sources[0x50]	2179	1			T4	36		T10	3		T41	2
valid_sources[0x51]	1644	1			T4	24		T84	2		T86	12
valid_sources[0x52]	2312	1			T4	29		T84	1		T11	1
valid_sources[0x53]	2595	1			T4	43		T15	1		T41	40
valid_sources[0x54]	1474	1			T4	23		T17	3		T41	56
valid_sources[0x55]	1803	1			T4	26		T10	57		T11	1
valid_sources[0x56]	2297	1			T25	1		T4	44		T84	1
valid_sources[0x57]	1602	1			T4	26		T9	1		T5	1
valid_sources[0x58]	1686	1			T4	27		T9	1		T86	8
valid_sources[0x59]	1569	1			T4	36		T41	17		T21	1
valid_sources[0x5a]	1942	1			T4	37		T84	1		T86	4
valid_sources[0x5b]	1621	1			T4	31		T44	3		T11	1
valid_sources[0x5c]	2158	1			T4	34		T9	1		T41	20
valid_sources[0x5d]	1723	1			T4	32		T86	1		T5	1
valid_sources[0x5e]	1452	1			T4	30		T41	44		T21	2
valid_sources[0x5f]	2125	1			T4	28		T84	1		T41	29
valid_sources[0x60]	1744	1			T4	37		T84	1		T11	1
valid_sources[0x61]	1704	1			T4	49		T84	1		T46	121
valid_sources[0x62]	1734	1			T4	25		T84	2		T80	2
valid_sources[0x63]	1846	1			T4	39		T10	2		T41	19
valid_sources[0x64]	1341	1			T4	23		T84	1		T44	1
valid_sources[0x65]	1658	1			T4	27		T84	1		T41	55
valid_sources[0x66]	1702	1			T4	37		T43	117		T60	3
valid_sources[0x67]	1945	1			T4	42		T62	1		T10	1
valid_sources[0x68]	1748	1			T4	34		T84	1		T41	29
valid_sources[0x69]	1759	1			T4	25		T9	1		T5	1
valid_sources[0x6a]	2032	1			T4	32		T41	30		T42	9
valid_sources[0x6b]	2101	1			T4	42		T41	28		T21	1
valid_sources[0x6c]	1896	1			T4	29		T84	1		T86	3
valid_sources[0x6d]	1915	1			T4	38		T84	1		T17	5
valid_sources[0x6e]	1861	1			T4	44		T29	2		T62	1
valid_sources[0x6f]	2524	1			T4	32		T84	1		T9	1
valid_sources[0x70]	2502	1			T4	34		T84	1		T10	1
valid_sources[0x71]	1742	1			T4	28		T84	2		T62	1
valid_sources[0x72]	1410	1			T4	21		T84	1		T9	1
valid_sources[0x73]	2156	1			T4	34		T41	136		T22	1
valid_sources[0x74]	1539	1			T4	39		T44	7		T41	111
valid_sources[0x75]	1784	1			T24	1		T4	27		T84	1
valid_sources[0x76]	3091	1			T25	1		T4	30		T11	3
valid_sources[0x77]	1861	1			T25	2		T4	27		T84	1
valid_sources[0x78]	1493	1			T4	21		T10	2		T41	12
valid_sources[0x79]	1962	1			T24	1		T4	26		T10	1
valid_sources[0x7a]	1406	1			T4	21		T9	1		T41	49
valid_sources[0x7b]	2408	1			T4	29		T62	1		T80	1
valid_sources[0x7c]	2055	1			T4	22		T44	7		T42	17
valid_sources[0x7d]	2313	1			T4	37		T41	20		T42	24
valid_sources[0x7e]	2252	1			T4	20		T17	3		T41	8
valid_sources[0x7f]	1923	1			T25	1		T4	38		T86	1
valid_sources[0x80]	2659	1			T4	33		T27	3		T41	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

88923

1

T1

4

T2

5

T3

61

values[0x0]

all_enables

biggest_size

121165

1

T1

11

T2

11

T3

63

values[0x1]

all_enables

biggest_size

118565

1

T1

8

T2

7

T3

53