Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1836	1			T1	1		T2	1		T3	4
non_zero_bins[1]	1241	1			T1	1		T2	1		T3	3
zero	6382	1			T1	2		T2	2		T3	20

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	315	1			T3	1		T4	6		T84	1
uni	2280	1			T1	1		T2	1		T3	8
gen	3208	1			T1	1		T2	1		T3	8
res	628	1			T1	1		T2	1		T3	2
ins	3028	1			T1	1		T2	1		T3	8

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5995

1

T1

2

T2

4

T3

19

mubi_true

3464

1

T1

2

T3

8

T24

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

36

1

T9

1

T11

1

T125

1

pass

9423

1

T1

4

T2

4

T3

27

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	77	1			T4	1		T41	2		T42	6
upd	non_zero_bins[0]	pass	mubi_true	71	1			T4	1		T84	1		T41	1
upd	non_zero_bins[1]	pass	mubi_false	49	1			T4	1		T83	2		T199	1
upd	non_zero_bins[1]	pass	mubi_true	51	1			T83	3		T91	1		T49	1
upd	zero	pass	mubi_false	26	1			T81	1		T83	1		T199	1
upd	zero	pass	mubi_true	41	1			T3	1		T4	3		T41	1
uni	zero	pass	mubi_false	1692	1			T1	1		T2	1		T3	5
uni	zero	pass	mubi_true	588	1			T3	3		T4	6		T46	1
gen	non_zero_bins[0]	pass	mubi_false	361	1			T2	1		T3	1		T4	4
gen	non_zero_bins[0]	pass	mubi_true	369	1			T3	2		T4	1		T86	1
gen	non_zero_bins[1]	pass	mubi_false	236	1			T84	1		T46	1		T41	2
gen	non_zero_bins[1]	pass	mubi_true	243	1			T4	2		T43	1		T41	1
gen	zero	fail	mubi_false	32	1			T9	1		T11	1		T125	1
gen	zero	pass	mubi_false	1248	1			T3	5		T24	2		T26	2
gen	zero	pass	mubi_true	719	1			T1	1		T24	2		T25	3
res	non_zero_bins[0]	pass	mubi_false	138	1			T4	1		T41	2		T81	2
res	non_zero_bins[0]	pass	mubi_true	135	1			T1	1		T42	2		T81	2
res	non_zero_bins[1]	pass	mubi_false	112	1			T3	1		T81	2		T197	1
res	non_zero_bins[1]	pass	mubi_true	97	1			T86	1		T43	1		T15	2
res	zero	fail	mubi_false	4	1			T99	1		T157	1		T285	1
res	zero	pass	mubi_false	78	1			T2	1		T3	1		T4	1
res	zero	pass	mubi_true	64	1			T42	2		T199	1		T114	2
ins	non_zero_bins[0]	pass	mubi_false	348	1			T3	1		T4	3		T86	1
ins	non_zero_bins[0]	pass	mubi_true	337	1			T4	4		T46	1		T41	3
ins	non_zero_bins[1]	pass	mubi_false	223	1			T1	1		T2	1		T4	2
ins	non_zero_bins[1]	pass	mubi_true	230	1			T3	2		T4	3		T84	1
ins	zero	pass	mubi_false	1371	1			T3	5		T24	2		T25	2
ins	zero	pass	mubi_true	519	1			T24	1		T25	1		T26	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded