Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T122,T116
1	1	Covered	T24,T25,T26

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T6,T7
1	1	Covered	T9,T10,T11

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
1	0	Covered	T5,T6,T16

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T5,T6,T16

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T5,T6,T16

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T24,T25,T26

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T9,T11,T15
AutoCaptGenCnt	143	Covered	T9,T11,T15
AutoCaptReseedCnt	141	Covered	T15,T21,T22
AutoDispatch	125	Covered	T9,T10,T11
AutoFirstAckWait	119	Covered	T9,T10,T11
AutoLoadIns	69	Covered	T9,T10,T11
AutoSendGenCmd	150	Covered	T9,T11,T15
AutoSendReseedCmd	162	Covered	T15,T21,T22
BootDone	98	Covered	T24,T25,T26
BootGenAckWait	90	Covered	T24,T25,T26
BootInsAckWait	80	Covered	T24,T25,T26
BootLoadGen	85	Covered	T24,T25,T26
BootLoadIns	65	Covered	T24,T25,T26
BootLoadUni	102	Covered	T24,T25,T26
BootPulse	94	Covered	T24,T25,T26
BootUniAckWait	107	Covered	T24,T25,T26
Error	188	Covered	T5,T6,T16
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T24,T25,T26
SWPortMode	74	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T15,T21,T22
AutoAckWait->Error	188	Covered	T64,T69,T123
AutoAckWait->Idle	211	Covered	T82,T94,T124
AutoAckWait->RejectCsrngEntropy	188	Covered	T9,T11,T125
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T9,T11,T15
AutoCaptGenCnt->Error	188	Covered	T6,T126,T127
AutoCaptGenCnt->Idle	211	Covered	T82,T128,T129
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T130,T131,T132
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T15,T21,T22
AutoCaptReseedCnt->Error	188	Covered	T133
AutoCaptReseedCnt->Idle	211	Covered	T134,T75,T135
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T136,T137,T138
AutoDispatch->AutoCaptGenCnt	143	Covered	T9,T11,T15
AutoDispatch->AutoCaptReseedCnt	141	Covered	T15,T21,T22
AutoDispatch->Error	188	Covered	T8,T139
AutoDispatch->Idle	138	Covered	T15,T21,T22
AutoDispatch->RejectCsrngEntropy	188	Covered	T10,T140,T141
AutoFirstAckWait->AutoDispatch	125	Covered	T9,T10,T11
AutoFirstAckWait->Error	188	Covered	T66,T142
AutoFirstAckWait->Idle	211	Covered	T124,T106,T73
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T105,T143,T144
AutoLoadIns->AutoFirstAckWait	119	Covered	T9,T10,T11
AutoLoadIns->Error	188	Covered	T65,T145,T146
AutoLoadIns->Idle	211	Covered	T10,T104,T105
AutoLoadIns->RejectCsrngEntropy	188	Covered	T104,T147,T148
AutoSendGenCmd->AutoAckWait	156	Covered	T9,T11,T15
AutoSendGenCmd->Error	188	Covered	T149
AutoSendGenCmd->Idle	211	Covered	T150,T151,T152
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T116,T98,T153
AutoSendReseedCmd->AutoAckWait	168	Covered	T15,T21,T22
AutoSendReseedCmd->Error	188	Not Covered
AutoSendReseedCmd->Idle	211	Covered	T154,T155,T156
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T99,T118,T157
BootDone->BootLoadUni	102	Covered	T24,T25,T26
BootDone->Error	188	Covered	T16,T88,T63
BootDone->Idle	211	Covered	T29,T158,T159
BootDone->RejectCsrngEntropy	188	Covered	T24,T60,T160
BootGenAckWait->BootPulse	94	Covered	T24,T25,T26
BootGenAckWait->Error	188	Covered	T161,T162,T163
BootGenAckWait->Idle	211	Covered	T122,T67,T164
BootGenAckWait->RejectCsrngEntropy	188	Covered	T27,T165,T166
BootInsAckWait->BootLoadGen	85	Covered	T24,T25,T26
BootInsAckWait->Error	188	Covered	T167,T168,T169
BootInsAckWait->Idle	211	Covered	T16,T87,T88
BootInsAckWait->RejectCsrngEntropy	188	Covered	T25,T17,T120
BootLoadGen->BootGenAckWait	90	Covered	T24,T25,T26
BootLoadGen->Error	188	Covered	T170
BootLoadGen->Idle	211	Covered	T59,T171,T172
BootLoadGen->RejectCsrngEntropy	188	Covered	T173,T174,T175
BootLoadIns->BootInsAckWait	80	Covered	T24,T25,T26
BootLoadIns->Error	188	Covered	T67,T176,T177
BootLoadIns->Idle	211	Covered	T178
BootLoadIns->RejectCsrngEntropy	188	Covered	T53,T179,T180
BootLoadUni->BootUniAckWait	107	Covered	T24,T25,T26
BootLoadUni->Error	188	Covered	T181
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T92,T182,T183
BootPulse->BootDone	98	Covered	T24,T25,T26
BootPulse->Error	188	Covered	T87,T184
BootPulse->Idle	211	Covered	T170,T185,T186
BootPulse->RejectCsrngEntropy	188	Covered	T117,T187,T188
BootUniAckWait->Error	188	Covered	T189,T190,T191
BootUniAckWait->Idle	112	Covered	T24,T25,T26
BootUniAckWait->RejectCsrngEntropy	188	Covered	T26,T44,T45
Idle->AutoLoadIns	69	Covered	T9,T10,T11
Idle->BootLoadIns	65	Covered	T24,T25,T26
Idle->Error	188	Covered	T18,T19,T20
Idle->RejectCsrngEntropy	188	Covered	T27,T17,T105
Idle->SWPortMode	74	Covered	T1,T2,T3
RejectCsrngEntropy->Error	188	Covered	T192,T193,T194
RejectCsrngEntropy->Idle	211	Covered	T24,T25,T26
SWPortMode->Error	188	Covered	T5,T195,T68
SWPortMode->Idle	211	Covered	T3,T4,T27
SWPortMode->RejectCsrngEntropy	188	Covered	T24,T25,T26

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T24,T26,T44
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T24,T25,T26
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T10,T11
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T9,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T9,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T9,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T11,T15
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T9,T11,T15
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T15,T21,T22
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T15,T21,T22
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T9,T10,T11
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T11,T15
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T9,T11,T15
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T21,T22
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T21,T22
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T15,T21,T22
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T26
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T16
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T54,T112

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T5,T6,T16
1	0	1	-	Not Covered
1	0	0	-	Covered	T24,T25,T26
0	-	-	1	Covered	T24,T25,T26
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	12230911	133492	0	0
FpvSecCmErrorStEscalate_A	12230911	134403	0	0
u_state_regs_A	12198782	12035856	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	133492	0	0
T5	2083	1083	0	0
T6	0	1137	0	0
T7	0	1058	0	0
T8	0	352	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T16	0	476	0	0
T17	2362	0	0	0
T21	2782	0	0	0
T22	1701	0	0	0
T41	264116	0	0	0
T42	245810	0	0	0
T50	2550	0	0	0
T54	0	1038	0	0
T63	0	342	0	0
T64	0	492	0	0
T87	0	600	0	0
T88	0	260	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	134403	0	0
T5	2083	1084	0	0
T6	0	1138	0	0
T7	0	1059	0	0
T8	0	353	0	0
T10	1598	0	0	0
T11	2405	0	0	0
T15	1617	0	0	0
T16	0	477	0	0
T17	2362	0	0	0
T21	2782	0	0	0
T22	1701	0	0	0
T41	264116	0	0	0
T42	245810	0	0	0
T50	2550	0	0	0
T54	0	1039	0	0
T63	0	343	0	0
T64	0	493	0	0
T87	0	601	0	0
T88	0	261	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12198782	12035856	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0