Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T39,T103
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T34,T40
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T15

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	23838782	1495136	0	0
DepthKnown_A	24461822	24135970	0	0
RvalidKnown_A	24461822	24135970	0	0
WreadyKnown_A	24461822	24135970	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	24184442	1569043	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23838782	1495136	0	0
T5	822	0	0	0
T6	0	330	0	0
T9	5842	760	0	0
T10	0	381	0	0
T11	0	623	0	0
T15	0	979	0	0
T17	0	179	0	0
T21	0	1891	0	0
T22	0	659	0	0
T43	3498	0	0	0
T45	3646	0	0	0
T46	6958	0	0	0
T60	3810	0	0	0
T61	1444	0	0	0
T62	1918	0	0	0
T80	1760	0	0	0
T86	8006	0	0	0
T104	0	725	0	0
T105	0	1107	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24461822	24135970	0	0
T1	4278	4114	0	0
T2	7110	7004	0	0
T3	23982	22326	0	0
T4	315596	315426	0	0
T24	3924	3740	0	0
T25	3340	3142	0	0
T26	4608	4422	0	0
T27	4036	3924	0	0
T28	1490	1318	0	0
T29	2526	2350	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24461822	24135970	0	0
T1	4278	4114	0	0
T2	7110	7004	0	0
T3	23982	22326	0	0
T4	315596	315426	0	0
T24	3924	3740	0	0
T25	3340	3142	0	0
T26	4608	4422	0	0
T27	4036	3924	0	0
T28	1490	1318	0	0
T29	2526	2350	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24461822	24135970	0	0
T1	4278	4114	0	0
T2	7110	7004	0	0
T3	23982	22326	0	0
T4	315596	315426	0	0
T24	3924	3740	0	0
T25	3340	3142	0	0
T26	4608	4422	0	0
T27	4036	3924	0	0
T28	1490	1318	0	0
T29	2526	2350	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	24184442	1569043	0	0
T5	4166	0	0	0
T6	0	2182	0	0
T9	5842	760	0	0
T10	0	381	0	0
T11	0	623	0	0
T15	0	979	0	0
T17	0	179	0	0
T21	0	1891	0	0
T22	0	659	0	0
T43	3498	0	0	0
T45	3646	0	0	0
T46	6958	0	0	0
T60	3810	0	0	0
T61	1444	0	0	0
T62	1918	0	0	0
T80	1760	0	0	0
T86	8006	0	0	0
T104	0	725	0	0
T105	0	1107	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T106,T107,T108
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T38,T39
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T109,T110
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T15,T21,T22

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	11919391	741966	0	0
DepthKnown_A	12230911	12067985	0	0
RvalidKnown_A	12230911	12067985	0	0
WreadyKnown_A	12230911	12067985	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	12092221	778629	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11919391	741966	0	0
T5	411	0	0	0
T6	0	136	0	0
T9	2921	383	0	0
T10	0	179	0	0
T11	0	314	0	0
T15	0	486	0	0
T17	0	76	0	0
T21	0	923	0	0
T22	0	327	0	0
T43	1749	0	0	0
T45	1823	0	0	0
T46	3479	0	0	0
T60	1905	0	0	0
T61	722	0	0	0
T62	959	0	0	0
T80	880	0	0	0
T86	4003	0	0	0
T104	0	319	0	0
T105	0	536	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	12092221	778629	0	0
T5	2083	0	0	0
T6	0	1030	0	0
T9	2921	383	0	0
T10	0	179	0	0
T11	0	314	0	0
T15	0	486	0	0
T17	0	76	0	0
T21	0	923	0	0
T22	0	327	0	0
T43	1749	0	0	0
T45	1823	0	0	0
T46	3479	0	0	0
T60	1905	0	0	0
T61	722	0	0	0
T62	959	0	0	0
T80	880	0	0	0
T86	4003	0	0	0
T104	0	319	0	0
T105	0	536	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T10,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T103
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T40,T111
1	0	1	Covered	T9,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	11919391	753170	0	0
DepthKnown_A	12230911	12067985	0	0
RvalidKnown_A	12230911	12067985	0	0
WreadyKnown_A	12230911	12067985	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	12092221	790414	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11919391	753170	0	0
T5	411	0	0	0
T6	0	194	0	0
T9	2921	377	0	0
T10	0	202	0	0
T11	0	309	0	0
T15	0	493	0	0
T17	0	103	0	0
T21	0	968	0	0
T22	0	332	0	0
T43	1749	0	0	0
T45	1823	0	0	0
T46	3479	0	0	0
T60	1905	0	0	0
T61	722	0	0	0
T62	959	0	0	0
T80	880	0	0	0
T86	4003	0	0	0
T104	0	406	0	0
T105	0	571	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12230911	12067985	0	0
T1	2139	2057	0	0
T2	3555	3502	0	0
T3	11991	11163	0	0
T4	157798	157713	0	0
T24	1962	1870	0	0
T25	1670	1571	0	0
T26	2304	2211	0	0
T27	2018	1962	0	0
T28	745	659	0	0
T29	1263	1175	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	12092221	790414	0	0
T5	2083	0	0	0
T6	0	1152	0	0
T9	2921	377	0	0
T10	0	202	0	0
T11	0	309	0	0
T15	0	493	0	0
T17	0	103	0	0
T21	0	968	0	0
T22	0	332	0	0
T43	1749	0	0	0
T45	1823	0	0	0
T46	3479	0	0	0
T60	1905	0	0	0
T61	722	0	0	0
T62	959	0	0	0
T80	880	0	0	0
T86	4003	0	0	0
T104	0	406	0	0
T105	0	571	0	0