Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154685	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

315314

1

T1

37

T2

235

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	202032	1			T1	295		T2	720		T3	1
values[0x0]	126885	1			T1	16		T2	115		T3	2
values[0x1]	141082	1			T1	19		T2	118		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	103912	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

366087

1

T1

138

T2

448

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1592	1			T1	3		T26	2		T27	2
valid_sources[0x01]	1463	1			T27	1		T5	3		T44	6
valid_sources[0x02]	1816	1			T1	1		T4	1		T5	8
valid_sources[0x03]	1625	1			T1	1		T27	1		T5	2
valid_sources[0x04]	1555	1			T1	1		T5	4		T9	1
valid_sources[0x05]	1788	1			T1	2		T29	2		T4	1
valid_sources[0x06]	2261	1			T29	1		T5	2		T30	7
valid_sources[0x07]	1542	1			T27	1		T5	6		T30	4
valid_sources[0x08]	1903	1			T1	2		T29	1		T30	1
valid_sources[0x09]	1579	1			T1	1		T5	5		T14	2
valid_sources[0x0a]	2664	1			T5	1		T30	6		T44	10
valid_sources[0x0b]	1666	1			T1	1		T27	1		T5	3
valid_sources[0x0c]	1772	1			T1	1		T5	5		T9	1
valid_sources[0x0d]	2249	1			T1	1		T27	1		T5	2
valid_sources[0x0e]	1669	1			T26	1		T27	3		T29	2
valid_sources[0x0f]	1866	1			T1	1		T5	1		T30	3
valid_sources[0x10]	2028	1			T1	2		T29	1		T4	1
valid_sources[0x11]	1667	1			T1	1		T26	1		T29	1
valid_sources[0x12]	1912	1			T26	1		T29	3		T5	4
valid_sources[0x13]	1869	1			T27	1		T5	5		T30	3
valid_sources[0x14]	1612	1			T1	1		T26	1		T5	4
valid_sources[0x15]	1652	1			T27	1		T5	6		T30	2
valid_sources[0x16]	1889	1			T1	1		T27	1		T4	1
valid_sources[0x17]	2365	1			T1	2		T27	3		T4	1
valid_sources[0x18]	3020	1			T1	1		T27	1		T29	1
valid_sources[0x19]	1702	1			T26	2		T29	1		T5	6
valid_sources[0x1a]	1972	1			T1	1		T5	2		T30	1
valid_sources[0x1b]	2234	1			T1	1		T27	1		T5	3
valid_sources[0x1c]	1608	1			T1	4		T5	3		T30	3
valid_sources[0x1d]	1574	1			T1	2		T28	3		T5	2
valid_sources[0x1e]	1923	1			T29	1		T5	6		T100	1
valid_sources[0x1f]	2048	1			T1	2		T27	1		T5	2
valid_sources[0x20]	1669	1			T4	1		T5	1		T30	1
valid_sources[0x21]	1445	1			T1	1		T5	4		T30	3
valid_sources[0x22]	1995	1			T1	4		T5	4		T30	2
valid_sources[0x23]	1991	1			T1	3		T26	1		T5	5
valid_sources[0x24]	1638	1			T1	1		T27	1		T5	3
valid_sources[0x25]	2059	1			T1	2		T28	2		T5	2
valid_sources[0x26]	1677	1			T1	1		T5	3		T30	2
valid_sources[0x27]	1476	1			T27	3		T29	1		T5	2
valid_sources[0x28]	2085	1			T1	2		T28	1		T5	5
valid_sources[0x29]	2589	1			T1	1		T4	1		T5	5
valid_sources[0x2a]	1751	1			T5	7		T30	1		T11	2
valid_sources[0x2b]	1580	1			T1	2		T5	3		T30	6
valid_sources[0x2c]	2031	1			T1	2		T5	1		T30	5
valid_sources[0x2d]	1772	1			T1	1		T5	6		T30	1
valid_sources[0x2e]	1616	1			T1	1		T5	4		T30	3
valid_sources[0x2f]	1831	1			T5	4		T39	1		T52	1
valid_sources[0x30]	1578	1			T1	1		T29	1		T5	3
valid_sources[0x31]	2169	1			T1	3		T28	5		T5	7
valid_sources[0x32]	2111	1			T1	2		T5	1		T30	3
valid_sources[0x33]	1560	1			T28	1		T5	1		T6	4
valid_sources[0x34]	1566	1			T1	3		T5	4		T14	6
valid_sources[0x35]	1507	1			T26	1		T4	1		T5	4
valid_sources[0x36]	1485	1			T1	3		T4	1		T5	1
valid_sources[0x37]	1942	1			T1	5		T27	1		T28	2
valid_sources[0x38]	1667	1			T1	2		T28	3		T4	3
valid_sources[0x39]	1861	1			T1	3		T27	1		T29	1
valid_sources[0x3a]	1702	1			T28	1		T29	1		T5	3
valid_sources[0x3b]	1730	1			T1	3		T29	1		T5	4
valid_sources[0x3c]	2153	1			T26	1		T5	4		T30	1
valid_sources[0x3d]	1717	1			T1	2		T29	1		T5	4
valid_sources[0x3e]	1935	1			T1	1		T29	1		T4	1
valid_sources[0x3f]	1433	1			T1	1		T26	1		T27	1
valid_sources[0x40]	1661	1			T1	2		T28	2		T29	1
valid_sources[0x41]	1614	1			T1	1		T5	4		T30	2
valid_sources[0x42]	1908	1			T1	2		T5	3		T30	2
valid_sources[0x43]	2735	1			T1	2		T29	1		T4	3
valid_sources[0x44]	1599	1			T4	1		T5	4		T11	1
valid_sources[0x45]	1782	1			T1	2		T4	1		T5	4
valid_sources[0x46]	1843	1			T1	1		T27	1		T5	4
valid_sources[0x47]	1665	1			T1	1		T5	4		T9	1
valid_sources[0x48]	1506	1			T5	4		T30	1		T52	1
valid_sources[0x49]	2160	1			T5	5		T30	2		T11	11
valid_sources[0x4a]	1610	1			T4	1		T5	6		T39	1
valid_sources[0x4b]	1385	1			T1	2		T5	3		T30	5
valid_sources[0x4c]	1694	1			T1	2		T29	2		T5	1
valid_sources[0x4d]	1662	1			T28	1		T5	3		T30	1
valid_sources[0x4e]	1501	1			T1	1		T27	1		T5	2
valid_sources[0x4f]	1518	1			T1	1		T28	1		T5	4
valid_sources[0x50]	1960	1			T1	3		T4	1		T5	4
valid_sources[0x51]	2593	1			T29	1		T5	2		T30	3
valid_sources[0x52]	2015	1			T28	1		T9	3		T11	2
valid_sources[0x53]	2143	1			T1	1		T29	1		T5	3
valid_sources[0x54]	1508	1			T1	1		T27	1		T5	3
valid_sources[0x55]	1749	1			T1	1		T5	1		T30	3
valid_sources[0x56]	1826	1			T1	4		T26	1		T29	2
valid_sources[0x57]	1633	1			T27	2		T29	1		T4	2
valid_sources[0x58]	1769	1			T1	1		T29	1		T30	7
valid_sources[0x59]	1776	1			T1	3		T5	2		T34	3
valid_sources[0x5a]	2268	1			T1	1		T29	1		T5	6
valid_sources[0x5b]	1972	1			T5	5		T44	136		T89	1
valid_sources[0x5c]	1975	1			T4	1		T5	3		T11	1
valid_sources[0x5d]	2216	1			T1	1		T26	2		T5	3
valid_sources[0x5e]	2052	1			T1	1		T5	4		T100	1
valid_sources[0x5f]	2199	1			T29	2		T5	7		T30	4
valid_sources[0x60]	1941	1			T1	1		T27	6		T4	1
valid_sources[0x61]	2206	1			T1	1		T27	2		T29	1
valid_sources[0x62]	1618	1			T1	4		T5	3		T30	1
valid_sources[0x63]	1530	1			T1	1		T26	1		T5	1
valid_sources[0x64]	1820	1			T1	1		T5	4		T30	1
valid_sources[0x65]	2121	1			T28	3		T5	1		T30	14
valid_sources[0x66]	1896	1			T1	1		T27	1		T4	1
valid_sources[0x67]	1643	1			T27	2		T5	4		T118	14
valid_sources[0x68]	2536	1			T5	7		T44	345		T11	3
valid_sources[0x69]	1932	1			T5	1		T39	1		T34	39
valid_sources[0x6a]	1565	1			T5	3		T30	1		T23	6
valid_sources[0x6b]	1647	1			T1	1		T27	1		T28	4
valid_sources[0x6c]	1702	1			T1	4		T5	1		T30	4
valid_sources[0x6d]	2313	1			T29	1		T5	6		T30	1
valid_sources[0x6e]	1765	1			T5	5		T30	10		T84	2
valid_sources[0x6f]	1715	1			T1	4		T4	1		T5	2
valid_sources[0x70]	1750	1			T1	2		T5	2		T30	2
valid_sources[0x71]	1982	1			T1	4		T27	2		T5	4
valid_sources[0x72]	2102	1			T1	1		T27	1		T4	1
valid_sources[0x73]	2041	1			T27	1		T4	1		T5	10
valid_sources[0x74]	1581	1			T27	1		T5	3		T30	1
valid_sources[0x75]	1914	1			T29	3		T5	1		T30	10
valid_sources[0x76]	1912	1			T1	1		T4	1		T5	1
valid_sources[0x77]	2224	1			T1	2		T27	1		T29	1
valid_sources[0x78]	1866	1			T1	1		T5	2		T30	5
valid_sources[0x79]	1871	1			T1	3		T26	1		T5	2
valid_sources[0x7a]	1773	1			T1	3		T26	3		T4	1
valid_sources[0x7b]	2966	1			T1	3		T5	3		T30	10
valid_sources[0x7c]	1712	1			T1	3		T5	1		T14	2
valid_sources[0x7d]	1925	1			T1	2		T29	1		T4	1
valid_sources[0x7e]	1538	1			T1	1		T5	7		T44	7
valid_sources[0x7f]	1669	1			T3	5		T4	2		T5	2
valid_sources[0x80]	2564	1			T2	953		T26	1		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

85189

1

T1

4

T2

71

T3

1

values[0x0]

all_enables

biggest_size

116197

1

T1

16

T2

87

T3

2

values[0x1]

all_enables

biggest_size

113928

1

T1

17

T2

77

T3

2