Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
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Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
92.86 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[edn_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[edn_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[edn_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 1 13 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[edn_reg_block]
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_is_mem 2 1 1 50.00 100 0 0 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_is_mem

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
[auto[1]] 0 0 - - - - - -
auto[0] 944226 0 T1 330 T2 953 T3 5



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 943994 1 T1 330 T2 953 T3 5
values[1] 32 1 T296 3 T297 2 T252 2
values[2] 2 1 T303 1 T304 1 - -
values[3] 122 1 T296 8 T297 6 T252 4



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0] 944006 1 T1 330 T2 953 T3 5
values[1] 28 1 T296 4 T297 1 T305 2
values[2] 11 1 T297 1 T306 1 T303 1
values[3] 104 1 T296 7 T297 5 T252 2



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[TlIntgErrNone] 943896 1 T1 330 T2 953 T3 5
auto[TlIntgErrCmd] 110 1 T296 6 T297 8 T252 6
auto[TlIntgErrData] 98 1 T296 3 T297 7 T252 1
auto[TlIntgErrBoth] 122 1 T296 11 T297 5 T252 3