Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1812	1			T1	2		T2	9		T27	2
non_zero_bins[1]	1221	1			T1	1		T2	5		T28	1
zero	6197	1			T1	4		T2	21		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	307	1			T2	3		T28	1		T5	2
uni	2218	1			T1	2		T2	10		T26	1
gen	3088	1			T1	2		T2	10		T3	1
res	641	1			T1	1		T2	2		T29	1
ins	2976	1			T1	2		T2	10		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5896

1

T1

5

T2

24

T3

1

mubi_true

3334

1

T1

2

T2

11

T3

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

37

1

T9

1

T14

1

T88

1

pass

9193

1

T1

7

T2

35

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	63	1			T28	1		T44	1		T90	1
upd	non_zero_bins[0]	pass	mubi_true	87	1			T2	1		T44	5		T100	2
upd	non_zero_bins[1]	pass	mubi_false	46	1			T5	1		T44	1		T51	1
upd	non_zero_bins[1]	pass	mubi_true	46	1			T2	2		T118	1		T298	1
upd	zero	pass	mubi_false	32	1			T50	1		T119	1		T45	1
upd	zero	pass	mubi_true	33	1			T5	1		T79	1		T115	1
uni	zero	pass	mubi_false	1705	1			T1	2		T2	8		T27	2
uni	zero	pass	mubi_true	513	1			T2	2		T26	1		T27	1
gen	non_zero_bins[0]	pass	mubi_false	372	1			T2	2		T27	1		T28	1
gen	non_zero_bins[0]	pass	mubi_true	326	1			T2	1		T29	1		T5	4
gen	non_zero_bins[1]	pass	mubi_false	230	1			T2	1		T44	5		T299	1
gen	non_zero_bins[1]	pass	mubi_true	230	1			T1	1		T2	1		T5	1
gen	zero	fail	mubi_false	32	1			T9	1		T14	1		T88	1
gen	zero	pass	mubi_false	1214	1			T1	1		T2	5		T26	1
gen	zero	pass	mubi_true	684	1			T3	1		T30	1		T9	2
res	non_zero_bins[0]	pass	mubi_false	159	1			T1	1		T44	1		T11	2
res	non_zero_bins[0]	pass	mubi_true	158	1			T2	2		T29	1		T48	1
res	non_zero_bins[1]	pass	mubi_false	100	1			T30	1		T44	3		T20	2
res	non_zero_bins[1]	pass	mubi_true	97	1			T5	1		T30	1		T44	1
res	zero	fail	mubi_false	5	1			T23	1		T167	1		T300	1
res	zero	pass	mubi_false	63	1			T5	1		T116	1		T121	1
res	zero	pass	mubi_true	59	1			T24	2		T25	2		T74	2
ins	non_zero_bins[0]	pass	mubi_false	330	1			T2	2		T5	3		T30	1
ins	non_zero_bins[0]	pass	mubi_true	317	1			T1	1		T2	1		T27	1
ins	non_zero_bins[1]	pass	mubi_false	234	1			T5	1		T44	5		T47	1
ins	non_zero_bins[1]	pass	mubi_true	238	1			T2	1		T28	1		T29	1
ins	zero	pass	mubi_false	1311	1			T1	1		T2	6		T3	1
ins	zero	pass	mubi_true	546	1			T30	1		T9	1		T10	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded