Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable 100.00 1 100 1 64 64




Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 21 1 T143 2 T311 1 T161 2
others[1] 25 1 T34 2 T59 2 T206 2
others[2] 29 1 T91 2 T49 2 T68 2
others[3] 28 1 T88 2 T23 2 T31 1
false 3520 1 T1 2 T2 2 T3 2
true 810 1 T9 3 T6 5 T10 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 23 1 T31 1 T293 2 T149 2
others[1] 14 1 T33 1 T291 2 T312 2
others[2] 20 1 T32 1 T313 1 T314 2
others[3] 30 1 T10 2 T121 2 T92 2
false 3692 1 T1 1 T2 2 T26 1
true 654 1 T1 1 T3 2 T27 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 17 1 T117 1 T31 1 T315 1
others[1] 14 1 T14 1 T192 1 T75 1
others[2] 15 1 T125 1 T316 1 T313 1
others[3] 20 1 T52 1 T89 1 T58 1
false 3523 1 T1 2 T2 2 T3 2
true 844 1 T4 1 T39 1 T9 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 14 1 T9 2 T137 2 T148 2
others[1] 40 1 T31 1 T32 1 T106 2
others[2] 29 1 T120 2 T77 2 T147 2
others[3] 38 1 T101 2 T155 2 T311 1
false 1987 1 T4 1 T39 1 T9 7
true 2325 1 T1 2 T2 2 T3 2

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