Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.14	100.00	94.44		98.65	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.14	100.00	94.44		98.65	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.16	100.00	94.44		98.65	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T26
1	0	Covered	T3,T87,T55
1	1	Covered	T1,T3,T27

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T26
1	0	Covered	T9,T6,T101
1	1	Covered	T9,T6,T10

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T34
1	0	Covered	T4,T39,T6

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T9,T10,T34
1	Covered	T4,T39,T6

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T9,T10,T34
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T4,T39,T9
1	Covered	T4,T39,T6

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T6

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	73	98.65
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T9,T14,T11
AutoCaptGenCnt	143	Covered	T9,T10,T14
AutoCaptReseedCnt	141	Covered	T11,T20,T23
AutoDispatch	125	Covered	T9,T10,T14
AutoFirstAckWait	119	Covered	T9,T10,T34
AutoLoadIns	69	Covered	T9,T6,T10
AutoSendGenCmd	150	Covered	T9,T14,T11
AutoSendReseedCmd	162	Covered	T11,T20,T23
BootDone	98	Covered	T1,T3,T27
BootGenAckWait	90	Covered	T1,T3,T27
BootInsAckWait	80	Covered	T1,T3,T27
BootLoadGen	85	Covered	T1,T3,T27
BootLoadIns	65	Covered	T1,T3,T27
BootLoadUni	102	Covered	T1,T27,T34
BootPulse	94	Covered	T1,T3,T27
BootUniAckWait	107	Covered	T1,T27,T34
Error	188	Covered	T4,T39,T6
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T9,T10,T34
SWPortMode	74	Covered	T1,T2,T26

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T11,T20,T23
AutoAckWait->Error	188	Covered	T129,T130,T131
AutoAckWait->Idle	211	Covered	T20,T21,T83
AutoAckWait->RejectCsrngEntropy	188	Covered	T9,T14,T88
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T9,T14,T11
AutoCaptGenCnt->Error	188	Covered	T132,T133,T134
AutoCaptGenCnt->Idle	211	Covered	T135,T136
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T10,T106,T137
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T11,T20,T23
AutoCaptReseedCnt->Error	188	Covered	T138,T139,T140
AutoCaptReseedCnt->Idle	211	Covered	T21,T141
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T142,T143,T144
AutoDispatch->AutoCaptGenCnt	143	Covered	T9,T10,T14
AutoDispatch->AutoCaptReseedCnt	141	Covered	T11,T20,T23
AutoDispatch->Error	188	Covered	T16,T145,T146
AutoDispatch->Idle	138	Covered	T11,T24,T25
AutoDispatch->RejectCsrngEntropy	188	Covered	T147,T148,T149
AutoFirstAckWait->AutoDispatch	125	Covered	T9,T10,T14
AutoFirstAckWait->Error	188	Covered	T150,T151
AutoFirstAckWait->Idle	211	Covered	T152,T153,T154
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T34,T155,T124
AutoLoadIns->AutoFirstAckWait	119	Covered	T9,T10,T34
AutoLoadIns->Error	188	Covered	T7,T60,T156
AutoLoadIns->Idle	211	Covered	T6,T10,T89
AutoLoadIns->RejectCsrngEntropy	188	Covered	T59,T52,T157
AutoSendGenCmd->AutoAckWait	156	Covered	T9,T14,T11
AutoSendGenCmd->Error	188	Covered	T8,T158,T123
AutoSendGenCmd->Idle	211	Covered	T159,T160
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T161,T162
AutoSendReseedCmd->AutoAckWait	168	Covered	T11,T20,T21
AutoSendReseedCmd->Error	188	Covered	T163,T164,T165
AutoSendReseedCmd->Idle	211	Covered	T83,T103,T166
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T23,T167,T122
BootDone->BootLoadUni	102	Covered	T1,T27,T34
BootDone->Error	188	Covered	T63,T168,T169
BootDone->Idle	211	Covered	T55,T93,T170
BootDone->RejectCsrngEntropy	188	Covered	T75,T171,T172
BootGenAckWait->BootPulse	94	Covered	T1,T3,T27
BootGenAckWait->Error	188	Covered	T173,T174
BootGenAckWait->Idle	211	Covered	T175,T176,T177
BootGenAckWait->RejectCsrngEntropy	188	Covered	T125,T99,T178
BootInsAckWait->BootLoadGen	85	Covered	T1,T3,T27
BootInsAckWait->Error	188	Covered	T61,T179,T176
BootInsAckWait->Idle	211	Covered	T61,T180,T181
BootInsAckWait->RejectCsrngEntropy	188	Covered	T89,T101,T117
BootLoadGen->BootGenAckWait	90	Covered	T1,T3,T27
BootLoadGen->Error	188	Covered	T86,T182,T183
BootLoadGen->Idle	211	Covered	T87,T86,T71
BootLoadGen->RejectCsrngEntropy	188	Covered	T91,T49,T184
BootLoadIns->BootInsAckWait	80	Covered	T1,T3,T27
BootLoadIns->Error	188	Covered	T71,T177,T185
BootLoadIns->Idle	211	Covered	T3,T186
BootLoadIns->RejectCsrngEntropy	188	Covered	T92,T187,T188
BootLoadUni->BootUniAckWait	107	Covered	T1,T27,T34
BootLoadUni->Error	188	Covered	T189,T190,T191
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T192,T193,T194
BootPulse->BootDone	98	Covered	T1,T3,T27
BootPulse->Error	188	Covered	T64,T195,T196
BootPulse->Idle	211	Covered	T197,T198,T199
BootPulse->RejectCsrngEntropy	188	Covered	T200,T201,T202
BootUniAckWait->Error	188	Covered	T203,T204,T205
BootUniAckWait->Idle	112	Covered	T1,T27,T34
BootUniAckWait->RejectCsrngEntropy	188	Covered	T120,T68,T206
Idle->AutoLoadIns	69	Covered	T9,T6,T10
Idle->BootLoadIns	65	Covered	T1,T3,T27
Idle->Error	188	Covered	T17,T18,T19
Idle->RejectCsrngEntropy	188	Covered	T59,T52,T101
Idle->SWPortMode	74	Covered	T1,T2,T26
RejectCsrngEntropy->Error	188	Covered	T207
RejectCsrngEntropy->Idle	211	Covered	T9,T10,T34
SWPortMode->Error	188	Covered	T15,T56,T113
SWPortMode->Idle	211	Covered	T2,T5,T30
SWPortMode->RejectCsrngEntropy	188	Covered	T9,T10,T34

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T27
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T6,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T26
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T27
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T27
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T27
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T27
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T27
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T27
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T27
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T27,T34
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T3,T34,T14
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T27,T34
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T27,T88
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T27,T34
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T9,T10,T34
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T9,T6,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T9,T10,T34
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T9,T10,T34
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T9,T14,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T9,T14,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T11,T24,T25
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T11,T20,T23
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T9,T10,T14
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T9,T14,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T9,T14,T11
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T20,T23
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T11,T20,T21
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T11,T20,T23
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T26
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T34
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T39,T6
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T39,T6

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T4,T39,T6
1	0	1	-	Not Covered
1	0	0	-	Covered	T9,T10,T34
0	-	-	1	Covered	T3,T9,T6
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	12074411	132499	0	0
FpvSecCmErrorStEscalate_A	12074411	133532	0	0
u_state_regs_A	12038049	11862250	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	132499	0	0
T4	2014	1018	0	0
T5	34029	0	0	0
T6	1075	293	0	0
T7	0	620	0	0
T8	0	384	0	0
T9	2789	0	0	0
T10	2086	0	0	0
T14	1625	0	0	0
T15	0	208	0	0
T16	0	612	0	0
T30	32026	0	0	0
T34	1913	0	0	0
T39	1193	445	0	0
T44	204185	0	0	0
T60	0	443	0	0
T85	0	118	0	0
T86	0	635	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	133532	0	0
T4	2014	1019	0	0
T5	34029	0	0	0
T6	1075	294	0	0
T7	0	621	0	0
T8	0	385	0	0
T9	2789	0	0	0
T10	2086	0	0	0
T14	1625	0	0	0
T15	0	209	0	0
T16	0	613	0	0
T30	32026	0	0	0
T34	1913	0	0	0
T39	1193	446	0	0
T44	204185	0	0	0
T60	0	444	0	0
T85	0	119	0	0
T86	0	636	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12038049	11862250	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	1902	1773	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0