Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T6,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T40,T42,T105
1	1	0	Not Covered
1	1	1	Covered	T9,T6,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T36,T43
1	0	1	Covered	T9,T6,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T14

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T6,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	23478146	2347999	0	0
DepthKnown_A	24148822	23797224	0	0
RvalidKnown_A	24148822	23797224	0	0
WreadyKnown_A	24148822	23797224	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	23811954	2432610	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23478146	2347999	0	0
T6	598	204	0	0
T9	5578	1020	0	0
T10	4172	528	0	0
T11	6212	918	0	0
T14	3250	383	0	0
T34	3826	457	0	0
T44	408370	0	0	0
T52	0	252	0	0
T59	3426	325	0	0
T84	3586	0	0	0
T87	1678	0	0	0
T88	0	739	0	0
T89	0	273	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148822	23797224	0	0
T1	9442	9244	0	0
T2	34928	33400	0	0
T3	1842	1682	0	0
T4	4028	3770	0	0
T5	68058	66188	0	0
T26	2602	2424	0	0
T27	5354	5240	0	0
T28	5332	5224	0	0
T29	5370	5264	0	0
T30	64052	62740	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148822	23797224	0	0
T1	9442	9244	0	0
T2	34928	33400	0	0
T3	1842	1682	0	0
T4	4028	3770	0	0
T5	68058	66188	0	0
T26	2602	2424	0	0
T27	5354	5240	0	0
T28	5332	5224	0	0
T29	5370	5264	0	0
T30	64052	62740	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24148822	23797224	0	0
T1	9442	9244	0	0
T2	34928	33400	0	0
T3	1842	1682	0	0
T4	4028	3770	0	0
T5	68058	66188	0	0
T26	2602	2424	0	0
T27	5354	5240	0	0
T28	5332	5224	0	0
T29	5370	5264	0	0
T30	64052	62740	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	23811954	2432610	0	0
T6	2150	892	0	0
T9	5578	1020	0	0
T10	4172	528	0	0
T11	6212	918	0	0
T14	3250	383	0	0
T34	3826	457	0	0
T44	408370	0	0	0
T52	0	252	0	0
T59	3426	325	0	0
T84	3586	0	0	0
T87	1678	0	0	0
T88	0	739	0	0
T89	0	273	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T106,T103,T107
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T6,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T40,T42,T105
1	1	0	Not Covered
1	1	1	Covered	T9,T6,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35,T36,T43
1	0	1	Covered	T9,T6,T10
1	1	0	Not Covered
1	1	1	Covered	T11,T20,T23

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T6,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	11739073	1167848	0	0
DepthKnown_A	12074411	11898612	0	0
RvalidKnown_A	12074411	11898612	0	0
WreadyKnown_A	12074411	11898612	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	11905977	1209953	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11739073	1167848	0	0
T6	299	109	0	0
T9	2789	485	0	0
T10	2086	234	0	0
T11	3106	455	0	0
T14	1625	193	0	0
T34	1913	234	0	0
T44	204185	0	0	0
T52	0	127	0	0
T59	1713	165	0	0
T84	1793	0	0	0
T87	839	0	0	0
T88	0	376	0	0
T89	0	133	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	11905977	1209953	0	0
T6	1075	448	0	0
T9	2789	485	0	0
T10	2086	234	0	0
T11	3106	455	0	0
T14	1625	193	0	0
T34	1913	234	0	0
T44	204185	0	0	0
T52	0	127	0	0
T59	1713	165	0	0
T84	1793	0	0	0
T87	839	0	0	0
T88	0	376	0	0
T89	0	133	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T6,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T108,T109
1	1	0	Not Covered
1	1	1	Covered	T9,T6,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T110,T111,T112
1	0	1	Covered	T9,T6,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T6,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	11739073	1180151	0	0
DepthKnown_A	12074411	11898612	0	0
RvalidKnown_A	12074411	11898612	0	0
WreadyKnown_A	12074411	11898612	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	11905977	1222657	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11739073	1180151	0	0
T6	299	95	0	0
T9	2789	535	0	0
T10	2086	294	0	0
T11	3106	463	0	0
T14	1625	190	0	0
T34	1913	223	0	0
T44	204185	0	0	0
T52	0	125	0	0
T59	1713	160	0	0
T84	1793	0	0	0
T87	839	0	0	0
T88	0	363	0	0
T89	0	140	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12074411	11898612	0	0
T1	4721	4622	0	0
T2	17464	16700	0	0
T3	921	841	0	0
T4	2014	1885	0	0
T5	34029	33094	0	0
T26	1301	1212	0	0
T27	2677	2620	0	0
T28	2666	2612	0	0
T29	2685	2632	0	0
T30	32026	31370	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	11905977	1222657	0	0
T6	1075	444	0	0
T9	2789	535	0	0
T10	2086	294	0	0
T11	3106	463	0	0
T14	1625	190	0	0
T34	1913	223	0	0
T44	204185	0	0	0
T52	0	125	0	0
T59	1713	160	0	0
T84	1793	0	0	0
T87	839	0	0	0
T88	0	363	0	0
T89	0	140	0	0