| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 83.33 | 83.33 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| edn_alert_cg | 83.33 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 1 | 5 | 83.33 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_recov_alert_cg | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 6 | 1 | 5 | 83.33 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| auto[csrng_ack_err] | 0 | 1 | 1 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[edn_enable_field_alert] | 57 | 1 | T28 | 1 | T31 | 1 | T29 | 1 | ||||
| auto[boot_req_mode_field_alert] | 41 | 1 | T9 | 1 | T59 | 1 | T102 | 1 | ||||
| auto[auto_req_mode_field_alert] | 52 | 1 | T103 | 1 | T104 | 1 | T105 | 1 | ||||
| auto[cmd_fifo_rst_field_alert] | 50 | 1 | T10 | 1 | T82 | 1 | T84 | 1 | ||||
| auto[edn_bus_cmp_alert] | 200 | 1 | T9 | 1 | T10 | 1 | T28 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |