Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.94	93.94	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	93.94	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.94	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	2	19	90.48

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	2	19	90.48	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	154	1			T30	1		T41	1		T42	1
auto_req_mode	117	1			T1	1		T3	1		T39	1
sw_mode	1856	1			T2	42		T23	1		T25	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

302

1

T1

1

T3

1

T23

1

single

97

1

T40

1

T30

1

T41

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	951	1			T3	1		T25	1		T4	31
auto[2]	22	1			T283	1		T276	1		T284	1
auto[3]	153	1			T51	16		T72	1		T98	8
auto[4]	99	1			T23	1		T26	1		T73	1
auto[5]	133	1			T48	1		T285	68		T286	2
auto[6]	52	1			T95	32		T75	1		T287	1
auto[7]	717	1			T1	1		T2	42		T30	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	2	19	90.48	2

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[4]]	[auto_req_mode]	0	1	1
[auto[6]]	[auto_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	87	1			T41	1		T275	1		T100	1
auto[1]	auto_req_mode	79	1			T3	1		T39	1		T40	1
auto[1]	sw_mode	785	1			T25	1		T4	31		T56	1
auto[2]	boot_req_mode	4	1			T283	1		T284	1		T288	1
auto[2]	auto_req_mode	1	1			T289	1		-	-		-	-
auto[2]	sw_mode	17	1			T276	1		T290	1		T291	1
auto[3]	boot_req_mode	9	1			T44	1		T292	1		T293	1
auto[3]	auto_req_mode	1	1			T12	1		-	-		-	-
auto[3]	sw_mode	143	1			T51	16		T72	1		T98	8
auto[4]	boot_req_mode	8	1			T97	1		T294	1		T295	1
auto[4]	sw_mode	91	1			T23	1		T26	1		T73	1
auto[5]	boot_req_mode	5	1			T296	1		T297	1		T298	1
auto[5]	auto_req_mode	1	1			T299	1		-	-		-	-
auto[5]	sw_mode	127	1			T48	1		T285	68		T286	2
auto[6]	boot_req_mode	6	1			T75	1		T287	1		T300	1
auto[6]	sw_mode	46	1			T95	32		T301	1		T302	1
auto[7]	boot_req_mode	35	1			T30	1		T42	1		T43	1
auto[7]	auto_req_mode	35	1			T1	1		T46	1		T50	1
auto[7]	sw_mode	647	1			T2	42		T47	1		T38	21