Group : tb.dut.u_edn_cov_if::edn_error_cg
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Group : tb.dut.u_edn_cov_if::edn_error_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
87.50 87.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_error_cg 87.50 1 100 1 64 64




Group Instance : edn_error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64




Summary for Group Instance edn_error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 1 7 87.50


Variables for Group Instance edn_error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error_test 8 1 7 87.50 100 1 1 0


Summary for Variable cp_error_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 1 7 87.50


Automatically Generated Bins for cp_error_test

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[EdnFifoReadErrTest] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[EdnSfifoRescmdErrTest] 29 1 T15 2 T8 1 T16 9
auto[EdnSfifoGencmdErrTest] 32 1 T15 3 T16 8 T17 4
auto[EdnAckSmErrTest] 1140 1 T5 1 T6 1 T13 1
auto[EdnMainSmErrTest] 1140 1 T5 1 T6 1 T13 1
auto[EdnCntrErrTest] 108 1 T5 1 T13 1 T14 1
auto[EdnFifoWriteErrTest] 1 1 T8 1 - - - -
auto[EdnFifoStateErrTest] 60 1 T15 5 T16 17 T17 8

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