Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
58.33 58.33 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_sw_cmd_sts_cg 58.33 1 100 1 64 64



Group Instance : edn_sw_cmd_sts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
58.33 1 100 1 64 64



Summary for Group Instance edn_sw_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 5 7 58.33


Variables for Group Instance edn_sw_cmd_sts_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_cmd_ack_cg 2 0 2 100.00 100 1 1 0
cp_cmd_rdy_cg 2 0 2 100.00 100 1 1 0
cp_cmd_reg_rdy_cg 2 0 2 100.00 100 1 1 0
cp_cmd_sts_cg 6 5 1 16.67 100 1 1 0


Summary for Variable cp_cmd_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_ack_cg

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
no_ack 16073 1 T1 21 T2 159 T3 13
ack 11939 1 T1 5 T2 160 T3 1


Summary for Variable cp_cmd_rdy_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_rdy_cg

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
not_ready 15344 1 T1 21 T2 155 T3 12
ready 12668 1 T1 5 T2 164 T3 2


Summary for Variable cp_cmd_reg_rdy_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_reg_rdy_cg

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
not_ready 313 1 T1 1 T2 4 T3 1
ready 27699 1 T1 25 T2 315 T3 13


Summary for Variable cp_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 6 5 1 16.67


Automatically Generated Bins for cp_cmd_sts_cg

Uncovered bins
NAME   COUNT   AT LEAST   NUMBER   STATUS   
auto[CMD_STS_INVALID_ACMD] 0 1 1
auto[CMD_STS_INVALID_GEN_CMD] 0 1 1
auto[CMD_STS_INVALID_CMD_SEQ] 0 1 1
auto[CMD_STS_RESEED_CNT_EXCEEDED] 0 1 1
auto[CMD_STS_UNDRIVEN] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CMD_STS_SUCCESS] 28012 1 T1 26 T2 319 T3 14