Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149662	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

277559

1

T1

75

T2

3288

T3

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	189666	1			T1	72		T2	1624		T3	21
values[0x0]	112456	1			T1	35		T2	1303		T3	30
values[0x1]	125099	1			T1	37		T2	1493		T3	30

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	101200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

326021

1

T1

96

T2

3632

T3

62

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1700	1			T1	3		T2	24		T4	29
valid_sources[0x01]	1542	1			T2	12		T23	2		T4	34
valid_sources[0x02]	1480	1			T2	21		T4	29		T26	2
valid_sources[0x03]	1791	1			T2	8		T4	31		T26	4
valid_sources[0x04]	1287	1			T1	1		T2	15		T9	4
valid_sources[0x05]	1481	1			T1	1		T2	21		T4	23
valid_sources[0x06]	1921	1			T2	15		T4	26		T26	2
valid_sources[0x07]	1602	1			T2	24		T10	1		T4	30
valid_sources[0x08]	1433	1			T2	11		T4	29		T26	6
valid_sources[0x09]	2229	1			T1	1		T2	12		T3	6
valid_sources[0x0a]	2008	1			T2	16		T24	1		T4	34
valid_sources[0x0b]	1711	1			T1	2		T2	14		T4	33
valid_sources[0x0c]	1424	1			T1	2		T2	16		T4	30
valid_sources[0x0d]	1198	1			T1	1		T2	20		T4	28
valid_sources[0x0e]	1761	1			T2	24		T9	8		T25	1
valid_sources[0x0f]	2055	1			T1	1		T2	13		T4	22
valid_sources[0x10]	1763	1			T2	13		T4	26		T26	4
valid_sources[0x11]	1755	1			T2	18		T4	36		T26	1
valid_sources[0x12]	1331	1			T2	12		T23	1		T10	1
valid_sources[0x13]	1941	1			T2	17		T4	20		T26	1
valid_sources[0x14]	2360	1			T2	14		T4	22		T26	3
valid_sources[0x15]	1912	1			T2	20		T23	1		T4	27
valid_sources[0x16]	3112	1			T1	1		T2	26		T10	1
valid_sources[0x17]	1628	1			T1	1		T2	17		T9	3
valid_sources[0x18]	1547	1			T2	17		T10	2		T4	28
valid_sources[0x19]	1320	1			T2	18		T4	27		T40	1
valid_sources[0x1a]	1295	1			T2	12		T10	2		T4	36
valid_sources[0x1b]	1834	1			T2	20		T25	2		T4	23
valid_sources[0x1c]	1195	1			T2	13		T4	24		T26	1
valid_sources[0x1d]	1571	1			T2	20		T4	31		T47	3
valid_sources[0x1e]	3284	1			T1	1		T2	18		T3	5
valid_sources[0x1f]	1994	1			T1	1		T2	11		T4	23
valid_sources[0x20]	1364	1			T2	16		T3	1		T24	1
valid_sources[0x21]	1309	1			T1	1		T2	23		T3	3
valid_sources[0x22]	1454	1			T2	16		T3	1		T4	29
valid_sources[0x23]	1525	1			T1	2		T2	15		T4	39
valid_sources[0x24]	1664	1			T2	17		T23	2		T4	26
valid_sources[0x25]	1608	1			T2	20		T9	1		T4	31
valid_sources[0x26]	1669	1			T2	19		T4	22		T26	3
valid_sources[0x27]	1813	1			T2	18		T4	31		T26	3
valid_sources[0x28]	1799	1			T2	14		T23	4		T4	39
valid_sources[0x29]	1303	1			T1	1		T2	12		T23	4
valid_sources[0x2a]	1482	1			T2	18		T4	20		T26	1
valid_sources[0x2b]	1311	1			T2	16		T4	42		T26	3
valid_sources[0x2c]	2881	1			T2	12		T4	29		T26	1
valid_sources[0x2d]	1633	1			T1	1		T2	21		T4	24
valid_sources[0x2e]	1348	1			T2	11		T23	2		T4	30
valid_sources[0x2f]	1149	1			T2	15		T4	28		T26	3
valid_sources[0x30]	1782	1			T1	1		T2	18		T23	2
valid_sources[0x31]	1949	1			T1	1		T2	25		T4	33
valid_sources[0x32]	1486	1			T1	1		T2	16		T23	2
valid_sources[0x33]	2623	1			T2	22		T23	1		T4	26
valid_sources[0x34]	1685	1			T1	1		T2	22		T4	20
valid_sources[0x35]	1343	1			T2	19		T4	33		T26	3
valid_sources[0x36]	2027	1			T2	20		T4	21		T26	1
valid_sources[0x37]	1110	1			T2	17		T4	25		T30	3
valid_sources[0x38]	1137	1			T1	1		T2	16		T23	2
valid_sources[0x39]	1468	1			T2	18		T10	1		T4	41
valid_sources[0x3a]	1360	1			T2	15		T9	2		T4	30
valid_sources[0x3b]	1438	1			T1	1		T2	17		T4	23
valid_sources[0x3c]	1526	1			T1	1		T2	20		T4	25
valid_sources[0x3d]	1529	1			T2	19		T3	6		T10	1
valid_sources[0x3e]	1678	1			T2	13		T4	33		T51	11
valid_sources[0x3f]	2341	1			T1	1		T2	23		T4	36
valid_sources[0x40]	1136	1			T1	2		T2	17		T4	29
valid_sources[0x41]	1489	1			T2	15		T4	25		T6	3
valid_sources[0x42]	1517	1			T2	21		T24	1		T10	2
valid_sources[0x43]	1285	1			T1	1		T2	17		T9	1
valid_sources[0x44]	1638	1			T1	2		T2	19		T4	37
valid_sources[0x45]	1858	1			T2	22		T4	38		T26	1
valid_sources[0x46]	1354	1			T2	19		T4	24		T26	2
valid_sources[0x47]	1425	1			T2	25		T4	18		T30	1
valid_sources[0x48]	1251	1			T2	13		T4	30		T26	1
valid_sources[0x49]	1590	1			T1	1		T2	14		T10	2
valid_sources[0x4a]	2311	1			T2	17		T25	1		T4	29
valid_sources[0x4b]	1258	1			T1	1		T2	14		T4	29
valid_sources[0x4c]	2115	1			T1	3		T2	12		T23	4
valid_sources[0x4d]	1380	1			T2	21		T23	1		T25	3
valid_sources[0x4e]	1607	1			T1	1		T2	13		T4	27
valid_sources[0x4f]	1401	1			T1	1		T2	17		T4	25
valid_sources[0x50]	2234	1			T2	21		T4	38		T40	1
valid_sources[0x51]	1566	1			T1	1		T2	14		T4	32
valid_sources[0x52]	1453	1			T2	22		T9	8		T10	1
valid_sources[0x53]	1649	1			T2	9		T10	1		T4	28
valid_sources[0x54]	1614	1			T1	1		T2	17		T23	1
valid_sources[0x55]	1599	1			T1	1		T2	14		T10	1
valid_sources[0x56]	1923	1			T2	9		T9	1		T24	1
valid_sources[0x57]	2247	1			T1	1		T2	25		T9	1
valid_sources[0x58]	1187	1			T1	1		T2	22		T4	16
valid_sources[0x59]	1415	1			T2	20		T23	3		T4	28
valid_sources[0x5a]	1696	1			T2	13		T10	1		T4	40
valid_sources[0x5b]	2996	1			T2	27		T9	3		T23	1
valid_sources[0x5c]	1460	1			T1	1		T2	13		T4	34
valid_sources[0x5d]	1750	1			T1	2		T2	16		T4	21
valid_sources[0x5e]	1637	1			T2	12		T24	1		T4	33
valid_sources[0x5f]	1488	1			T2	10		T3	6		T4	47
valid_sources[0x60]	2281	1			T1	1		T2	21		T25	1
valid_sources[0x61]	1414	1			T1	1		T2	17		T4	27
valid_sources[0x62]	2139	1			T1	3		T2	25		T4	29
valid_sources[0x63]	1585	1			T2	18		T25	1		T4	43
valid_sources[0x64]	1482	1			T1	1		T2	21		T4	38
valid_sources[0x65]	1809	1			T1	3		T2	16		T23	3
valid_sources[0x66]	1223	1			T2	27		T4	24		T26	2
valid_sources[0x67]	1485	1			T2	15		T10	2		T4	30
valid_sources[0x68]	1538	1			T1	1		T2	5		T4	28
valid_sources[0x69]	1670	1			T2	18		T10	1		T4	31
valid_sources[0x6a]	1482	1			T1	1		T2	16		T4	25
valid_sources[0x6b]	2434	1			T2	16		T4	34		T30	1
valid_sources[0x6c]	2338	1			T1	2		T2	13		T4	30
valid_sources[0x6d]	1515	1			T2	19		T4	30		T51	9
valid_sources[0x6e]	1344	1			T2	24		T4	32		T26	1
valid_sources[0x6f]	1783	1			T2	17		T23	1		T4	33
valid_sources[0x70]	1536	1			T1	1		T2	13		T4	30
valid_sources[0x71]	1719	1			T2	22		T4	27		T26	1
valid_sources[0x72]	2143	1			T2	13		T23	2		T4	36
valid_sources[0x73]	1582	1			T1	1		T2	10		T4	35
valid_sources[0x74]	1505	1			T1	4		T2	14		T4	22
valid_sources[0x75]	1682	1			T2	18		T4	36		T38	21
valid_sources[0x76]	1868	1			T2	15		T4	30		T26	1
valid_sources[0x77]	1299	1			T2	15		T4	29		T30	1
valid_sources[0x78]	1556	1			T2	16		T4	29		T26	2
valid_sources[0x79]	2002	1			T2	20		T10	1		T4	25
valid_sources[0x7a]	1568	1			T2	15		T4	27		T42	3
valid_sources[0x7b]	1423	1			T1	2		T2	18		T23	2
valid_sources[0x7c]	1340	1			T2	18		T24	1		T4	43
valid_sources[0x7d]	1907	1			T1	1		T2	12		T3	3
valid_sources[0x7e]	1472	1			T2	23		T4	35		T26	8
valid_sources[0x7f]	1869	1			T2	24		T4	33		T39	1
valid_sources[0x80]	1541	1			T2	22		T4	25		T26	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75502

1

T1

6

T2

920

T3

2

values[0x0]

all_enables

biggest_size

102044

1

T1

33

T2

1178

T3

26

values[0x1]

all_enables

biggest_size

100013

1

T1

36

T2

1190

T3

28