Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1732	1			T1	5		T2	21		T23	3
non_zero_bins[1]	1153	1			T1	4		T2	7		T3	1
zero	6006	1			T1	1		T2	54		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	287	1			T2	3		T23	1		T4	3
uni	2139	1			T1	1		T2	26		T23	1
gen	2990	1			T1	6		T2	22		T9	3
res	593	1			T1	2		T2	5		T3	3
ins	2882	1			T1	1		T2	26		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5574

1

T1

4

T2

53

T9

3

mubi_true

3317

1

T1

6

T2

29

T3

4

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

26

1

T84

1

T62

1

T67

1

pass

8865

1

T1

10

T2

82

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	67	1			T51	1		T47	1		T38	1
upd	non_zero_bins[0]	pass	mubi_true	72	1			T2	1		T23	1		T4	2
upd	non_zero_bins[1]	pass	mubi_false	53	1			T4	1		T274	1		T100	1
upd	non_zero_bins[1]	pass	mubi_true	48	1			T2	1		T275	1		T223	3
upd	zero	pass	mubi_false	24	1			T2	1		T223	1		T276	1
upd	zero	pass	mubi_true	23	1			T51	1		T38	2		T98	1
uni	zero	pass	mubi_false	1603	1			T1	1		T2	17		T23	1
uni	zero	pass	mubi_true	536	1			T2	9		T4	10		T51	7
gen	non_zero_bins[0]	pass	mubi_false	322	1			T2	3		T4	6		T51	4
gen	non_zero_bins[0]	pass	mubi_true	372	1			T1	5		T2	3		T23	1
gen	non_zero_bins[1]	pass	mubi_false	180	1			T1	1		T2	1		T4	1
gen	non_zero_bins[1]	pass	mubi_true	244	1			T2	2		T4	1		T51	1
gen	zero	fail	mubi_false	22	1			T84	1		T62	1		T67	1
gen	zero	pass	mubi_false	1179	1			T2	10		T9	1		T25	1
gen	zero	pass	mubi_true	671	1			T2	3		T9	2		T10	2
res	non_zero_bins[0]	pass	mubi_false	148	1			T2	3		T4	1		T51	1
res	non_zero_bins[0]	pass	mubi_true	120	1			T2	1		T51	1		T39	2
res	non_zero_bins[1]	pass	mubi_false	99	1			T1	2		T4	1		T20	3
res	non_zero_bins[1]	pass	mubi_true	92	1			T51	1		T18	2		T38	1
res	zero	fail	mubi_false	4	1			T152	1		T153	1		T154	1
res	zero	pass	mubi_false	73	1			T2	1		T9	1		T4	1
res	zero	pass	mubi_true	57	1			T3	3		T4	1		T40	2
ins	non_zero_bins[0]	pass	mubi_false	313	1			T2	5		T4	2		T26	1
ins	non_zero_bins[0]	pass	mubi_true	318	1			T2	5		T23	1		T4	4
ins	non_zero_bins[1]	pass	mubi_false	209	1			T2	1		T4	2		T26	1
ins	non_zero_bins[1]	pass	mubi_true	228	1			T1	1		T2	2		T3	1
ins	zero	pass	mubi_false	1278	1			T2	11		T9	1		T10	1
ins	zero	pass	mubi_true	536	1			T2	2		T9	1		T10	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded