Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T28,T29,T13
1	1	Covered	T28,T31,T29

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T3,T39,T6
1	1	Covered	T1,T3,T9

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T28
1	0	Covered	T5,T6,T35

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T9,T10,T28
1	Covered	T5,T6,T35

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T9,T10,T28
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T9,T10,T5
1	Covered	T5,T6,T35

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T1,T3,T9
AutoCaptGenCnt	143	Covered	T1,T3,T9
AutoCaptReseedCnt	141	Covered	T1,T3,T9
AutoDispatch	125	Covered	T1,T3,T9
AutoFirstAckWait	119	Covered	T1,T3,T9
AutoLoadIns	69	Covered	T1,T3,T9
AutoSendGenCmd	150	Covered	T1,T3,T9
AutoSendReseedCmd	162	Covered	T1,T3,T9
BootDone	98	Covered	T30,T41,T13
BootGenAckWait	90	Covered	T30,T41,T13
BootInsAckWait	80	Covered	T28,T29,T30
BootLoadGen	85	Covered	T30,T41,T13
BootLoadIns	65	Covered	T28,T31,T29
BootLoadUni	102	Covered	T30,T82,T85
BootPulse	94	Covered	T30,T41,T13
BootUniAckWait	107	Covered	T30,T82,T85
Error	188	Covered	T5,T6,T35
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T9,T10,T28
SWPortMode	74	Covered	T1,T2,T9

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T1,T3,T9
AutoAckWait->Error	188	Covered	T7,T114,T115
AutoAckWait->Idle	211	Covered	T3,T39,T40
AutoAckWait->RejectCsrngEntropy	188	Covered	T9,T84,T62
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T1,T3,T9
AutoCaptGenCnt->Error	188	Covered	T116,T117,T118
AutoCaptGenCnt->Idle	211	Covered	T119,T120,T121
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T10,T71,T122
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T1,T3,T9
AutoCaptReseedCnt->Error	188	Covered	T8,T123,T124
AutoCaptReseedCnt->Idle	211	Covered	T40,T125,T126
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T127,T128,T129
AutoDispatch->AutoCaptGenCnt	143	Covered	T1,T3,T9
AutoDispatch->AutoCaptReseedCnt	141	Covered	T1,T3,T9
AutoDispatch->Error	188	Covered	T130,T131,T132
AutoDispatch->Idle	138	Covered	T1,T18,T19
AutoDispatch->RejectCsrngEntropy	188	Covered	T104,T133,T134
AutoFirstAckWait->AutoDispatch	125	Covered	T1,T3,T9
AutoFirstAckWait->Error	188	Covered	T135
AutoFirstAckWait->Idle	211	Covered	T3,T39,T22
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T59,T108,T105
AutoLoadIns->AutoFirstAckWait	119	Covered	T1,T3,T9
AutoLoadIns->Error	188	Covered	T136,T137,T138
AutoLoadIns->Idle	211	Covered	T10,T6,T84
AutoLoadIns->RejectCsrngEntropy	188	Covered	T85,T139,T140
AutoSendGenCmd->AutoAckWait	156	Covered	T1,T3,T9
AutoSendGenCmd->Error	188	Covered	T106,T141
AutoSendGenCmd->Idle	211	Covered	T142,T143,T144
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T145,T146,T147
AutoSendReseedCmd->AutoAckWait	168	Covered	T1,T3,T9
AutoSendReseedCmd->Error	188	Covered	T148,T149
AutoSendReseedCmd->Idle	211	Covered	T68,T150,T151
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T152,T153,T154
BootDone->BootLoadUni	102	Covered	T30,T82,T85
BootDone->Error	188	Covered	T155,T156,T157
BootDone->Idle	211	Covered	T52,T76,T158
BootDone->RejectCsrngEntropy	188	Covered	T159,T160,T161
BootGenAckWait->BootPulse	94	Covered	T30,T41,T13
BootGenAckWait->Error	188	Covered	T54,T101,T162
BootGenAckWait->Idle	211	Covered	T163,T164,T165
BootGenAckWait->RejectCsrngEntropy	188	Covered	T166,T167,T168
BootInsAckWait->BootLoadGen	85	Covered	T30,T41,T13
BootInsAckWait->Error	188	Covered	T13,T52,T169
BootInsAckWait->Idle	211	Covered	T13,T66,T14
BootInsAckWait->RejectCsrngEntropy	188	Covered	T28,T29,T170
BootLoadGen->BootGenAckWait	90	Covered	T30,T41,T13
BootLoadGen->Error	188	Covered	T66,T171,T172
BootLoadGen->Idle	211	Covered	T78,T173,T174
BootLoadGen->RejectCsrngEntropy	188	Covered	T175,T176,T177
BootLoadIns->BootInsAckWait	80	Covered	T28,T29,T30
BootLoadIns->Error	188	Covered	T99,T178,T179
BootLoadIns->Idle	211	Covered	T180,T181
BootLoadIns->RejectCsrngEntropy	188	Covered	T31,T103,T96
BootLoadUni->BootUniAckWait	107	Covered	T30,T82,T85
BootLoadUni->Error	188	Covered	T182
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T183,T184,T185
BootPulse->BootDone	98	Covered	T30,T41,T13
BootPulse->Error	188	Covered	T14,T158
BootPulse->Idle	211	Covered	T178,T186,T187
BootPulse->RejectCsrngEntropy	188	Covered	T188,T189,T190
BootUniAckWait->Error	188	Not Covered
BootUniAckWait->Idle	112	Covered	T30,T82,T85
BootUniAckWait->RejectCsrngEntropy	188	Covered	T82,T109,T102
Idle->AutoLoadIns	69	Covered	T1,T3,T9
Idle->BootLoadIns	65	Covered	T28,T31,T29
Idle->Error	188	Covered	T15,T16,T17
Idle->RejectCsrngEntropy	188	Covered	T9,T28,T29
Idle->SWPortMode	74	Covered	T1,T2,T9
RejectCsrngEntropy->Error	188	Covered	T191,T192,T193
RejectCsrngEntropy->Idle	211	Covered	T9,T10,T28
SWPortMode->Error	188	Covered	T5,T35,T65
SWPortMode->Idle	211	Covered	T2,T9,T4
SWPortMode->RejectCsrngEntropy	188	Covered	T10,T31,T84

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T31,T29
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T9
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T28,T31,T29
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T28,T29,T30
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T28,T29,T30
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T30,T41,T13
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T30,T41,T13
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T30,T41,T13
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T30,T41,T13
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T82,T85
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T41,T13,T82
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T30,T82,T85
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T30,T82,T42
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T30,T82,T85
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T3,T9
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T3,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T3,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T3,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T3,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T18,T19
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T3,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T3,T9
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T3,T39
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T9
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T9
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T28
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T35
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T15,T92

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T5,T6,T35
1	0	1	-	Not Covered
1	0	0	-	Covered	T9,T10,T28
0	-	-	1	Covered	T3,T9,T10
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	10249775	154986	0	0
FpvSecCmErrorStEscalate_A	10249775	156154	0	0
u_state_regs_A	10214194	10028703	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	154986	0	0
T5	671	333	0	0
T6	2417	1060	0	0
T13	0	1072	0	0
T14	0	592	0	0
T15	0	10192	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	390	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	644	0	0
T53	0	291	0	0
T56	2853	0	0	0
T65	0	639	0	0
T66	0	1080	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	156154	0	0
T5	671	334	0	0
T6	2417	1061	0	0
T13	0	1073	0	0
T14	0	593	0	0
T15	0	10322	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	391	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	645	0	0
T53	0	292	0	0
T56	2853	0	0	0
T65	0	640	0	0
T66	0	1081	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10214194	10028703	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0