Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T9
DataWait	75	Covered	T1,T2,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T6,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T194,T195,T196
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T9
DataWait->AckPls	80	Covered	T1,T2,T9
DataWait->Disabled	107	Covered	T4,T163,T173
DataWait->Error	99	Covered	T14,T52,T54
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T197,T180,T198
EndPointClear->Error	99	Covered	T15,T99,T178
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T9
Idle->Disabled	107	Covered	T2,T3,T9
Idle->Error	99	Covered	T5,T6,T35

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T9
Idle	-	1	0	-	Covered	T1,T2,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T9
DataWait	-	-	-	0	Covered	T1,T2,T9
AckPls	-	-	-	-	Covered	T1,T2,T9
Error	-	-	-	-	Covered	T5,T6,T35
default	-	-	-	-	Covered	T35,T65,T66

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T35
0	1	Covered	T3,T9,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	71748425	1094402	0	0
FpvSecCmErrorStEscalate_A	71748425	1102578	0	0
u_state_regs_A	71712844	70414407	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71748425	1094402	0	0
T5	4697	2331	0	0
T6	16919	7770	0	0
T13	0	7504	0	0
T14	0	4144	0	0
T15	0	71344	0	0
T28	12943	0	0	0
T29	11921	0	0	0
T31	10535	0	0	0
T33	14756	0	0	0
T35	0	2680	0	0
T39	17444	0	0	0
T40	19894	0	0	0
T51	182959	0	0	0
T52	0	4508	0	0
T53	0	2037	0	0
T56	19971	0	0	0
T65	0	4423	0	0
T66	0	7510	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71748425	1102578	0	0
T5	4697	2338	0	0
T6	16919	7777	0	0
T13	0	7511	0	0
T14	0	4151	0	0
T15	0	72254	0	0
T28	12943	0	0	0
T29	11921	0	0	0
T31	10535	0	0	0
T33	14756	0	0	0
T35	0	2687	0	0
T39	17444	0	0	0
T40	19894	0	0	0
T51	182959	0	0	0
T52	0	4515	0	0
T53	0	2044	0	0
T56	19971	0	0	0
T65	0	4430	0	0
T66	0	7517	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71712844	70414407	0	0
T1	35462	34923	0	0
T2	913262	912387	0	0
T3	20104	19404	0	0
T4	947464	946799	0	0
T9	12670	12313	0	0
T10	19873	19306	0	0
T23	15169	14714	0	0
T24	8645	8071	0	0
T25	11571	11144	0	0
T26	12166	11774	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T9
DataWait	75	Covered	T1,T2,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T6,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T9
DataWait->AckPls	80	Covered	T1,T2,T9
DataWait->Disabled	107	Covered	T4,T163,T173
DataWait->Error	99	Covered	T52,T199,T165
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T197,T180,T198
EndPointClear->Error	99	Covered	T15,T16,T17
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T9
Idle->Disabled	107	Covered	T2,T3,T9
Idle->Error	99	Covered	T5,T6,T13

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T9
Idle	-	1	0	-	Covered	T1,T2,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T9
DataWait	-	-	-	0	Covered	T1,T2,T9
AckPls	-	-	-	-	Covered	T1,T2,T9
Error	-	-	-	-	Covered	T5,T6,T35
default	-	-	-	-	Covered	T35,T65,T66

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T35
0	1	Covered	T3,T9,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10249775	153986	0	0
FpvSecCmErrorStEscalate_A	10249775	155154	0	0
u_state_regs_A	10214194	10028703	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	153986	0	0
T5	671	333	0	0
T6	2417	1110	0	0
T13	0	1072	0	0
T14	0	592	0	0
T15	0	10192	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	340	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	644	0	0
T53	0	291	0	0
T56	2853	0	0	0
T65	0	589	0	0
T66	0	1030	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	155154	0	0
T5	671	334	0	0
T6	2417	1111	0	0
T13	0	1073	0	0
T14	0	593	0	0
T15	0	10322	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	341	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	645	0	0
T53	0	292	0	0
T56	2853	0	0	0
T65	0	590	0	0
T66	0	1031	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10214194	10028703	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T26,T29,T30
DataWait	75	Covered	T26,T29,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T6,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T26,T29,T30
DataWait->AckPls	80	Covered	T26,T29,T30
DataWait->Disabled	107	Covered	T174,T200,T119
DataWait->Error	99	Covered	T14,T86,T182
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T197,T180,T198
EndPointClear->Error	99	Covered	T15,T99,T178
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T26,T29,T30
Idle->Disabled	107	Covered	T2,T3,T9
Idle->Error	99	Covered	T5,T6,T35

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T26,T29,T30
Idle	-	1	0	-	Covered	T26,T29,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T26,T29,T30
DataWait	-	-	-	0	Covered	T26,T29,T30
AckPls	-	-	-	-	Covered	T26,T29,T30
Error	-	-	-	-	Covered	T5,T6,T35
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T35
0	1	Covered	T3,T9,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10249775	156736	0	0
FpvSecCmErrorStEscalate_A	10249775	157904	0	0
u_state_regs_A	10249775	10064284	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	156736	0	0
T5	671	333	0	0
T6	2417	1110	0	0
T13	0	1072	0	0
T14	0	592	0	0
T15	0	10192	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	390	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	644	0	0
T53	0	291	0	0
T56	2853	0	0	0
T65	0	639	0	0
T66	0	1080	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	157904	0	0
T5	671	334	0	0
T6	2417	1111	0	0
T13	0	1073	0	0
T14	0	593	0	0
T15	0	10322	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	391	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	645	0	0
T53	0	292	0	0
T56	2853	0	0	0
T65	0	640	0	0
T66	0	1081	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T23,T26
DataWait	75	Covered	T1,T23,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T6,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T23,T26
DataWait->AckPls	80	Covered	T1,T23,T26
DataWait->Disabled	107	Covered	T143,T201,T202
DataWait->Error	99	Covered	T130,T203,T116
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T197,T180,T198
EndPointClear->Error	99	Covered	T15,T99,T178
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T23,T26
Idle->Disabled	107	Covered	T2,T3,T9
Idle->Error	99	Covered	T5,T6,T35

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T23,T26
Idle	-	1	0	-	Covered	T1,T23,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T23,T26
DataWait	-	-	-	0	Covered	T1,T23,T26
AckPls	-	-	-	-	Covered	T1,T23,T26
Error	-	-	-	-	Covered	T5,T6,T35
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T35
0	1	Covered	T3,T9,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10249775	156736	0	0
FpvSecCmErrorStEscalate_A	10249775	157904	0	0
u_state_regs_A	10249775	10064284	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	156736	0	0
T5	671	333	0	0
T6	2417	1110	0	0
T13	0	1072	0	0
T14	0	592	0	0
T15	0	10192	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	390	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	644	0	0
T53	0	291	0	0
T56	2853	0	0	0
T65	0	639	0	0
T66	0	1080	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	157904	0	0
T5	671	334	0	0
T6	2417	1111	0	0
T13	0	1073	0	0
T14	0	593	0	0
T15	0	10322	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	391	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	645	0	0
T53	0	292	0	0
T56	2853	0	0	0
T65	0	640	0	0
T66	0	1081	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T39,T40,T30
DataWait	75	Covered	T39,T40,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T6,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T39,T40,T30
DataWait->AckPls	80	Covered	T39,T40,T30
DataWait->Disabled	107	Covered	T78,T204
DataWait->Error	99	Covered	T117,T205,T138
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T197,T180,T198
EndPointClear->Error	99	Covered	T15,T99,T178
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T39,T40,T30
Idle->Disabled	107	Covered	T2,T3,T9
Idle->Error	99	Covered	T5,T6,T35

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T39,T40,T30
Idle	-	1	0	-	Covered	T39,T40,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T39,T40,T30
DataWait	-	-	-	0	Covered	T39,T40,T30
AckPls	-	-	-	-	Covered	T39,T40,T30
Error	-	-	-	-	Covered	T5,T6,T35
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T35
0	1	Covered	T3,T9,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10249775	156736	0	0
FpvSecCmErrorStEscalate_A	10249775	157904	0	0
u_state_regs_A	10249775	10064284	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	156736	0	0
T5	671	333	0	0
T6	2417	1110	0	0
T13	0	1072	0	0
T14	0	592	0	0
T15	0	10192	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	390	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	644	0	0
T53	0	291	0	0
T56	2853	0	0	0
T65	0	639	0	0
T66	0	1080	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	157904	0	0
T5	671	334	0	0
T6	2417	1111	0	0
T13	0	1073	0	0
T14	0	593	0	0
T15	0	10322	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	391	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	645	0	0
T53	0	292	0	0
T56	2853	0	0	0
T65	0	640	0	0
T66	0	1081	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T41,T42,T43
DataWait	75	Covered	T41,T42,T43
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T6,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T41,T42,T43
DataWait->AckPls	80	Covered	T41,T42,T43
DataWait->Disabled	107	Covered	T206,T207,T121
DataWait->Error	99	Covered	T172,T208,T209
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T197,T180,T198
EndPointClear->Error	99	Covered	T15,T99,T178
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T41,T42,T43
Idle->Disabled	107	Covered	T2,T3,T9
Idle->Error	99	Covered	T5,T6,T35

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T41,T42,T43
Idle	-	1	0	-	Covered	T41,T42,T43
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T41,T42,T43
DataWait	-	-	-	0	Covered	T41,T42,T43
AckPls	-	-	-	-	Covered	T41,T42,T43
Error	-	-	-	-	Covered	T5,T6,T35
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T35
0	1	Covered	T3,T9,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10249775	156736	0	0
FpvSecCmErrorStEscalate_A	10249775	157904	0	0
u_state_regs_A	10249775	10064284	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	156736	0	0
T5	671	333	0	0
T6	2417	1110	0	0
T13	0	1072	0	0
T14	0	592	0	0
T15	0	10192	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	390	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	644	0	0
T53	0	291	0	0
T56	2853	0	0	0
T65	0	639	0	0
T66	0	1080	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	157904	0	0
T5	671	334	0	0
T6	2417	1111	0	0
T13	0	1073	0	0
T14	0	593	0	0
T15	0	10322	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	391	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	645	0	0
T53	0	292	0	0
T56	2853	0	0	0
T65	0	640	0	0
T66	0	1081	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T26,T30
DataWait	75	Covered	T1,T26,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T6,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T194,T195
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T26,T30
DataWait->AckPls	80	Covered	T1,T26,T30
DataWait->Disabled	107	Covered	T144,T210,T211
DataWait->Error	99	Covered	T54,T7,T101
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T197,T180,T198
EndPointClear->Error	99	Covered	T15,T99,T178
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T26,T30
Idle->Disabled	107	Covered	T2,T3,T9
Idle->Error	99	Covered	T5,T6,T35

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T26,T30
Idle	-	1	0	-	Covered	T1,T26,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T26,T30
DataWait	-	-	-	0	Covered	T1,T26,T30
AckPls	-	-	-	-	Covered	T1,T26,T30
Error	-	-	-	-	Covered	T5,T6,T35
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T35
0	1	Covered	T3,T9,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10249775	156736	0	0
FpvSecCmErrorStEscalate_A	10249775	157904	0	0
u_state_regs_A	10249775	10064284	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	156736	0	0
T5	671	333	0	0
T6	2417	1110	0	0
T13	0	1072	0	0
T14	0	592	0	0
T15	0	10192	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	390	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	644	0	0
T53	0	291	0	0
T56	2853	0	0	0
T65	0	639	0	0
T66	0	1080	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	157904	0	0
T5	671	334	0	0
T6	2417	1111	0	0
T13	0	1073	0	0
T14	0	593	0	0
T15	0	10322	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	391	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	645	0	0
T53	0	292	0	0
T56	2853	0	0	0
T65	0	640	0	0
T66	0	1081	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T30,T47
DataWait	75	Covered	T3,T30,T47
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T6,T35
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T196
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T30,T47
DataWait->AckPls	80	Covered	T3,T30,T47
DataWait->Disabled	107	Covered	T212
DataWait->Error	99	Covered	T213,T158,T214
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T15,T16,T17
EndPointClear->Disabled	107	Covered	T197,T180,T198
EndPointClear->Error	99	Covered	T15,T99,T178
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T30,T47
Idle->Disabled	107	Covered	T2,T3,T9
Idle->Error	99	Covered	T5,T6,T35

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T30,T47
Idle	-	1	0	-	Covered	T3,T5,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T30,T47
DataWait	-	-	-	0	Covered	T3,T30,T47
AckPls	-	-	-	-	Covered	T3,T30,T47
Error	-	-	-	-	Covered	T5,T6,T35
default	-	-	-	-	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T35
0	1	Covered	T3,T9,T10
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	10249775	156736	0	0
FpvSecCmErrorStEscalate_A	10249775	157904	0	0
u_state_regs_A	10249775	10064284	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	156736	0	0
T5	671	333	0	0
T6	2417	1110	0	0
T13	0	1072	0	0
T14	0	592	0	0
T15	0	10192	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	390	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	644	0	0
T53	0	291	0	0
T56	2853	0	0	0
T65	0	639	0	0
T66	0	1080	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	157904	0	0
T5	671	334	0	0
T6	2417	1111	0	0
T13	0	1073	0	0
T14	0	593	0	0
T15	0	10322	0	0
T28	1849	0	0	0
T29	1703	0	0	0
T31	1505	0	0	0
T33	2108	0	0	0
T35	0	391	0	0
T39	2492	0	0	0
T40	2842	0	0	0
T51	26137	0	0	0
T52	0	645	0	0
T53	0	292	0	0
T56	2853	0	0	0
T65	0	640	0	0
T66	0	1081	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0