Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T8,T36
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T37,T32
1	0	1	Covered	T1,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	19718166	554856	0	0
DepthKnown_A	20499550	20128568	0	0
RvalidKnown_A	20499550	20128568	0	0
WreadyKnown_A	20499550	20128568	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	20060862	649334	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19718166	554856	0	0
T1	10132	3929	0	0
T2	260932	0	0	0
T3	5744	2845	0	0
T4	270704	0	0	0
T6	0	89	0	0
T9	3620	418	0	0
T10	5678	1190	0	0
T18	0	7643	0	0
T23	4334	0	0	0
T24	2470	0	0	0
T25	3306	0	0	0
T26	3476	0	0	0
T31	0	67	0	0
T39	0	1916	0	0
T40	0	3053	0	0
T84	0	683	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20499550	20128568	0	0
T1	10132	9978	0	0
T2	260932	260682	0	0
T3	5744	5544	0	0
T4	270704	270514	0	0
T9	3620	3518	0	0
T10	5678	5516	0	0
T23	4334	4204	0	0
T24	2470	2306	0	0
T25	3306	3184	0	0
T26	3476	3364	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20499550	20128568	0	0
T1	10132	9978	0	0
T2	260932	260682	0	0
T3	5744	5544	0	0
T4	270704	270514	0	0
T9	3620	3518	0	0
T10	5678	5516	0	0
T23	4334	4204	0	0
T24	2470	2306	0	0
T25	3306	3184	0	0
T26	3476	3364	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20499550	20128568	0	0
T1	10132	9978	0	0
T2	260932	260682	0	0
T3	5744	5544	0	0
T4	270704	270514	0	0
T9	3620	3518	0	0
T10	5678	5516	0	0
T23	4334	4204	0	0
T24	2470	2306	0	0
T25	3306	3184	0	0
T26	3476	3364	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	20060862	649334	0	0
T1	10132	3929	0	0
T2	260932	0	0	0
T3	5744	2845	0	0
T4	270704	0	0	0
T5	0	252	0	0
T6	0	1702	0	0
T9	3620	418	0	0
T10	5678	1190	0	0
T13	0	112	0	0
T23	4334	0	0	0
T24	2470	0	0	0
T25	3306	0	0	0
T26	3476	0	0	0
T31	0	67	0	0
T33	0	24	0	0
T39	0	1916	0	0
T40	0	3053	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T77,T86
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T8,T36
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T32,T87,T88
1	0	1	Covered	T1,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9859083	271788	0	0
DepthKnown_A	10249775	10064284	0	0
RvalidKnown_A	10249775	10064284	0	0
WreadyKnown_A	10249775	10064284	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	10030431	318739	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9859083	271788	0	0
T1	5066	1938	0	0
T2	130466	0	0	0
T3	2872	1321	0	0
T4	135352	0	0	0
T6	0	37	0	0
T9	1810	210	0	0
T10	2839	551	0	0
T18	0	3807	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T31	0	29	0	0
T39	0	863	0	0
T40	0	1385	0	0
T84	0	331	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	10030431	318739	0	0
T1	5066	1938	0	0
T2	130466	0	0	0
T3	2872	1321	0	0
T4	135352	0	0	0
T5	0	131	0	0
T6	0	840	0	0
T9	1810	210	0	0
T10	2839	551	0	0
T13	0	112	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T31	0	29	0	0
T39	0	863	0	0
T40	0	1385	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T89,T90
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T37,T91
1	0	1	Covered	T1,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	9859083	283068	0	0
DepthKnown_A	10249775	10064284	0	0
RvalidKnown_A	10249775	10064284	0	0
WreadyKnown_A	10249775	10064284	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	10030431	330595	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9859083	283068	0	0
T1	5066	1991	0	0
T2	130466	0	0	0
T3	2872	1524	0	0
T4	135352	0	0	0
T6	0	52	0	0
T9	1810	208	0	0
T10	2839	639	0	0
T18	0	3836	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T31	0	38	0	0
T39	0	1053	0	0
T40	0	1668	0	0
T84	0	352	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10249775	10064284	0	0
T1	5066	4989	0	0
T2	130466	130341	0	0
T3	2872	2772	0	0
T4	135352	135257	0	0
T9	1810	1759	0	0
T10	2839	2758	0	0
T23	2167	2102	0	0
T24	1235	1153	0	0
T25	1653	1592	0	0
T26	1738	1682	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	10030431	330595	0	0
T1	5066	1991	0	0
T2	130466	0	0	0
T3	2872	1524	0	0
T4	135352	0	0	0
T5	0	121	0	0
T6	0	862	0	0
T9	1810	208	0	0
T10	2839	639	0	0
T23	2167	0	0	0
T24	1235	0	0	0
T25	1653	0	0	0
T26	1738	0	0	0
T31	0	38	0	0
T33	0	24	0	0
T39	0	1053	0	0
T40	0	1668	0	0