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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.72 98.25 93.97 97.02 91.28 96.37 99.77 93.37


Total test records in report: 1111
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T285 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1414310091 Aug 16 06:29:05 PM PDT 24 Aug 16 06:29:07 PM PDT 24 287875483 ps
T1013 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.305172417 Aug 16 06:28:32 PM PDT 24 Aug 16 06:28:33 PM PDT 24 33546902 ps
T1014 /workspace/coverage/cover_reg_top/9.edn_intr_test.2178007080 Aug 16 06:28:55 PM PDT 24 Aug 16 06:28:56 PM PDT 24 13595244 ps
T1015 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.641176483 Aug 16 06:28:56 PM PDT 24 Aug 16 06:28:57 PM PDT 24 35344222 ps
T251 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.933850582 Aug 16 06:28:41 PM PDT 24 Aug 16 06:28:42 PM PDT 24 13766982 ps
T1016 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1809384421 Aug 16 06:28:50 PM PDT 24 Aug 16 06:28:53 PM PDT 24 175058355 ps
T1017 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2753546426 Aug 16 06:29:23 PM PDT 24 Aug 16 06:29:25 PM PDT 24 75622137 ps
T1018 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.277248792 Aug 16 06:28:38 PM PDT 24 Aug 16 06:28:39 PM PDT 24 15356448 ps
T1019 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2089684225 Aug 16 06:28:46 PM PDT 24 Aug 16 06:28:47 PM PDT 24 53671297 ps
T1020 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2054639090 Aug 16 06:28:48 PM PDT 24 Aug 16 06:28:49 PM PDT 24 43492821 ps
T1021 /workspace/coverage/cover_reg_top/36.edn_intr_test.503958960 Aug 16 06:29:29 PM PDT 24 Aug 16 06:29:30 PM PDT 24 29921296 ps
T1022 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3975495112 Aug 16 06:29:14 PM PDT 24 Aug 16 06:29:15 PM PDT 24 67452740 ps
T1023 /workspace/coverage/cover_reg_top/4.edn_csr_rw.667245330 Aug 16 06:28:45 PM PDT 24 Aug 16 06:28:46 PM PDT 24 12000574 ps
T1024 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1334523222 Aug 16 06:28:52 PM PDT 24 Aug 16 06:28:54 PM PDT 24 24842101 ps
T252 /workspace/coverage/cover_reg_top/0.edn_csr_rw.66260510 Aug 16 06:28:39 PM PDT 24 Aug 16 06:28:40 PM PDT 24 13445980 ps
T1025 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.9026968 Aug 16 06:28:55 PM PDT 24 Aug 16 06:28:56 PM PDT 24 65797733 ps
T1026 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2457510302 Aug 16 06:29:12 PM PDT 24 Aug 16 06:29:15 PM PDT 24 282405672 ps
T1027 /workspace/coverage/cover_reg_top/43.edn_intr_test.26804626 Aug 16 06:29:33 PM PDT 24 Aug 16 06:29:34 PM PDT 24 31543970 ps
T253 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3603395667 Aug 16 06:28:52 PM PDT 24 Aug 16 06:28:53 PM PDT 24 13564022 ps
T281 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2087708661 Aug 16 06:28:45 PM PDT 24 Aug 16 06:28:47 PM PDT 24 188470282 ps
T1028 /workspace/coverage/cover_reg_top/48.edn_intr_test.537716159 Aug 16 06:29:27 PM PDT 24 Aug 16 06:29:28 PM PDT 24 14599542 ps
T1029 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3242310214 Aug 16 06:28:54 PM PDT 24 Aug 16 06:28:55 PM PDT 24 12517036 ps
T254 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.661041724 Aug 16 06:28:48 PM PDT 24 Aug 16 06:28:49 PM PDT 24 60999736 ps
T1030 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2212323026 Aug 16 06:29:12 PM PDT 24 Aug 16 06:29:14 PM PDT 24 350412587 ps
T255 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3723594740 Aug 16 06:28:40 PM PDT 24 Aug 16 06:28:43 PM PDT 24 38134727 ps
T1031 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3224402035 Aug 16 06:29:20 PM PDT 24 Aug 16 06:29:21 PM PDT 24 32504615 ps
T1032 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3676549664 Aug 16 06:28:33 PM PDT 24 Aug 16 06:28:36 PM PDT 24 191308226 ps
T1033 /workspace/coverage/cover_reg_top/20.edn_intr_test.3369936523 Aug 16 06:29:21 PM PDT 24 Aug 16 06:29:22 PM PDT 24 27285706 ps
T1034 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2210944108 Aug 16 06:29:22 PM PDT 24 Aug 16 06:29:24 PM PDT 24 189313461 ps
T1035 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3237967958 Aug 16 06:29:05 PM PDT 24 Aug 16 06:29:07 PM PDT 24 202823987 ps
T1036 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3016038221 Aug 16 06:29:13 PM PDT 24 Aug 16 06:29:14 PM PDT 24 33617958 ps
T1037 /workspace/coverage/cover_reg_top/26.edn_intr_test.904182768 Aug 16 06:29:37 PM PDT 24 Aug 16 06:29:38 PM PDT 24 15997281 ps
T1038 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2893235994 Aug 16 06:28:35 PM PDT 24 Aug 16 06:28:36 PM PDT 24 26840554 ps
T1039 /workspace/coverage/cover_reg_top/23.edn_intr_test.2792455747 Aug 16 06:29:19 PM PDT 24 Aug 16 06:29:20 PM PDT 24 21384773 ps
T1040 /workspace/coverage/cover_reg_top/34.edn_intr_test.1701754856 Aug 16 06:29:39 PM PDT 24 Aug 16 06:29:40 PM PDT 24 14232684 ps
T1041 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2861024694 Aug 16 06:28:48 PM PDT 24 Aug 16 06:28:49 PM PDT 24 71106856 ps
T1042 /workspace/coverage/cover_reg_top/22.edn_intr_test.1346546591 Aug 16 06:29:20 PM PDT 24 Aug 16 06:29:21 PM PDT 24 15297649 ps
T256 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1661879595 Aug 16 06:29:20 PM PDT 24 Aug 16 06:29:21 PM PDT 24 23322121 ps
T1043 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4026659909 Aug 16 06:28:54 PM PDT 24 Aug 16 06:28:57 PM PDT 24 339594665 ps
T1044 /workspace/coverage/cover_reg_top/4.edn_intr_test.2755896639 Aug 16 06:28:39 PM PDT 24 Aug 16 06:28:40 PM PDT 24 22312867 ps
T1045 /workspace/coverage/cover_reg_top/44.edn_intr_test.3442143372 Aug 16 06:29:29 PM PDT 24 Aug 16 06:29:30 PM PDT 24 12201373 ps
T1046 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1062364633 Aug 16 06:29:13 PM PDT 24 Aug 16 06:29:14 PM PDT 24 47170925 ps
T1047 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3449049680 Aug 16 06:29:11 PM PDT 24 Aug 16 06:29:14 PM PDT 24 90366863 ps
T1048 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1519615811 Aug 16 06:28:54 PM PDT 24 Aug 16 06:28:55 PM PDT 24 29364944 ps
T1049 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2913626794 Aug 16 06:28:55 PM PDT 24 Aug 16 06:28:58 PM PDT 24 134712287 ps
T1050 /workspace/coverage/cover_reg_top/5.edn_intr_test.1833711485 Aug 16 06:28:48 PM PDT 24 Aug 16 06:28:49 PM PDT 24 14852172 ps
T1051 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2375044776 Aug 16 06:28:30 PM PDT 24 Aug 16 06:28:37 PM PDT 24 586800660 ps
T1052 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4079234775 Aug 16 06:28:40 PM PDT 24 Aug 16 06:28:43 PM PDT 24 351294434 ps
T1053 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3904880784 Aug 16 06:28:54 PM PDT 24 Aug 16 06:28:55 PM PDT 24 85170513 ps
T1054 /workspace/coverage/cover_reg_top/49.edn_intr_test.1614031183 Aug 16 06:29:32 PM PDT 24 Aug 16 06:29:33 PM PDT 24 15732002 ps
T1055 /workspace/coverage/cover_reg_top/2.edn_intr_test.169867696 Aug 16 06:28:47 PM PDT 24 Aug 16 06:28:48 PM PDT 24 55624589 ps
T1056 /workspace/coverage/cover_reg_top/14.edn_intr_test.1293336990 Aug 16 06:29:13 PM PDT 24 Aug 16 06:29:14 PM PDT 24 47351362 ps
T1057 /workspace/coverage/cover_reg_top/8.edn_intr_test.343834815 Aug 16 06:28:55 PM PDT 24 Aug 16 06:28:56 PM PDT 24 25110628 ps
T1058 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1520196706 Aug 16 06:28:55 PM PDT 24 Aug 16 06:29:00 PM PDT 24 911068623 ps
T286 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3153781050 Aug 16 06:28:32 PM PDT 24 Aug 16 06:28:34 PM PDT 24 63577220 ps
T1059 /workspace/coverage/cover_reg_top/17.edn_tl_errors.950850206 Aug 16 06:29:21 PM PDT 24 Aug 16 06:29:23 PM PDT 24 128071358 ps
T1060 /workspace/coverage/cover_reg_top/15.edn_tl_errors.326219061 Aug 16 06:29:14 PM PDT 24 Aug 16 06:29:16 PM PDT 24 97387031 ps
T1061 /workspace/coverage/cover_reg_top/11.edn_intr_test.288929349 Aug 16 06:29:05 PM PDT 24 Aug 16 06:29:06 PM PDT 24 151346931 ps
T1062 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2316497541 Aug 16 06:28:39 PM PDT 24 Aug 16 06:28:40 PM PDT 24 35190023 ps
T1063 /workspace/coverage/cover_reg_top/19.edn_intr_test.1799019576 Aug 16 06:29:19 PM PDT 24 Aug 16 06:29:20 PM PDT 24 13192173 ps
T1064 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2303583671 Aug 16 06:28:54 PM PDT 24 Aug 16 06:28:57 PM PDT 24 252030965 ps
T1065 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.943890560 Aug 16 06:28:44 PM PDT 24 Aug 16 06:28:45 PM PDT 24 78559390 ps
T1066 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3412513149 Aug 16 06:28:54 PM PDT 24 Aug 16 06:28:58 PM PDT 24 195716408 ps
T1067 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1371706493 Aug 16 06:28:40 PM PDT 24 Aug 16 06:28:41 PM PDT 24 38519868 ps
T1068 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.90345890 Aug 16 06:28:47 PM PDT 24 Aug 16 06:28:49 PM PDT 24 176029267 ps
T1069 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4215779798 Aug 16 06:28:32 PM PDT 24 Aug 16 06:28:34 PM PDT 24 80271391 ps
T1070 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.958669472 Aug 16 06:29:20 PM PDT 24 Aug 16 06:29:22 PM PDT 24 37712461 ps
T1071 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3743476103 Aug 16 06:28:53 PM PDT 24 Aug 16 06:28:56 PM PDT 24 252366652 ps
T1072 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3086971666 Aug 16 06:28:39 PM PDT 24 Aug 16 06:28:42 PM PDT 24 35853348 ps
T1073 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3841327948 Aug 16 06:29:20 PM PDT 24 Aug 16 06:29:22 PM PDT 24 63334096 ps
T1074 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1336903314 Aug 16 06:29:05 PM PDT 24 Aug 16 06:29:07 PM PDT 24 111921598 ps
T1075 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1785906198 Aug 16 06:28:46 PM PDT 24 Aug 16 06:28:48 PM PDT 24 25988690 ps
T1076 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.921363442 Aug 16 06:28:41 PM PDT 24 Aug 16 06:28:43 PM PDT 24 57987024 ps
T1077 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3523236717 Aug 16 06:29:12 PM PDT 24 Aug 16 06:29:13 PM PDT 24 87379573 ps
T1078 /workspace/coverage/cover_reg_top/41.edn_intr_test.4284846846 Aug 16 06:29:27 PM PDT 24 Aug 16 06:29:28 PM PDT 24 64148254 ps
T1079 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.496507540 Aug 16 06:28:48 PM PDT 24 Aug 16 06:28:51 PM PDT 24 98643337 ps
T1080 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3587091757 Aug 16 06:29:21 PM PDT 24 Aug 16 06:29:22 PM PDT 24 66599678 ps
T1081 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.339055243 Aug 16 06:29:19 PM PDT 24 Aug 16 06:29:20 PM PDT 24 191140484 ps
T1082 /workspace/coverage/cover_reg_top/0.edn_tl_errors.865102019 Aug 16 06:28:31 PM PDT 24 Aug 16 06:28:33 PM PDT 24 90609747 ps
T1083 /workspace/coverage/cover_reg_top/7.edn_intr_test.1837245779 Aug 16 06:28:53 PM PDT 24 Aug 16 06:28:54 PM PDT 24 91349374 ps
T1084 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1686953066 Aug 16 06:28:54 PM PDT 24 Aug 16 06:28:55 PM PDT 24 19888286 ps
T1085 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.13065465 Aug 16 06:29:20 PM PDT 24 Aug 16 06:29:23 PM PDT 24 99849539 ps
T1086 /workspace/coverage/cover_reg_top/17.edn_intr_test.1464068101 Aug 16 06:29:22 PM PDT 24 Aug 16 06:29:23 PM PDT 24 19015273 ps
T1087 /workspace/coverage/cover_reg_top/29.edn_intr_test.2098423994 Aug 16 06:29:26 PM PDT 24 Aug 16 06:29:27 PM PDT 24 111770603 ps
T1088 /workspace/coverage/cover_reg_top/28.edn_intr_test.394133657 Aug 16 06:29:33 PM PDT 24 Aug 16 06:29:34 PM PDT 24 15598810 ps
T1089 /workspace/coverage/cover_reg_top/3.edn_intr_test.928536410 Aug 16 06:28:46 PM PDT 24 Aug 16 06:28:46 PM PDT 24 39341672 ps
T1090 /workspace/coverage/cover_reg_top/27.edn_intr_test.456630778 Aug 16 06:29:39 PM PDT 24 Aug 16 06:29:41 PM PDT 24 48016926 ps
T1091 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3836771441 Aug 16 06:29:04 PM PDT 24 Aug 16 06:29:06 PM PDT 24 32706099 ps
T1092 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1987744549 Aug 16 06:29:15 PM PDT 24 Aug 16 06:29:17 PM PDT 24 142143085 ps
T1093 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2936176616 Aug 16 06:28:38 PM PDT 24 Aug 16 06:28:39 PM PDT 24 26464455 ps
T282 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2269302453 Aug 16 06:29:14 PM PDT 24 Aug 16 06:29:16 PM PDT 24 106163887 ps
T1094 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1204595859 Aug 16 06:29:21 PM PDT 24 Aug 16 06:29:22 PM PDT 24 47191073 ps
T257 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.946963622 Aug 16 06:28:47 PM PDT 24 Aug 16 06:28:48 PM PDT 24 44962581 ps
T1095 /workspace/coverage/cover_reg_top/3.edn_tl_errors.291657580 Aug 16 06:28:47 PM PDT 24 Aug 16 06:28:51 PM PDT 24 192393309 ps
T1096 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1237912254 Aug 16 06:28:40 PM PDT 24 Aug 16 06:28:42 PM PDT 24 55347525 ps
T1097 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1117683219 Aug 16 06:28:42 PM PDT 24 Aug 16 06:28:46 PM PDT 24 271899076 ps
T1098 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2777185397 Aug 16 06:29:21 PM PDT 24 Aug 16 06:29:22 PM PDT 24 19290647 ps
T1099 /workspace/coverage/cover_reg_top/18.edn_csr_rw.112966318 Aug 16 06:29:22 PM PDT 24 Aug 16 06:29:23 PM PDT 24 22835499 ps
T1100 /workspace/coverage/cover_reg_top/47.edn_intr_test.4157985595 Aug 16 06:29:39 PM PDT 24 Aug 16 06:29:40 PM PDT 24 16436936 ps
T1101 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3388892057 Aug 16 06:29:13 PM PDT 24 Aug 16 06:29:15 PM PDT 24 19333835 ps
T283 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2491588788 Aug 16 06:29:11 PM PDT 24 Aug 16 06:29:14 PM PDT 24 92096307 ps
T1102 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4052158059 Aug 16 06:29:04 PM PDT 24 Aug 16 06:29:05 PM PDT 24 22102499 ps
T1103 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2658361246 Aug 16 06:29:12 PM PDT 24 Aug 16 06:29:13 PM PDT 24 13967196 ps
T1104 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2934513412 Aug 16 06:28:32 PM PDT 24 Aug 16 06:28:34 PM PDT 24 118419520 ps
T1105 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2871811869 Aug 16 06:29:21 PM PDT 24 Aug 16 06:29:23 PM PDT 24 117457695 ps
T1106 /workspace/coverage/cover_reg_top/33.edn_intr_test.3592195086 Aug 16 06:29:26 PM PDT 24 Aug 16 06:29:27 PM PDT 24 32710565 ps
T1107 /workspace/coverage/cover_reg_top/11.edn_csr_rw.849029552 Aug 16 06:29:04 PM PDT 24 Aug 16 06:29:05 PM PDT 24 11344404 ps
T1108 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1361278174 Aug 16 06:28:47 PM PDT 24 Aug 16 06:28:48 PM PDT 24 13171903 ps
T1109 /workspace/coverage/cover_reg_top/15.edn_intr_test.2187144764 Aug 16 06:29:13 PM PDT 24 Aug 16 06:29:14 PM PDT 24 13180523 ps
T1110 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.936955751 Aug 16 06:29:13 PM PDT 24 Aug 16 06:29:14 PM PDT 24 108051626 ps
T1111 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.858501623 Aug 16 06:29:11 PM PDT 24 Aug 16 06:29:13 PM PDT 24 36366163 ps

Test location /workspace/coverage/default/237.edn_genbits.445038685
Short name T2
Test name
Test status
Simulation time 86301941 ps
CPU time 1.28 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:08 PM PDT 24
Peak memory 217632 kb
Host smart-64d2ee77-8b4e-4983-8a41-40f8d7bae51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445038685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.445038685
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_sec_cm.4135674359
Short name T5
Test name
Test status
Simulation time 3064861081 ps
CPU time 7.29 seconds
Started Aug 16 06:21:04 PM PDT 24
Finished Aug 16 06:21:12 PM PDT 24
Peak memory 238228 kb
Host smart-9f7e8217-924f-4bbe-b7ee-f7a2bfdfecaa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135674359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.4135674359
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/108.edn_alert.1802414713
Short name T9
Test name
Test status
Simulation time 180741949 ps
CPU time 1.17 seconds
Started Aug 16 06:22:42 PM PDT 24
Finished Aug 16 06:22:43 PM PDT 24
Peak memory 218676 kb
Host smart-23f710bb-c09d-4bb1-a231-ef9242ab1150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802414713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.1802414713
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.634835359
Short name T27
Test name
Test status
Simulation time 28173869367 ps
CPU time 87.88 seconds
Started Aug 16 06:21:10 PM PDT 24
Finished Aug 16 06:22:38 PM PDT 24
Peak memory 218928 kb
Host smart-e90e4fe5-80bc-4434-b097-6330af1c5843
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634835359 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.634835359
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.edn_genbits.4092881981
Short name T17
Test name
Test status
Simulation time 58013437 ps
CPU time 1.38 seconds
Started Aug 16 06:22:52 PM PDT 24
Finished Aug 16 06:22:54 PM PDT 24
Peak memory 220328 kb
Host smart-04803f56-d091-45d0-9c58-b8b7af48b6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092881981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.4092881981
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.534129404
Short name T7
Test name
Test status
Simulation time 88646301 ps
CPU time 0.99 seconds
Started Aug 16 06:22:24 PM PDT 24
Finished Aug 16 06:22:25 PM PDT 24
Peak memory 215504 kb
Host smart-d06541b9-1881-49b4-86bd-4bee926e496b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534129404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.534129404
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/5.edn_disable.2552569279
Short name T171
Test name
Test status
Simulation time 33336620 ps
CPU time 0.83 seconds
Started Aug 16 06:21:08 PM PDT 24
Finished Aug 16 06:21:09 PM PDT 24
Peak memory 215444 kb
Host smart-612e073a-a6e2-4c61-a84b-68fab0b8692c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552569279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2552569279
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/146.edn_alert.4160164957
Short name T97
Test name
Test status
Simulation time 242187734 ps
CPU time 1.42 seconds
Started Aug 16 06:22:52 PM PDT 24
Finished Aug 16 06:22:54 PM PDT 24
Peak memory 220264 kb
Host smart-48beb008-355b-4736-b1e7-ebf46276e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160164957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.4160164957
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/51.edn_alert.864196974
Short name T95
Test name
Test status
Simulation time 25938616 ps
CPU time 1.26 seconds
Started Aug 16 06:22:13 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 218696 kb
Host smart-2e60be6c-2efb-4310-b830-72b60f025be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864196974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.864196974
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/40.edn_disable.287750667
Short name T32
Test name
Test status
Simulation time 35494422 ps
CPU time 0.89 seconds
Started Aug 16 06:21:55 PM PDT 24
Finished Aug 16 06:21:56 PM PDT 24
Peak memory 215420 kb
Host smart-87f35e13-83ce-4f77-b0e2-156a67a7fa1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287750667 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.287750667
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.181852318
Short name T112
Test name
Test status
Simulation time 271155894 ps
CPU time 1.16 seconds
Started Aug 16 06:21:07 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 216836 kb
Host smart-06a5880a-e0a8-463b-a2f7-6154b60cc616
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181852318 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.181852318
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/106.edn_alert.3433718832
Short name T163
Test name
Test status
Simulation time 58181207 ps
CPU time 1 seconds
Started Aug 16 06:22:30 PM PDT 24
Finished Aug 16 06:22:31 PM PDT 24
Peak memory 219560 kb
Host smart-95018fbc-0f4a-454f-9525-e48d6debcc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433718832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.3433718832
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1947521396
Short name T29
Test name
Test status
Simulation time 11789180319 ps
CPU time 84.48 seconds
Started Aug 16 06:21:57 PM PDT 24
Finished Aug 16 06:23:22 PM PDT 24
Peak memory 219144 kb
Host smart-849e0bda-2e0c-4cee-9c0a-2f658125011a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947521396 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1947521396
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1859142273
Short name T284
Test name
Test status
Simulation time 112595921 ps
CPU time 1.77 seconds
Started Aug 16 06:29:03 PM PDT 24
Finished Aug 16 06:29:05 PM PDT 24
Peak memory 215260 kb
Host smart-04d5b59b-7144-4671-95dc-e2821e6b3629
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859142273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1859142273
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/3.edn_alert.1805406144
Short name T36
Test name
Test status
Simulation time 66525907 ps
CPU time 1.14 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:07 PM PDT 24
Peak memory 215724 kb
Host smart-b15bda84-01fc-4e77-b42b-7beade22b907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805406144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1805406144
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/24.edn_stress_all.482939617
Short name T21
Test name
Test status
Simulation time 160348640 ps
CPU time 1.83 seconds
Started Aug 16 06:21:34 PM PDT 24
Finished Aug 16 06:21:36 PM PDT 24
Peak memory 215436 kb
Host smart-3e0f0426-3e2c-47e8-953d-b91dacf58be4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482939617 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.482939617
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_disable.2696552332
Short name T182
Test name
Test status
Simulation time 49206018 ps
CPU time 0.88 seconds
Started Aug 16 06:21:41 PM PDT 24
Finished Aug 16 06:21:42 PM PDT 24
Peak memory 215420 kb
Host smart-abd3648f-72c7-4e82-ba58-b8edc5ee4362
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696552332 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2696552332
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2223679889
Short name T139
Test name
Test status
Simulation time 71197640 ps
CPU time 1.32 seconds
Started Aug 16 06:21:25 PM PDT 24
Finished Aug 16 06:21:27 PM PDT 24
Peak memory 216892 kb
Host smart-f6cfa8c9-abc7-42ad-8216-d03f9e5961b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223679889 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2223679889
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/72.edn_err.3023230605
Short name T176
Test name
Test status
Simulation time 32739462 ps
CPU time 0.94 seconds
Started Aug 16 06:22:37 PM PDT 24
Finished Aug 16 06:22:38 PM PDT 24
Peak memory 218592 kb
Host smart-71755125-3e04-4dd6-b882-d6048deb9b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023230605 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3023230605
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/114.edn_alert.3637944362
Short name T148
Test name
Test status
Simulation time 31029354 ps
CPU time 1.35 seconds
Started Aug 16 06:22:36 PM PDT 24
Finished Aug 16 06:22:37 PM PDT 24
Peak memory 219152 kb
Host smart-ddf40438-daea-48ab-af74-881e88037c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637944362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.3637944362
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.66260510
Short name T252
Test name
Test status
Simulation time 13445980 ps
CPU time 0.91 seconds
Started Aug 16 06:28:39 PM PDT 24
Finished Aug 16 06:28:40 PM PDT 24
Peak memory 206980 kb
Host smart-a4ade1c4-ba87-40be-9836-f9fa5b2f82cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66260510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.66260510
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/default/246.edn_genbits.2877135765
Short name T43
Test name
Test status
Simulation time 65235216 ps
CPU time 1.26 seconds
Started Aug 16 06:23:16 PM PDT 24
Finished Aug 16 06:23:17 PM PDT 24
Peak memory 219296 kb
Host smart-26f1f8ad-264b-4005-b98f-439efa3a7a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877135765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2877135765
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3188875515
Short name T125
Test name
Test status
Simulation time 88696163 ps
CPU time 1.21 seconds
Started Aug 16 06:21:29 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 218696 kb
Host smart-faf84662-7364-4b9e-88cb-da791a311ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188875515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3188875515
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/184.edn_alert.3484421529
Short name T100
Test name
Test status
Simulation time 41074353 ps
CPU time 1.12 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 219952 kb
Host smart-f921269a-deed-4c06-a1fe-aaa48dd7df77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484421529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.3484421529
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/82.edn_genbits.1522637222
Short name T10
Test name
Test status
Simulation time 107127412 ps
CPU time 1.57 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 220568 kb
Host smart-61fb5aba-7599-4487-b7a6-7f1226d3e59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522637222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1522637222
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_alert.1969384731
Short name T104
Test name
Test status
Simulation time 25545975 ps
CPU time 1.25 seconds
Started Aug 16 06:22:30 PM PDT 24
Finished Aug 16 06:22:32 PM PDT 24
Peak memory 219584 kb
Host smart-1baa8815-1fa9-46c7-ba69-4b16de9e6cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969384731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.1969384731
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/60.edn_alert.2368358339
Short name T156
Test name
Test status
Simulation time 31765003 ps
CPU time 1.39 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 220020 kb
Host smart-8e8833c5-ecce-40b4-845c-319fc3f97247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368358339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.2368358339
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/9.edn_intr.3962806136
Short name T85
Test name
Test status
Simulation time 47922983 ps
CPU time 0.95 seconds
Started Aug 16 06:21:18 PM PDT 24
Finished Aug 16 06:21:20 PM PDT 24
Peak memory 215668 kb
Host smart-6b31b21e-8258-45fe-b341-6130a640c0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962806136 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3962806136
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/198.edn_genbits.2807244077
Short name T38
Test name
Test status
Simulation time 707908164 ps
CPU time 4.05 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 218748 kb
Host smart-1f88efb5-1a93-4926-8d97-9a202b8aca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807244077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2807244077
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2556122279
Short name T334
Test name
Test status
Simulation time 509671151 ps
CPU time 3.87 seconds
Started Aug 16 06:23:11 PM PDT 24
Finished Aug 16 06:23:15 PM PDT 24
Peak memory 219772 kb
Host smart-f7503742-85cf-4095-8cf9-431341942da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556122279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2556122279
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.1363085169
Short name T178
Test name
Test status
Simulation time 51969733 ps
CPU time 1.25 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 218932 kb
Host smart-cfecfb3d-fc24-49d5-a909-7e2d01953ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363085169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.1363085169
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert.1823155063
Short name T8
Test name
Test status
Simulation time 30875578 ps
CPU time 1.33 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 219880 kb
Host smart-efebac1b-8e8e-4bc4-ba6a-93f8571efe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823155063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1823155063
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/7.edn_disable.1757207789
Short name T153
Test name
Test status
Simulation time 10483489 ps
CPU time 0.87 seconds
Started Aug 16 06:21:07 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 215404 kb
Host smart-9dc6e111-359f-42d3-9299-fcefb6cbd2fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757207789 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1757207789
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1132233650
Short name T731
Test name
Test status
Simulation time 22008843 ps
CPU time 1.03 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:21:00 PM PDT 24
Peak memory 216932 kb
Host smart-d3ba3b90-003c-492c-add3-3c8c7ec6e643
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132233650 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1132233650
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2247789988
Short name T147
Test name
Test status
Simulation time 334388090 ps
CPU time 1.4 seconds
Started Aug 16 06:20:59 PM PDT 24
Finished Aug 16 06:21:01 PM PDT 24
Peak memory 216952 kb
Host smart-538751ce-fd69-4d8f-a67b-191ca3a68c75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247789988 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2247789988
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/101.edn_alert.2206950867
Short name T519
Test name
Test status
Simulation time 40748585 ps
CPU time 1.12 seconds
Started Aug 16 06:22:44 PM PDT 24
Finished Aug 16 06:22:46 PM PDT 24
Peak memory 219820 kb
Host smart-1ce2cdd2-967d-481a-a92f-1474118e5f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206950867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.2206950867
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.3116017992
Short name T773
Test name
Test status
Simulation time 49711719 ps
CPU time 1.26 seconds
Started Aug 16 06:22:28 PM PDT 24
Finished Aug 16 06:22:29 PM PDT 24
Peak memory 215756 kb
Host smart-a6a00abb-4a18-4044-a375-b2e84ffaea8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116017992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.3116017992
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.290099419
Short name T133
Test name
Test status
Simulation time 29461445 ps
CPU time 1.28 seconds
Started Aug 16 06:23:00 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 215772 kb
Host smart-71a809a2-11cb-45d3-91ed-39f2c5b317dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290099419 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.290099419
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3162746489
Short name T117
Test name
Test status
Simulation time 157965448 ps
CPU time 1.21 seconds
Started Aug 16 06:21:14 PM PDT 24
Finished Aug 16 06:21:15 PM PDT 24
Peak memory 216896 kb
Host smart-0a709e99-a79a-4d96-a069-a99b2fd42a0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162746489 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3162746489
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_disable.2189112689
Short name T183
Test name
Test status
Simulation time 11435844 ps
CPU time 0.89 seconds
Started Aug 16 06:21:20 PM PDT 24
Finished Aug 16 06:21:21 PM PDT 24
Peak memory 215596 kb
Host smart-0cd9aa69-de9d-4c96-8c2b-afdb413143a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189112689 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2189112689
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.1155872307
Short name T395
Test name
Test status
Simulation time 85477115 ps
CPU time 1.1 seconds
Started Aug 16 06:21:18 PM PDT 24
Finished Aug 16 06:21:19 PM PDT 24
Peak memory 219760 kb
Host smart-59d5ff98-ed01-4e87-b1e2-81b1302f4638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155872307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1155872307
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/17.edn_disable.281612982
Short name T198
Test name
Test status
Simulation time 20432956 ps
CPU time 0.81 seconds
Started Aug 16 06:21:29 PM PDT 24
Finished Aug 16 06:21:30 PM PDT 24
Peak memory 214132 kb
Host smart-3c9dc140-2bb4-471f-9536-4c249c5a45af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281612982 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.281612982
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/183.edn_alert.906245778
Short name T167
Test name
Test status
Simulation time 218293351 ps
CPU time 1.45 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 220684 kb
Host smart-61af6219-56b1-4e7f-9a52-d61a9296c57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906245778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.906245778
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2479550017
Short name T201
Test name
Test status
Simulation time 48412179 ps
CPU time 1.02 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:34 PM PDT 24
Peak memory 217328 kb
Host smart-5f14c0b8-dadb-4485-a5d1-35ba1abacb2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479550017 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2479550017
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1790041763
Short name T187
Test name
Test status
Simulation time 27989289 ps
CPU time 0.99 seconds
Started Aug 16 06:21:40 PM PDT 24
Finished Aug 16 06:21:41 PM PDT 24
Peak memory 223896 kb
Host smart-f46f024f-435f-44aa-b258-a7dbe3d74896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790041763 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1790041763
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/30.edn_disable.1038482720
Short name T164
Test name
Test status
Simulation time 12020021 ps
CPU time 0.89 seconds
Started Aug 16 06:21:41 PM PDT 24
Finished Aug 16 06:21:42 PM PDT 24
Peak memory 215428 kb
Host smart-63a3ce34-28c2-4ef0-ac0a-de316fa164df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038482720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1038482720
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.3066435993
Short name T190
Test name
Test status
Simulation time 20572679 ps
CPU time 1.1 seconds
Started Aug 16 06:21:46 PM PDT 24
Finished Aug 16 06:21:47 PM PDT 24
Peak memory 219496 kb
Host smart-866605d5-fe0d-48cd-8a02-d3f80d72f4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066435993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3066435993
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/11.edn_alert_test.3014487464
Short name T60
Test name
Test status
Simulation time 39907813 ps
CPU time 0.98 seconds
Started Aug 16 06:21:14 PM PDT 24
Finished Aug 16 06:21:15 PM PDT 24
Peak memory 206752 kb
Host smart-f4690e80-8896-493c-9286-3a5e834a3d72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014487464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3014487464
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_alert.3745310708
Short name T287
Test name
Test status
Simulation time 125261113 ps
CPU time 1.17 seconds
Started Aug 16 06:21:27 PM PDT 24
Finished Aug 16 06:21:28 PM PDT 24
Peak memory 219600 kb
Host smart-80b0112b-ec70-4e5f-ae12-386e8c3ab1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745310708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3745310708
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/97.edn_genbits.3260623097
Short name T299
Test name
Test status
Simulation time 46404579 ps
CPU time 1.18 seconds
Started Aug 16 06:22:41 PM PDT 24
Finished Aug 16 06:22:42 PM PDT 24
Peak memory 217552 kb
Host smart-9b51efae-cbb7-417d-8d45-0659a9fe0443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260623097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3260623097
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3516521111
Short name T226
Test name
Test status
Simulation time 4433904824 ps
CPU time 104.63 seconds
Started Aug 16 06:21:13 PM PDT 24
Finished Aug 16 06:22:58 PM PDT 24
Peak memory 219068 kb
Host smart-8170f78c-2e45-4eae-80ec-8ed5fc754ca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516521111 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3516521111
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.255422547
Short name T671
Test name
Test status
Simulation time 20756511582 ps
CPU time 38.16 seconds
Started Aug 16 06:20:59 PM PDT 24
Finished Aug 16 06:21:37 PM PDT 24
Peak memory 219260 kb
Host smart-995e7fbc-96b0-44dc-a070-ed616fc2d03e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255422547 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.255422547
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.edn_intr.433271463
Short name T82
Test name
Test status
Simulation time 33537086 ps
CPU time 0.93 seconds
Started Aug 16 06:21:23 PM PDT 24
Finished Aug 16 06:21:24 PM PDT 24
Peak memory 215816 kb
Host smart-0959758e-78da-4840-add6-e4a442cc6ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433271463 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.433271463
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/37.edn_err.2507981517
Short name T47
Test name
Test status
Simulation time 90165270 ps
CPU time 1.03 seconds
Started Aug 16 06:21:44 PM PDT 24
Finished Aug 16 06:21:45 PM PDT 24
Peak memory 229612 kb
Host smart-ddd50e35-37cf-462e-ba20-d703439402d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507981517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2507981517
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.2082364609
Short name T636
Test name
Test status
Simulation time 21000181 ps
CPU time 1.06 seconds
Started Aug 16 06:21:02 PM PDT 24
Finished Aug 16 06:21:03 PM PDT 24
Peak memory 215856 kb
Host smart-df2ffb1c-aa4a-4009-bc8e-e9ba05d56b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082364609 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2082364609
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1140478215
Short name T261
Test name
Test status
Simulation time 27208989 ps
CPU time 1.05 seconds
Started Aug 16 06:28:42 PM PDT 24
Finished Aug 16 06:28:44 PM PDT 24
Peak memory 207120 kb
Host smart-c59d27fb-8282-4e84-b93e-7bf2fe40368b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140478215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1140478215
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2269302453
Short name T282
Test name
Test status
Simulation time 106163887 ps
CPU time 1.65 seconds
Started Aug 16 06:29:14 PM PDT 24
Finished Aug 16 06:29:16 PM PDT 24
Peak memory 207472 kb
Host smart-4bdc18a9-9b45-4998-a885-1b0dc60a1b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269302453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2269302453
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2497689709
Short name T343
Test name
Test status
Simulation time 112256389 ps
CPU time 1.68 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:21:00 PM PDT 24
Peak memory 218996 kb
Host smart-6fce989e-8b97-4572-9945-becf82a99545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497689709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2497689709
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_genbits.1900602999
Short name T68
Test name
Test status
Simulation time 41698899 ps
CPU time 1.08 seconds
Started Aug 16 06:21:14 PM PDT 24
Finished Aug 16 06:21:16 PM PDT 24
Peak memory 217396 kb
Host smart-f8da1904-4b3d-4ba8-8880-0bbe611673c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900602999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1900602999
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.4053470755
Short name T308
Test name
Test status
Simulation time 33020981 ps
CPU time 1.12 seconds
Started Aug 16 06:22:51 PM PDT 24
Finished Aug 16 06:22:53 PM PDT 24
Peak memory 220324 kb
Host smart-39d6f567-3754-4602-bbbf-c9e9cb6dea10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053470755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.4053470755
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2401284430
Short name T298
Test name
Test status
Simulation time 27262194 ps
CPU time 1 seconds
Started Aug 16 06:22:54 PM PDT 24
Finished Aug 16 06:22:55 PM PDT 24
Peak memory 217232 kb
Host smart-9c607777-3705-4273-a055-f387c8bc2d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401284430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2401284430
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2999130299
Short name T275
Test name
Test status
Simulation time 116294391 ps
CPU time 1.16 seconds
Started Aug 16 06:21:29 PM PDT 24
Finished Aug 16 06:21:30 PM PDT 24
Peak memory 216964 kb
Host smart-89d9e65d-6b44-4c92-8743-9c798ee147dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999130299 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2999130299
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.560214814
Short name T28
Test name
Test status
Simulation time 1689218380 ps
CPU time 41.72 seconds
Started Aug 16 06:21:29 PM PDT 24
Finished Aug 16 06:22:11 PM PDT 24
Peak memory 218308 kb
Host smart-63c41992-0b2d-44fa-ac93-f32180ad2438
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560214814 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.560214814
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.edn_genbits.2526465713
Short name T883
Test name
Test status
Simulation time 33219773 ps
CPU time 1.43 seconds
Started Aug 16 06:22:49 PM PDT 24
Finished Aug 16 06:22:51 PM PDT 24
Peak memory 217412 kb
Host smart-6b8e22fe-6aec-45e4-a452-518c9e08d570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526465713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2526465713
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3039972946
Short name T942
Test name
Test status
Simulation time 59987023 ps
CPU time 1.41 seconds
Started Aug 16 06:22:52 PM PDT 24
Finished Aug 16 06:22:54 PM PDT 24
Peak memory 218620 kb
Host smart-7db26a1a-248f-416e-9b54-28b281a3d0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039972946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3039972946
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_genbits.2071864727
Short name T919
Test name
Test status
Simulation time 140255278 ps
CPU time 2.16 seconds
Started Aug 16 06:21:29 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 218840 kb
Host smart-9983becd-a997-4421-b1a6-02daf6f5d876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071864727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2071864727
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1740606063
Short name T302
Test name
Test status
Simulation time 71681856 ps
CPU time 1.36 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 218364 kb
Host smart-faaa211f-c250-4f84-8249-80ce03b320bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740606063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1740606063
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1835077924
Short name T304
Test name
Test status
Simulation time 28988579 ps
CPU time 1.28 seconds
Started Aug 16 06:23:11 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 219556 kb
Host smart-ed04631c-f3b3-4f63-98df-7090c4c7a3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835077924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1835077924
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_genbits.701598429
Short name T322
Test name
Test status
Simulation time 31584995 ps
CPU time 1.53 seconds
Started Aug 16 06:22:16 PM PDT 24
Finished Aug 16 06:22:18 PM PDT 24
Peak memory 218776 kb
Host smart-de0df1f2-ae2a-4cab-88ff-0e23f92aa0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701598429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.701598429
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.884802036
Short name T83
Test name
Test status
Simulation time 71317008 ps
CPU time 0.9 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:07 PM PDT 24
Peak memory 215612 kb
Host smart-cc9f21a3-9e29-430b-b5ed-094f7d5a6b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884802036 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.884802036
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/14.edn_alert.3157597319
Short name T108
Test name
Test status
Simulation time 28203140 ps
CPU time 1.25 seconds
Started Aug 16 06:21:26 PM PDT 24
Finished Aug 16 06:21:27 PM PDT 24
Peak memory 218796 kb
Host smart-e32752aa-ceaa-4d3c-9115-d65721f75e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157597319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3157597319
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/81.edn_genbits.4276548363
Short name T329
Test name
Test status
Simulation time 126894232 ps
CPU time 1.38 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 219608 kb
Host smart-a70a330b-db89-4865-bcfa-bf0e48dbc4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276548363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4276548363
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4215779798
Short name T1069
Test name
Test status
Simulation time 80271391 ps
CPU time 1.58 seconds
Started Aug 16 06:28:32 PM PDT 24
Finished Aug 16 06:28:34 PM PDT 24
Peak memory 206924 kb
Host smart-4c1834fb-e582-4610-b0a1-9be8b8c50cd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215779798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4215779798
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3676549664
Short name T1032
Test name
Test status
Simulation time 191308226 ps
CPU time 3.16 seconds
Started Aug 16 06:28:33 PM PDT 24
Finished Aug 16 06:28:36 PM PDT 24
Peak memory 207028 kb
Host smart-b0683ccb-976d-4dda-88e6-ae13f864ebfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676549664 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3676549664
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.305172417
Short name T1013
Test name
Test status
Simulation time 33546902 ps
CPU time 0.94 seconds
Started Aug 16 06:28:32 PM PDT 24
Finished Aug 16 06:28:33 PM PDT 24
Peak memory 206980 kb
Host smart-f5a3c5a7-d2ea-4670-9373-8bb00a8b63c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305172417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.305172417
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2934513412
Short name T1104
Test name
Test status
Simulation time 118419520 ps
CPU time 1.5 seconds
Started Aug 16 06:28:32 PM PDT 24
Finished Aug 16 06:28:34 PM PDT 24
Peak memory 215288 kb
Host smart-e18838b1-f46d-4ec0-8e1d-bdf26f2dc7ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934513412 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2934513412
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1778307502
Short name T998
Test name
Test status
Simulation time 22783823 ps
CPU time 0.8 seconds
Started Aug 16 06:28:37 PM PDT 24
Finished Aug 16 06:28:38 PM PDT 24
Peak memory 206916 kb
Host smart-36e2ef4e-cb94-4576-88fa-277b0d9ffebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778307502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1778307502
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.865102019
Short name T1082
Test name
Test status
Simulation time 90609747 ps
CPU time 1.88 seconds
Started Aug 16 06:28:31 PM PDT 24
Finished Aug 16 06:28:33 PM PDT 24
Peak memory 215436 kb
Host smart-f88299ac-db25-4518-87d8-5420fde7422a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865102019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.865102019
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3787783954
Short name T271
Test name
Test status
Simulation time 45368097 ps
CPU time 1.62 seconds
Started Aug 16 06:28:39 PM PDT 24
Finished Aug 16 06:28:41 PM PDT 24
Peak memory 207044 kb
Host smart-a7c214fd-5001-4f5d-a5b6-babe1c605a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787783954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3787783954
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.277248792
Short name T1018
Test name
Test status
Simulation time 15356448 ps
CPU time 1.07 seconds
Started Aug 16 06:28:38 PM PDT 24
Finished Aug 16 06:28:39 PM PDT 24
Peak memory 207040 kb
Host smart-3b53fdc1-a5c3-4266-80ea-be12d24728d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277248792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.277248792
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2375044776
Short name T1051
Test name
Test status
Simulation time 586800660 ps
CPU time 6.64 seconds
Started Aug 16 06:28:30 PM PDT 24
Finished Aug 16 06:28:37 PM PDT 24
Peak memory 206988 kb
Host smart-52cb9823-bbc6-4cbb-9add-4a90729f8256
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375044776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2375044776
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2936176616
Short name T1093
Test name
Test status
Simulation time 26464455 ps
CPU time 0.85 seconds
Started Aug 16 06:28:38 PM PDT 24
Finished Aug 16 06:28:39 PM PDT 24
Peak memory 206940 kb
Host smart-555f5c07-8785-4cc3-84a7-b0c170b55c11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936176616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2936176616
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3801831050
Short name T985
Test name
Test status
Simulation time 54975376 ps
CPU time 1.39 seconds
Started Aug 16 06:28:38 PM PDT 24
Finished Aug 16 06:28:40 PM PDT 24
Peak memory 215360 kb
Host smart-5b3eab89-fd7c-4e1b-b814-7c4ece6ce7eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801831050 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3801831050
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2893235994
Short name T1038
Test name
Test status
Simulation time 26840554 ps
CPU time 0.94 seconds
Started Aug 16 06:28:35 PM PDT 24
Finished Aug 16 06:28:36 PM PDT 24
Peak memory 206928 kb
Host smart-5a157ba3-60c9-4d4a-ac57-a637829e2339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893235994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2893235994
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3280766842
Short name T989
Test name
Test status
Simulation time 25019862 ps
CPU time 0.9 seconds
Started Aug 16 06:28:35 PM PDT 24
Finished Aug 16 06:28:36 PM PDT 24
Peak memory 206852 kb
Host smart-8fd540aa-b439-440d-aa07-cf3816fe146f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280766842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3280766842
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.796649005
Short name T264
Test name
Test status
Simulation time 243330068 ps
CPU time 0.98 seconds
Started Aug 16 06:28:38 PM PDT 24
Finished Aug 16 06:28:39 PM PDT 24
Peak memory 207136 kb
Host smart-8636c0a3-3eed-411c-ad8b-1b7e0e8f2951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796649005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.796649005
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3980787464
Short name T983
Test name
Test status
Simulation time 112854209 ps
CPU time 3.66 seconds
Started Aug 16 06:28:41 PM PDT 24
Finished Aug 16 06:28:44 PM PDT 24
Peak memory 215260 kb
Host smart-9b94bb15-b492-4333-8ef3-943d5ea24bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980787464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3980787464
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3153781050
Short name T286
Test name
Test status
Simulation time 63577220 ps
CPU time 1.82 seconds
Started Aug 16 06:28:32 PM PDT 24
Finished Aug 16 06:28:34 PM PDT 24
Peak memory 207124 kb
Host smart-bf3d8dd4-c4dd-4f20-9ea8-383d99a5aed3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153781050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3153781050
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3131385793
Short name T981
Test name
Test status
Simulation time 87671816 ps
CPU time 1.23 seconds
Started Aug 16 06:29:05 PM PDT 24
Finished Aug 16 06:29:06 PM PDT 24
Peak memory 215388 kb
Host smart-c9abee02-168b-47bd-8ab0-6828d564dc58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131385793 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3131385793
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3821236858
Short name T250
Test name
Test status
Simulation time 107271708 ps
CPU time 0.81 seconds
Started Aug 16 06:29:05 PM PDT 24
Finished Aug 16 06:29:06 PM PDT 24
Peak memory 206744 kb
Host smart-b1287491-9558-4eca-bc2d-ee8f54f6228c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821236858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3821236858
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.640101314
Short name T999
Test name
Test status
Simulation time 79365147 ps
CPU time 0.78 seconds
Started Aug 16 06:29:07 PM PDT 24
Finished Aug 16 06:29:08 PM PDT 24
Peak memory 206752 kb
Host smart-9e02c6ae-7f01-416c-a799-2a23ac809aac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640101314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.640101314
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.186858396
Short name T263
Test name
Test status
Simulation time 392281969 ps
CPU time 1.46 seconds
Started Aug 16 06:29:05 PM PDT 24
Finished Aug 16 06:29:07 PM PDT 24
Peak memory 207124 kb
Host smart-e2e03926-70f7-42ce-8a9c-5c194df79040
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186858396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.186858396
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3412513149
Short name T1066
Test name
Test status
Simulation time 195716408 ps
CPU time 3.8 seconds
Started Aug 16 06:28:54 PM PDT 24
Finished Aug 16 06:28:58 PM PDT 24
Peak memory 215308 kb
Host smart-e85263e9-0ce5-4ca6-ae01-6bdda040b829
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412513149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3412513149
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3836771441
Short name T1091
Test name
Test status
Simulation time 32706099 ps
CPU time 1.54 seconds
Started Aug 16 06:29:04 PM PDT 24
Finished Aug 16 06:29:06 PM PDT 24
Peak memory 215364 kb
Host smart-18661b0b-9a12-4c34-a136-c6c7499c08b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836771441 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3836771441
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.849029552
Short name T1107
Test name
Test status
Simulation time 11344404 ps
CPU time 0.94 seconds
Started Aug 16 06:29:04 PM PDT 24
Finished Aug 16 06:29:05 PM PDT 24
Peak memory 206980 kb
Host smart-b31f3f14-a89f-47ab-a49d-8103abec716e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849029552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.849029552
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.288929349
Short name T1061
Test name
Test status
Simulation time 151346931 ps
CPU time 0.86 seconds
Started Aug 16 06:29:05 PM PDT 24
Finished Aug 16 06:29:06 PM PDT 24
Peak memory 206824 kb
Host smart-280d2ecd-83ac-44cb-b49a-f5e13bf949b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288929349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.288929349
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4052158059
Short name T1102
Test name
Test status
Simulation time 22102499 ps
CPU time 1.12 seconds
Started Aug 16 06:29:04 PM PDT 24
Finished Aug 16 06:29:05 PM PDT 24
Peak memory 207052 kb
Host smart-8319bdbd-3c46-47e4-8560-a3b9832e3ead
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052158059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.4052158059
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3237967958
Short name T1035
Test name
Test status
Simulation time 202823987 ps
CPU time 2.14 seconds
Started Aug 16 06:29:05 PM PDT 24
Finished Aug 16 06:29:07 PM PDT 24
Peak memory 223420 kb
Host smart-4f0d4a43-69cc-485e-8cd1-0126acb3716b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237967958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3237967958
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1414310091
Short name T285
Test name
Test status
Simulation time 287875483 ps
CPU time 2.48 seconds
Started Aug 16 06:29:05 PM PDT 24
Finished Aug 16 06:29:07 PM PDT 24
Peak memory 215264 kb
Host smart-79582eae-5247-4a46-865f-d816fcf05b3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414310091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1414310091
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3975495112
Short name T1022
Test name
Test status
Simulation time 67452740 ps
CPU time 1.01 seconds
Started Aug 16 06:29:14 PM PDT 24
Finished Aug 16 06:29:15 PM PDT 24
Peak memory 207096 kb
Host smart-d70d2d14-706d-471f-94f0-72dc1bfc71f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975495112 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3975495112
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2417701870
Short name T1011
Test name
Test status
Simulation time 22823528 ps
CPU time 0.89 seconds
Started Aug 16 06:29:12 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 206844 kb
Host smart-8c8667d0-b36d-41d9-8978-800bfc361569
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417701870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2417701870
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1717723619
Short name T1000
Test name
Test status
Simulation time 24089859 ps
CPU time 0.91 seconds
Started Aug 16 06:29:11 PM PDT 24
Finished Aug 16 06:29:12 PM PDT 24
Peak memory 206860 kb
Host smart-b8715394-d45b-4e1b-b927-927243d719fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717723619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1717723619
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3523236717
Short name T1077
Test name
Test status
Simulation time 87379573 ps
CPU time 1.14 seconds
Started Aug 16 06:29:12 PM PDT 24
Finished Aug 16 06:29:13 PM PDT 24
Peak memory 207028 kb
Host smart-44a9b6bf-5fc3-4fb4-8ed1-a2e393b1ee55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523236717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3523236717
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1336903314
Short name T1074
Test name
Test status
Simulation time 111921598 ps
CPU time 2.16 seconds
Started Aug 16 06:29:05 PM PDT 24
Finished Aug 16 06:29:07 PM PDT 24
Peak memory 215288 kb
Host smart-894a52b7-4230-429b-ab3c-ae4f386835c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336903314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1336903314
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1987744549
Short name T1092
Test name
Test status
Simulation time 142143085 ps
CPU time 1.83 seconds
Started Aug 16 06:29:15 PM PDT 24
Finished Aug 16 06:29:17 PM PDT 24
Peak memory 207052 kb
Host smart-18188f28-8bca-459c-8c8c-0980d546bc82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987744549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1987744549
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.858501623
Short name T1111
Test name
Test status
Simulation time 36366163 ps
CPU time 1.57 seconds
Started Aug 16 06:29:11 PM PDT 24
Finished Aug 16 06:29:13 PM PDT 24
Peak memory 215300 kb
Host smart-c245c9d1-338d-4d33-a67b-36f4431894e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858501623 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.858501623
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.4032250071
Short name T248
Test name
Test status
Simulation time 93341978 ps
CPU time 0.91 seconds
Started Aug 16 06:29:13 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 206928 kb
Host smart-44fe27aa-6dbe-4513-9470-dc14ef6b1f25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032250071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.4032250071
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3714069406
Short name T1005
Test name
Test status
Simulation time 15551942 ps
CPU time 0.85 seconds
Started Aug 16 06:29:12 PM PDT 24
Finished Aug 16 06:29:13 PM PDT 24
Peak memory 206932 kb
Host smart-a4428fda-f52a-464d-b1ad-9934695b31cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714069406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3714069406
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1062364633
Short name T1046
Test name
Test status
Simulation time 47170925 ps
CPU time 0.98 seconds
Started Aug 16 06:29:13 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 207040 kb
Host smart-64b3b73c-a55e-4122-a643-c56ced9eb831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062364633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1062364633
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3449049680
Short name T1047
Test name
Test status
Simulation time 90366863 ps
CPU time 3.49 seconds
Started Aug 16 06:29:11 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 215188 kb
Host smart-cb3e65e1-7b63-489a-a5b0-0518fcfb9d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449049680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3449049680
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2212323026
Short name T1030
Test name
Test status
Simulation time 350412587 ps
CPU time 1.73 seconds
Started Aug 16 06:29:12 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 215240 kb
Host smart-44e704f8-d4df-4416-b614-2100de649791
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212323026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2212323026
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1447156610
Short name T984
Test name
Test status
Simulation time 438930356 ps
CPU time 2.02 seconds
Started Aug 16 06:29:14 PM PDT 24
Finished Aug 16 06:29:16 PM PDT 24
Peak memory 215308 kb
Host smart-c05c4d05-94cc-483a-8687-7e163c23bfe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447156610 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1447156610
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3016038221
Short name T1036
Test name
Test status
Simulation time 33617958 ps
CPU time 0.87 seconds
Started Aug 16 06:29:13 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 206936 kb
Host smart-3ac0abd7-9c9d-4505-b432-6af29e8c69ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016038221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3016038221
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1293336990
Short name T1056
Test name
Test status
Simulation time 47351362 ps
CPU time 0.88 seconds
Started Aug 16 06:29:13 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 206928 kb
Host smart-a756aedb-b962-49c7-a91e-bce166731516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293336990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1293336990
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3388892057
Short name T1101
Test name
Test status
Simulation time 19333835 ps
CPU time 1.23 seconds
Started Aug 16 06:29:13 PM PDT 24
Finished Aug 16 06:29:15 PM PDT 24
Peak memory 207092 kb
Host smart-778293f1-a288-4c68-ad22-8bc59709e6be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388892057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3388892057
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2457510302
Short name T1026
Test name
Test status
Simulation time 282405672 ps
CPU time 3.18 seconds
Started Aug 16 06:29:12 PM PDT 24
Finished Aug 16 06:29:15 PM PDT 24
Peak memory 215288 kb
Host smart-c15da0db-34ee-4e03-a8dc-976e53eef65d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457510302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2457510302
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.936955751
Short name T1110
Test name
Test status
Simulation time 108051626 ps
CPU time 1.34 seconds
Started Aug 16 06:29:13 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 215372 kb
Host smart-7fc0df49-add7-41ab-ba8a-53e7c78a919a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936955751 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.936955751
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3681771651
Short name T262
Test name
Test status
Simulation time 65689418 ps
CPU time 0.79 seconds
Started Aug 16 06:29:13 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 206760 kb
Host smart-8a2ea8ab-3519-491d-82ff-2cf9645d8980
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681771651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3681771651
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2187144764
Short name T1109
Test name
Test status
Simulation time 13180523 ps
CPU time 0.89 seconds
Started Aug 16 06:29:13 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 206860 kb
Host smart-73a3fd53-cdfb-4b45-bb52-213654b8b399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187144764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2187144764
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2658361246
Short name T1103
Test name
Test status
Simulation time 13967196 ps
CPU time 0.95 seconds
Started Aug 16 06:29:12 PM PDT 24
Finished Aug 16 06:29:13 PM PDT 24
Peak memory 207044 kb
Host smart-ebce5505-d9da-44a4-a655-94fd47568e89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658361246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2658361246
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.326219061
Short name T1060
Test name
Test status
Simulation time 97387031 ps
CPU time 2.34 seconds
Started Aug 16 06:29:14 PM PDT 24
Finished Aug 16 06:29:16 PM PDT 24
Peak memory 215300 kb
Host smart-946bde67-1180-4cd2-9329-74a2e96b7fba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326219061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.326219061
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2491588788
Short name T283
Test name
Test status
Simulation time 92096307 ps
CPU time 2.57 seconds
Started Aug 16 06:29:11 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 215316 kb
Host smart-bac4912f-bac3-4ffb-877e-1dddd8c77a78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491588788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2491588788
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.339055243
Short name T1081
Test name
Test status
Simulation time 191140484 ps
CPU time 1.01 seconds
Started Aug 16 06:29:19 PM PDT 24
Finished Aug 16 06:29:20 PM PDT 24
Peak memory 215300 kb
Host smart-f07ccb67-73b1-4b5a-8794-24360bd1bc01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339055243 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.339055243
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1661879595
Short name T256
Test name
Test status
Simulation time 23322121 ps
CPU time 0.96 seconds
Started Aug 16 06:29:20 PM PDT 24
Finished Aug 16 06:29:21 PM PDT 24
Peak memory 206980 kb
Host smart-f552c52d-bbbf-44a1-bdce-2cb0b923f63e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661879595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1661879595
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.725161439
Short name T996
Test name
Test status
Simulation time 23645359 ps
CPU time 0.8 seconds
Started Aug 16 06:29:20 PM PDT 24
Finished Aug 16 06:29:20 PM PDT 24
Peak memory 206744 kb
Host smart-0cd6a99b-f53c-4633-b405-d3532f987f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725161439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.725161439
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3841327948
Short name T1073
Test name
Test status
Simulation time 63334096 ps
CPU time 1.38 seconds
Started Aug 16 06:29:20 PM PDT 24
Finished Aug 16 06:29:22 PM PDT 24
Peak memory 207068 kb
Host smart-06415261-aba8-4cd7-8dbd-193d01144429
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841327948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3841327948
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2937176060
Short name T997
Test name
Test status
Simulation time 55782515 ps
CPU time 2.14 seconds
Started Aug 16 06:29:18 PM PDT 24
Finished Aug 16 06:29:20 PM PDT 24
Peak memory 215336 kb
Host smart-e1be75ef-c556-41cc-8112-11ebd877fdff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937176060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2937176060
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2210944108
Short name T1034
Test name
Test status
Simulation time 189313461 ps
CPU time 1.61 seconds
Started Aug 16 06:29:22 PM PDT 24
Finished Aug 16 06:29:24 PM PDT 24
Peak memory 207124 kb
Host smart-6b301e98-151b-4666-a349-726656fe4ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210944108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2210944108
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3224402035
Short name T1031
Test name
Test status
Simulation time 32504615 ps
CPU time 1.04 seconds
Started Aug 16 06:29:20 PM PDT 24
Finished Aug 16 06:29:21 PM PDT 24
Peak memory 216856 kb
Host smart-fac08734-5b3b-4892-8272-4acee84c1219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224402035 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3224402035
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2777185397
Short name T1098
Test name
Test status
Simulation time 19290647 ps
CPU time 0.88 seconds
Started Aug 16 06:29:21 PM PDT 24
Finished Aug 16 06:29:22 PM PDT 24
Peak memory 206996 kb
Host smart-bff8aad5-7f52-4f1e-a5b6-05b5a00651b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777185397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2777185397
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1464068101
Short name T1086
Test name
Test status
Simulation time 19015273 ps
CPU time 0.82 seconds
Started Aug 16 06:29:22 PM PDT 24
Finished Aug 16 06:29:23 PM PDT 24
Peak memory 206684 kb
Host smart-f0060e28-918a-4b3e-81c8-2a3e5661dcd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464068101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1464068101
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2071525208
Short name T258
Test name
Test status
Simulation time 114558352 ps
CPU time 1.32 seconds
Started Aug 16 06:29:23 PM PDT 24
Finished Aug 16 06:29:24 PM PDT 24
Peak memory 207128 kb
Host smart-be2ccbb4-3241-4fe4-80de-ceb1fef8fb87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071525208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2071525208
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.950850206
Short name T1059
Test name
Test status
Simulation time 128071358 ps
CPU time 2.54 seconds
Started Aug 16 06:29:21 PM PDT 24
Finished Aug 16 06:29:23 PM PDT 24
Peak memory 215224 kb
Host smart-7e9ceb48-7703-4f81-a52b-601a8bb33489
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950850206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.950850206
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.81320272
Short name T280
Test name
Test status
Simulation time 406271411 ps
CPU time 2.64 seconds
Started Aug 16 06:29:20 PM PDT 24
Finished Aug 16 06:29:23 PM PDT 24
Peak memory 207108 kb
Host smart-304fbc30-f32f-415a-b8cc-a3ca9d257d87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81320272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.81320272
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.958669472
Short name T1070
Test name
Test status
Simulation time 37712461 ps
CPU time 1.65 seconds
Started Aug 16 06:29:20 PM PDT 24
Finished Aug 16 06:29:22 PM PDT 24
Peak memory 215272 kb
Host smart-06ae1eeb-a447-408d-87ee-3eea30a4fe92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958669472 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.958669472
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.112966318
Short name T1099
Test name
Test status
Simulation time 22835499 ps
CPU time 0.84 seconds
Started Aug 16 06:29:22 PM PDT 24
Finished Aug 16 06:29:23 PM PDT 24
Peak memory 206988 kb
Host smart-cf6bf480-b936-4a54-a482-6f6946d3a50b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112966318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.112966318
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.564643376
Short name T1004
Test name
Test status
Simulation time 19565122 ps
CPU time 0.89 seconds
Started Aug 16 06:29:20 PM PDT 24
Finished Aug 16 06:29:21 PM PDT 24
Peak memory 206904 kb
Host smart-46cb7c2c-ce73-452f-acef-df8335035917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564643376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.564643376
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3587091757
Short name T1080
Test name
Test status
Simulation time 66599678 ps
CPU time 1.13 seconds
Started Aug 16 06:29:21 PM PDT 24
Finished Aug 16 06:29:22 PM PDT 24
Peak memory 207028 kb
Host smart-ee7bbfa9-6ddf-4151-9d26-8635b9d31b1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587091757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3587091757
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1962710446
Short name T1009
Test name
Test status
Simulation time 96908418 ps
CPU time 2.04 seconds
Started Aug 16 06:29:20 PM PDT 24
Finished Aug 16 06:29:22 PM PDT 24
Peak memory 215312 kb
Host smart-7eff8b50-cdf0-4433-b816-026cb8cef762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962710446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1962710446
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.13065465
Short name T1085
Test name
Test status
Simulation time 99849539 ps
CPU time 2.46 seconds
Started Aug 16 06:29:20 PM PDT 24
Finished Aug 16 06:29:23 PM PDT 24
Peak memory 207064 kb
Host smart-92467c69-fc6a-40ec-98da-01126f3fbc56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13065465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.13065465
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2871811869
Short name T1105
Test name
Test status
Simulation time 117457695 ps
CPU time 1.41 seconds
Started Aug 16 06:29:21 PM PDT 24
Finished Aug 16 06:29:23 PM PDT 24
Peak memory 217776 kb
Host smart-033b98b5-60fc-480a-9464-0712b22fed39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871811869 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2871811869
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1204595859
Short name T1094
Test name
Test status
Simulation time 47191073 ps
CPU time 0.89 seconds
Started Aug 16 06:29:21 PM PDT 24
Finished Aug 16 06:29:22 PM PDT 24
Peak memory 206936 kb
Host smart-b67720bb-bedf-40b5-8df3-378552bac9a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204595859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1204595859
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1799019576
Short name T1063
Test name
Test status
Simulation time 13192173 ps
CPU time 0.87 seconds
Started Aug 16 06:29:19 PM PDT 24
Finished Aug 16 06:29:20 PM PDT 24
Peak memory 206936 kb
Host smart-c768a4d2-52ba-48f8-861a-e6a28ee5070f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799019576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1799019576
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3328564007
Short name T259
Test name
Test status
Simulation time 54135248 ps
CPU time 0.95 seconds
Started Aug 16 06:29:21 PM PDT 24
Finished Aug 16 06:29:22 PM PDT 24
Peak memory 207084 kb
Host smart-f191df43-b9a0-4f25-aa5d-20ad5ecbbd24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328564007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3328564007
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2753546426
Short name T1017
Test name
Test status
Simulation time 75622137 ps
CPU time 2.47 seconds
Started Aug 16 06:29:23 PM PDT 24
Finished Aug 16 06:29:25 PM PDT 24
Peak memory 215284 kb
Host smart-67a787fb-b2e3-4a9a-8afc-4d74c807dccd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753546426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2753546426
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2720809122
Short name T272
Test name
Test status
Simulation time 122807166 ps
CPU time 1.72 seconds
Started Aug 16 06:29:22 PM PDT 24
Finished Aug 16 06:29:23 PM PDT 24
Peak memory 207056 kb
Host smart-479d76a1-18cd-446c-9d30-42bff5d7a921
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720809122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2720809122
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.921363442
Short name T1076
Test name
Test status
Simulation time 57987024 ps
CPU time 1.24 seconds
Started Aug 16 06:28:41 PM PDT 24
Finished Aug 16 06:28:43 PM PDT 24
Peak memory 207048 kb
Host smart-f7f962fc-f831-4dca-91b3-fb2d5a8c47d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921363442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.921363442
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3086971666
Short name T1072
Test name
Test status
Simulation time 35853348 ps
CPU time 2.04 seconds
Started Aug 16 06:28:39 PM PDT 24
Finished Aug 16 06:28:42 PM PDT 24
Peak memory 207064 kb
Host smart-afcd5843-9067-447e-ab2a-60aaeb367a6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086971666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3086971666
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.933850582
Short name T251
Test name
Test status
Simulation time 13766982 ps
CPU time 0.9 seconds
Started Aug 16 06:28:41 PM PDT 24
Finished Aug 16 06:28:42 PM PDT 24
Peak memory 207016 kb
Host smart-dcf2a9a8-7067-4c4a-9d80-69cf3c7f5b4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933850582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.933850582
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1785906198
Short name T1075
Test name
Test status
Simulation time 25988690 ps
CPU time 1.05 seconds
Started Aug 16 06:28:46 PM PDT 24
Finished Aug 16 06:28:48 PM PDT 24
Peak memory 215320 kb
Host smart-abf58a55-5b0a-46a5-9bb8-9b954ddba842
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785906198 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1785906198
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2316497541
Short name T1062
Test name
Test status
Simulation time 35190023 ps
CPU time 0.86 seconds
Started Aug 16 06:28:39 PM PDT 24
Finished Aug 16 06:28:40 PM PDT 24
Peak memory 206988 kb
Host smart-2a11ed0c-8ca3-4cc8-ba36-7e0debe7a105
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316497541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2316497541
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.169867696
Short name T1055
Test name
Test status
Simulation time 55624589 ps
CPU time 0.89 seconds
Started Aug 16 06:28:47 PM PDT 24
Finished Aug 16 06:28:48 PM PDT 24
Peak memory 206824 kb
Host smart-66cee7b0-03c8-47b6-9f24-3cfa0f7d647e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169867696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.169867696
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2266230603
Short name T260
Test name
Test status
Simulation time 55151098 ps
CPU time 1.04 seconds
Started Aug 16 06:28:37 PM PDT 24
Finished Aug 16 06:28:39 PM PDT 24
Peak memory 206996 kb
Host smart-2f14443a-7463-4152-9d77-40af5b784e3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266230603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2266230603
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2638180092
Short name T1001
Test name
Test status
Simulation time 140386565 ps
CPU time 1.81 seconds
Started Aug 16 06:28:42 PM PDT 24
Finished Aug 16 06:28:44 PM PDT 24
Peak memory 215296 kb
Host smart-5e59e179-31d9-4096-8007-2d52a3e71212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638180092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2638180092
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4079234775
Short name T1052
Test name
Test status
Simulation time 351294434 ps
CPU time 2.28 seconds
Started Aug 16 06:28:40 PM PDT 24
Finished Aug 16 06:28:43 PM PDT 24
Peak memory 207040 kb
Host smart-c714147f-f305-4532-a208-dbb5c156056d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079234775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4079234775
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3369936523
Short name T1033
Test name
Test status
Simulation time 27285706 ps
CPU time 0.82 seconds
Started Aug 16 06:29:21 PM PDT 24
Finished Aug 16 06:29:22 PM PDT 24
Peak memory 206736 kb
Host smart-7bbc073a-6e37-42e3-8d51-f5e519b76690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369936523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3369936523
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.450705491
Short name T1012
Test name
Test status
Simulation time 80918839 ps
CPU time 0.79 seconds
Started Aug 16 06:29:19 PM PDT 24
Finished Aug 16 06:29:20 PM PDT 24
Peak memory 206688 kb
Host smart-b63a78c4-baeb-42c8-9102-62a2fc6f1891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450705491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.450705491
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1346546591
Short name T1042
Test name
Test status
Simulation time 15297649 ps
CPU time 0.9 seconds
Started Aug 16 06:29:20 PM PDT 24
Finished Aug 16 06:29:21 PM PDT 24
Peak memory 206868 kb
Host smart-f1aa3162-1182-4b2f-857a-5dd12a613a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346546591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1346546591
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2792455747
Short name T1039
Test name
Test status
Simulation time 21384773 ps
CPU time 0.85 seconds
Started Aug 16 06:29:19 PM PDT 24
Finished Aug 16 06:29:20 PM PDT 24
Peak memory 206980 kb
Host smart-e987a88d-0a44-4c46-be18-65fcffb8fb2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792455747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2792455747
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4286243411
Short name T980
Test name
Test status
Simulation time 42625855 ps
CPU time 0.83 seconds
Started Aug 16 06:29:21 PM PDT 24
Finished Aug 16 06:29:22 PM PDT 24
Peak memory 206920 kb
Host smart-1e262349-567d-46fe-91bb-ccab3b79e975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286243411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4286243411
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.249692253
Short name T1007
Test name
Test status
Simulation time 16090842 ps
CPU time 0.95 seconds
Started Aug 16 06:29:21 PM PDT 24
Finished Aug 16 06:29:22 PM PDT 24
Peak memory 206924 kb
Host smart-fcdb353c-aa6f-40d4-878e-16072e6352ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249692253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.249692253
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.904182768
Short name T1037
Test name
Test status
Simulation time 15997281 ps
CPU time 0.89 seconds
Started Aug 16 06:29:37 PM PDT 24
Finished Aug 16 06:29:38 PM PDT 24
Peak memory 206908 kb
Host smart-bfb0e863-ae7b-4a11-9820-6b7e3d495524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904182768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.904182768
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.456630778
Short name T1090
Test name
Test status
Simulation time 48016926 ps
CPU time 0.88 seconds
Started Aug 16 06:29:39 PM PDT 24
Finished Aug 16 06:29:41 PM PDT 24
Peak memory 206884 kb
Host smart-1b91f63e-0e83-4276-a03a-f43872700817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456630778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.456630778
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.394133657
Short name T1088
Test name
Test status
Simulation time 15598810 ps
CPU time 0.89 seconds
Started Aug 16 06:29:33 PM PDT 24
Finished Aug 16 06:29:34 PM PDT 24
Peak memory 206904 kb
Host smart-1f9807a1-6508-4864-a7fe-db8b311872c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394133657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.394133657
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2098423994
Short name T1087
Test name
Test status
Simulation time 111770603 ps
CPU time 0.88 seconds
Started Aug 16 06:29:26 PM PDT 24
Finished Aug 16 06:29:27 PM PDT 24
Peak memory 206924 kb
Host smart-899dbc32-6d11-406d-aa8c-ee433cd688b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098423994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2098423994
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.661041724
Short name T254
Test name
Test status
Simulation time 60999736 ps
CPU time 1.45 seconds
Started Aug 16 06:28:48 PM PDT 24
Finished Aug 16 06:28:49 PM PDT 24
Peak memory 206960 kb
Host smart-c9a75551-8ec2-46e5-a549-7039aeeef861
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661041724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.661041724
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3723594740
Short name T255
Test name
Test status
Simulation time 38134727 ps
CPU time 2.07 seconds
Started Aug 16 06:28:40 PM PDT 24
Finished Aug 16 06:28:43 PM PDT 24
Peak memory 207012 kb
Host smart-5bfd164e-6714-48a5-b570-19f64ea0c2bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723594740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3723594740
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.946963622
Short name T257
Test name
Test status
Simulation time 44962581 ps
CPU time 0.86 seconds
Started Aug 16 06:28:47 PM PDT 24
Finished Aug 16 06:28:48 PM PDT 24
Peak memory 206924 kb
Host smart-714f90b6-112f-40f8-8a41-8d983c5510d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946963622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.946963622
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2054639090
Short name T1020
Test name
Test status
Simulation time 43492821 ps
CPU time 1.18 seconds
Started Aug 16 06:28:48 PM PDT 24
Finished Aug 16 06:28:49 PM PDT 24
Peak memory 215348 kb
Host smart-3a2e2062-04cf-4ad5-a27f-749a14272b7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054639090 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2054639090
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1371706493
Short name T1067
Test name
Test status
Simulation time 38519868 ps
CPU time 0.77 seconds
Started Aug 16 06:28:40 PM PDT 24
Finished Aug 16 06:28:41 PM PDT 24
Peak memory 206764 kb
Host smart-392374df-88ae-47db-be5f-dc4274c7aeac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371706493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1371706493
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.928536410
Short name T1089
Test name
Test status
Simulation time 39341672 ps
CPU time 0.82 seconds
Started Aug 16 06:28:46 PM PDT 24
Finished Aug 16 06:28:46 PM PDT 24
Peak memory 206920 kb
Host smart-c0be5b02-7190-46ea-a9da-4710eb00acb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928536410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.928536410
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.943890560
Short name T1065
Test name
Test status
Simulation time 78559390 ps
CPU time 1.1 seconds
Started Aug 16 06:28:44 PM PDT 24
Finished Aug 16 06:28:45 PM PDT 24
Peak memory 207056 kb
Host smart-3bd8b26c-d00d-42d5-a138-2536a0649498
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943890560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.943890560
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.291657580
Short name T1095
Test name
Test status
Simulation time 192393309 ps
CPU time 3.54 seconds
Started Aug 16 06:28:47 PM PDT 24
Finished Aug 16 06:28:51 PM PDT 24
Peak memory 215260 kb
Host smart-14c7637a-5a86-4107-a84d-89eeebcb60ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291657580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.291657580
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1237912254
Short name T1096
Test name
Test status
Simulation time 55347525 ps
CPU time 1.94 seconds
Started Aug 16 06:28:40 PM PDT 24
Finished Aug 16 06:28:42 PM PDT 24
Peak memory 215200 kb
Host smart-66fe571a-091b-467a-bce9-85cf787e0487
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237912254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1237912254
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.421480851
Short name T992
Test name
Test status
Simulation time 21074766 ps
CPU time 0.79 seconds
Started Aug 16 06:29:28 PM PDT 24
Finished Aug 16 06:29:29 PM PDT 24
Peak memory 206924 kb
Host smart-f41f1ac1-bf0b-4008-a458-451cd026caa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421480851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.421480851
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.4294890556
Short name T991
Test name
Test status
Simulation time 35786082 ps
CPU time 0.9 seconds
Started Aug 16 06:29:28 PM PDT 24
Finished Aug 16 06:29:29 PM PDT 24
Peak memory 206920 kb
Host smart-7e4bfcd3-1f20-434b-9433-b68f4e7d28bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294890556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.4294890556
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3485937789
Short name T993
Test name
Test status
Simulation time 12495456 ps
CPU time 0.85 seconds
Started Aug 16 06:29:30 PM PDT 24
Finished Aug 16 06:29:31 PM PDT 24
Peak memory 206908 kb
Host smart-d28c1a14-0f95-4926-9dea-e9a765c14f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485937789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3485937789
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3592195086
Short name T1106
Test name
Test status
Simulation time 32710565 ps
CPU time 0.76 seconds
Started Aug 16 06:29:26 PM PDT 24
Finished Aug 16 06:29:27 PM PDT 24
Peak memory 206828 kb
Host smart-7464a1da-8d1c-4678-8974-18dcba54a181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592195086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3592195086
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1701754856
Short name T1040
Test name
Test status
Simulation time 14232684 ps
CPU time 0.89 seconds
Started Aug 16 06:29:39 PM PDT 24
Finished Aug 16 06:29:40 PM PDT 24
Peak memory 206884 kb
Host smart-ebc5b559-8250-472a-8d8a-28c0da990e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701754856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1701754856
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3903169358
Short name T986
Test name
Test status
Simulation time 12333677 ps
CPU time 0.86 seconds
Started Aug 16 06:29:28 PM PDT 24
Finished Aug 16 06:29:29 PM PDT 24
Peak memory 206916 kb
Host smart-fce158ab-f0f5-4ca9-bf38-4c4091862f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903169358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3903169358
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.503958960
Short name T1021
Test name
Test status
Simulation time 29921296 ps
CPU time 0.78 seconds
Started Aug 16 06:29:29 PM PDT 24
Finished Aug 16 06:29:30 PM PDT 24
Peak memory 206764 kb
Host smart-60934ab5-b287-43b1-8830-5ce03403f131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503958960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.503958960
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2672645846
Short name T987
Test name
Test status
Simulation time 14031142 ps
CPU time 0.85 seconds
Started Aug 16 06:29:31 PM PDT 24
Finished Aug 16 06:29:32 PM PDT 24
Peak memory 206904 kb
Host smart-9c705154-4cab-43be-ae32-1c76de585a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672645846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2672645846
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1207514932
Short name T978
Test name
Test status
Simulation time 16330414 ps
CPU time 0.88 seconds
Started Aug 16 06:29:29 PM PDT 24
Finished Aug 16 06:29:30 PM PDT 24
Peak memory 206928 kb
Host smart-fab96b88-c47c-4a44-a3d8-0afec62fc7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207514932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1207514932
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.857280013
Short name T995
Test name
Test status
Simulation time 119276576 ps
CPU time 0.85 seconds
Started Aug 16 06:29:30 PM PDT 24
Finished Aug 16 06:29:31 PM PDT 24
Peak memory 206688 kb
Host smart-bd69eafb-b359-4ad5-a794-74c47b0c4d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857280013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.857280013
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3828877839
Short name T977
Test name
Test status
Simulation time 225251902 ps
CPU time 1.52 seconds
Started Aug 16 06:28:48 PM PDT 24
Finished Aug 16 06:28:50 PM PDT 24
Peak memory 206984 kb
Host smart-2f7608a1-aa24-41da-9304-b6b63752bdae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828877839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3828877839
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3628388723
Short name T994
Test name
Test status
Simulation time 624586662 ps
CPU time 3.03 seconds
Started Aug 16 06:28:46 PM PDT 24
Finished Aug 16 06:28:49 PM PDT 24
Peak memory 207000 kb
Host smart-31cba2b7-08a5-4577-85bd-5341a6069cab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628388723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3628388723
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3894438103
Short name T249
Test name
Test status
Simulation time 22838522 ps
CPU time 0.89 seconds
Started Aug 16 06:28:49 PM PDT 24
Finished Aug 16 06:28:50 PM PDT 24
Peak memory 206980 kb
Host smart-3fe8f92f-35c2-48f7-a213-45bf3fa466f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894438103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3894438103
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.90345890
Short name T1068
Test name
Test status
Simulation time 176029267 ps
CPU time 1.32 seconds
Started Aug 16 06:28:47 PM PDT 24
Finished Aug 16 06:28:49 PM PDT 24
Peak memory 215392 kb
Host smart-d6f730ac-649a-414e-9d96-26d2dd4df944
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90345890 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.90345890
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.667245330
Short name T1023
Test name
Test status
Simulation time 12000574 ps
CPU time 0.85 seconds
Started Aug 16 06:28:45 PM PDT 24
Finished Aug 16 06:28:46 PM PDT 24
Peak memory 207000 kb
Host smart-cf71e96a-f2ae-4b5a-b737-8ea23fc76fe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667245330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.667245330
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2755896639
Short name T1044
Test name
Test status
Simulation time 22312867 ps
CPU time 0.84 seconds
Started Aug 16 06:28:39 PM PDT 24
Finished Aug 16 06:28:40 PM PDT 24
Peak memory 206924 kb
Host smart-83992772-3851-40af-b857-1186dfd6101b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755896639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2755896639
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.9026968
Short name T1025
Test name
Test status
Simulation time 65797733 ps
CPU time 1.13 seconds
Started Aug 16 06:28:55 PM PDT 24
Finished Aug 16 06:28:56 PM PDT 24
Peak memory 207056 kb
Host smart-5e066628-22cf-4d0b-8efc-4ddc18aaf11b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9026968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outst
anding.9026968
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1117683219
Short name T1097
Test name
Test status
Simulation time 271899076 ps
CPU time 4.1 seconds
Started Aug 16 06:28:42 PM PDT 24
Finished Aug 16 06:28:46 PM PDT 24
Peak memory 215216 kb
Host smart-f968872a-9344-4330-bc6b-d24b0ee10b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117683219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1117683219
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.615159246
Short name T273
Test name
Test status
Simulation time 145219254 ps
CPU time 2.04 seconds
Started Aug 16 06:28:48 PM PDT 24
Finished Aug 16 06:28:51 PM PDT 24
Peak memory 207120 kb
Host smart-2f187d40-7b6b-4788-bebf-53ff53d17937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615159246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.615159246
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2691145217
Short name T1010
Test name
Test status
Simulation time 157390772 ps
CPU time 0.96 seconds
Started Aug 16 06:29:30 PM PDT 24
Finished Aug 16 06:29:31 PM PDT 24
Peak memory 206900 kb
Host smart-c7bac9c9-6908-4c8f-8904-191f4f1f2a24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691145217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2691145217
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.4284846846
Short name T1078
Test name
Test status
Simulation time 64148254 ps
CPU time 0.82 seconds
Started Aug 16 06:29:27 PM PDT 24
Finished Aug 16 06:29:28 PM PDT 24
Peak memory 206732 kb
Host smart-8b4af979-fb22-404f-ab3a-6ccc6a5bfd33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284846846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.4284846846
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2621185100
Short name T1003
Test name
Test status
Simulation time 14572611 ps
CPU time 0.86 seconds
Started Aug 16 06:29:28 PM PDT 24
Finished Aug 16 06:29:29 PM PDT 24
Peak memory 206948 kb
Host smart-b0028b9a-feb8-4626-9537-b8411408d1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621185100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2621185100
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.26804626
Short name T1027
Test name
Test status
Simulation time 31543970 ps
CPU time 0.93 seconds
Started Aug 16 06:29:33 PM PDT 24
Finished Aug 16 06:29:34 PM PDT 24
Peak memory 206884 kb
Host smart-3de2cabb-a642-466f-b28f-a2f61c623679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26804626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.26804626
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3442143372
Short name T1045
Test name
Test status
Simulation time 12201373 ps
CPU time 0.9 seconds
Started Aug 16 06:29:29 PM PDT 24
Finished Aug 16 06:29:30 PM PDT 24
Peak memory 206936 kb
Host smart-47eac007-0059-4fec-89e6-91f66c3f24b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442143372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3442143372
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3268312526
Short name T1002
Test name
Test status
Simulation time 11511361 ps
CPU time 0.84 seconds
Started Aug 16 06:29:28 PM PDT 24
Finished Aug 16 06:29:29 PM PDT 24
Peak memory 206928 kb
Host smart-4dcb97a4-8614-4014-ad3a-b6dd6e9e9cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268312526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3268312526
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.547277886
Short name T976
Test name
Test status
Simulation time 26465160 ps
CPU time 0.86 seconds
Started Aug 16 06:29:28 PM PDT 24
Finished Aug 16 06:29:29 PM PDT 24
Peak memory 206876 kb
Host smart-8c160032-25b5-4cc1-ba70-782776695f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547277886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.547277886
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.4157985595
Short name T1100
Test name
Test status
Simulation time 16436936 ps
CPU time 0.99 seconds
Started Aug 16 06:29:39 PM PDT 24
Finished Aug 16 06:29:40 PM PDT 24
Peak memory 206876 kb
Host smart-ac228f03-d40c-4b1b-a7dc-5be5e7f99e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157985595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.4157985595
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.537716159
Short name T1028
Test name
Test status
Simulation time 14599542 ps
CPU time 0.9 seconds
Started Aug 16 06:29:27 PM PDT 24
Finished Aug 16 06:29:28 PM PDT 24
Peak memory 206900 kb
Host smart-22880a2a-38c6-49c3-bb6a-83fb8831a269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537716159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.537716159
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1614031183
Short name T1054
Test name
Test status
Simulation time 15732002 ps
CPU time 0.91 seconds
Started Aug 16 06:29:32 PM PDT 24
Finished Aug 16 06:29:33 PM PDT 24
Peak memory 206880 kb
Host smart-59ace583-4de4-4bef-bd89-ff6c346f4aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614031183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1614031183
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2861024694
Short name T1041
Test name
Test status
Simulation time 71106856 ps
CPU time 1.12 seconds
Started Aug 16 06:28:48 PM PDT 24
Finished Aug 16 06:28:49 PM PDT 24
Peak memory 216644 kb
Host smart-bbf6ecbb-1c0c-4599-8683-fa266e1a4ec8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861024694 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2861024694
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2089684225
Short name T1019
Test name
Test status
Simulation time 53671297 ps
CPU time 0.95 seconds
Started Aug 16 06:28:46 PM PDT 24
Finished Aug 16 06:28:47 PM PDT 24
Peak memory 206960 kb
Host smart-8bd534d3-e733-4e39-b3b9-fe3a03625dac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089684225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2089684225
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1833711485
Short name T1050
Test name
Test status
Simulation time 14852172 ps
CPU time 0.89 seconds
Started Aug 16 06:28:48 PM PDT 24
Finished Aug 16 06:28:49 PM PDT 24
Peak memory 206952 kb
Host smart-eeb82ddd-2ac5-4b1d-9c7c-ecb0d7a01b8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833711485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1833711485
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3063456875
Short name T265
Test name
Test status
Simulation time 127875745 ps
CPU time 1.44 seconds
Started Aug 16 06:28:49 PM PDT 24
Finished Aug 16 06:28:51 PM PDT 24
Peak memory 207168 kb
Host smart-0c52452e-6000-4a04-bf15-f486aae3a0bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063456875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3063456875
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3437165146
Short name T982
Test name
Test status
Simulation time 432543578 ps
CPU time 4.13 seconds
Started Aug 16 06:28:50 PM PDT 24
Finished Aug 16 06:28:54 PM PDT 24
Peak memory 215332 kb
Host smart-8000b683-92fd-4ebe-94fb-be894c49692b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437165146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3437165146
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2087708661
Short name T281
Test name
Test status
Simulation time 188470282 ps
CPU time 1.67 seconds
Started Aug 16 06:28:45 PM PDT 24
Finished Aug 16 06:28:47 PM PDT 24
Peak memory 207044 kb
Host smart-72bc9961-8759-4cec-acff-269da3061e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087708661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2087708661
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1627535450
Short name T979
Test name
Test status
Simulation time 496980374 ps
CPU time 1.42 seconds
Started Aug 16 06:28:53 PM PDT 24
Finished Aug 16 06:28:55 PM PDT 24
Peak memory 218500 kb
Host smart-db08d51c-cea4-42b2-8d1c-78b903f51ae4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627535450 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1627535450
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1361278174
Short name T1108
Test name
Test status
Simulation time 13171903 ps
CPU time 0.92 seconds
Started Aug 16 06:28:47 PM PDT 24
Finished Aug 16 06:28:48 PM PDT 24
Peak memory 206992 kb
Host smart-02a4f591-b0db-40de-93c4-35d3a43273cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361278174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1361278174
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.520511622
Short name T1006
Test name
Test status
Simulation time 50288678 ps
CPU time 0.86 seconds
Started Aug 16 06:28:47 PM PDT 24
Finished Aug 16 06:28:48 PM PDT 24
Peak memory 206916 kb
Host smart-4856dc14-2170-4ce3-ac4c-1648efbfc33a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520511622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.520511622
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1509507056
Short name T266
Test name
Test status
Simulation time 103247689 ps
CPU time 1.12 seconds
Started Aug 16 06:28:55 PM PDT 24
Finished Aug 16 06:28:57 PM PDT 24
Peak memory 207056 kb
Host smart-98efb2d2-d55e-4046-87aa-e7c64e97aa8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509507056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1509507056
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1809384421
Short name T1016
Test name
Test status
Simulation time 175058355 ps
CPU time 2.92 seconds
Started Aug 16 06:28:50 PM PDT 24
Finished Aug 16 06:28:53 PM PDT 24
Peak memory 215340 kb
Host smart-c0c9e336-bf84-443c-97a1-4e4656ac9da6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809384421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1809384421
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.496507540
Short name T1079
Test name
Test status
Simulation time 98643337 ps
CPU time 2.51 seconds
Started Aug 16 06:28:48 PM PDT 24
Finished Aug 16 06:28:51 PM PDT 24
Peak memory 207448 kb
Host smart-ec2a4f95-15da-4b0e-bcc6-ebd33c6a58b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496507540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.496507540
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3224040259
Short name T990
Test name
Test status
Simulation time 30736814 ps
CPU time 1.44 seconds
Started Aug 16 06:28:53 PM PDT 24
Finished Aug 16 06:28:54 PM PDT 24
Peak memory 215388 kb
Host smart-42cb377e-8193-48e3-8575-152a42112d7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224040259 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3224040259
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3603395667
Short name T253
Test name
Test status
Simulation time 13564022 ps
CPU time 0.84 seconds
Started Aug 16 06:28:52 PM PDT 24
Finished Aug 16 06:28:53 PM PDT 24
Peak memory 207120 kb
Host smart-76b4f6bf-45c2-413b-a69b-31faff5015cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603395667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3603395667
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1837245779
Short name T1083
Test name
Test status
Simulation time 91349374 ps
CPU time 0.85 seconds
Started Aug 16 06:28:53 PM PDT 24
Finished Aug 16 06:28:54 PM PDT 24
Peak memory 206936 kb
Host smart-894c3b60-8e61-40c7-96a8-a951726b1143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837245779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1837245779
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.641176483
Short name T1015
Test name
Test status
Simulation time 35344222 ps
CPU time 1.02 seconds
Started Aug 16 06:28:56 PM PDT 24
Finished Aug 16 06:28:57 PM PDT 24
Peak memory 207068 kb
Host smart-a3085244-a76d-4845-9c79-96c20121a6ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641176483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.641176483
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2303583671
Short name T1064
Test name
Test status
Simulation time 252030965 ps
CPU time 2.39 seconds
Started Aug 16 06:28:54 PM PDT 24
Finished Aug 16 06:28:57 PM PDT 24
Peak memory 215244 kb
Host smart-6908d1ab-8f08-4810-92b9-894a6c38ad1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303583671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2303583671
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2913626794
Short name T1049
Test name
Test status
Simulation time 134712287 ps
CPU time 2.22 seconds
Started Aug 16 06:28:55 PM PDT 24
Finished Aug 16 06:28:58 PM PDT 24
Peak memory 206988 kb
Host smart-7ffbaef7-7dd6-4018-8fba-d8fa82b4e742
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913626794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2913626794
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3457549447
Short name T988
Test name
Test status
Simulation time 291146482 ps
CPU time 1.37 seconds
Started Aug 16 06:28:54 PM PDT 24
Finished Aug 16 06:28:55 PM PDT 24
Peak memory 215352 kb
Host smart-f6448145-6d51-4db3-a16e-2f9db66c07e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457549447 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3457549447
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1686953066
Short name T1084
Test name
Test status
Simulation time 19888286 ps
CPU time 0.86 seconds
Started Aug 16 06:28:54 PM PDT 24
Finished Aug 16 06:28:55 PM PDT 24
Peak memory 206936 kb
Host smart-28adc812-c2f3-430e-8793-f6e05a077185
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686953066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1686953066
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.343834815
Short name T1057
Test name
Test status
Simulation time 25110628 ps
CPU time 0.85 seconds
Started Aug 16 06:28:55 PM PDT 24
Finished Aug 16 06:28:56 PM PDT 24
Peak memory 206876 kb
Host smart-bec7ca75-c16c-448b-86f5-16c23e88b95c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343834815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.343834815
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1519615811
Short name T1048
Test name
Test status
Simulation time 29364944 ps
CPU time 1.3 seconds
Started Aug 16 06:28:54 PM PDT 24
Finished Aug 16 06:28:55 PM PDT 24
Peak memory 207196 kb
Host smart-0640b210-4bb1-43c4-b218-8570c3d96eb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519615811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1519615811
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1520196706
Short name T1058
Test name
Test status
Simulation time 911068623 ps
CPU time 4.19 seconds
Started Aug 16 06:28:55 PM PDT 24
Finished Aug 16 06:29:00 PM PDT 24
Peak memory 215292 kb
Host smart-7b851763-5bfe-4d27-ab84-68125b81e347
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520196706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1520196706
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3743476103
Short name T1071
Test name
Test status
Simulation time 252366652 ps
CPU time 2.57 seconds
Started Aug 16 06:28:53 PM PDT 24
Finished Aug 16 06:28:56 PM PDT 24
Peak memory 207112 kb
Host smart-229a1fe6-b73d-423f-97a6-98f4ae294b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743476103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3743476103
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.109943032
Short name T1008
Test name
Test status
Simulation time 25079881 ps
CPU time 1.6 seconds
Started Aug 16 06:28:55 PM PDT 24
Finished Aug 16 06:28:57 PM PDT 24
Peak memory 215324 kb
Host smart-04602f31-6166-4a8c-86a0-a36af5fa47f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109943032 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.109943032
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3242310214
Short name T1029
Test name
Test status
Simulation time 12517036 ps
CPU time 0.87 seconds
Started Aug 16 06:28:54 PM PDT 24
Finished Aug 16 06:28:55 PM PDT 24
Peak memory 207032 kb
Host smart-ee171151-c1e8-4b75-b291-edb47359928f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242310214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3242310214
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2178007080
Short name T1014
Test name
Test status
Simulation time 13595244 ps
CPU time 0.86 seconds
Started Aug 16 06:28:55 PM PDT 24
Finished Aug 16 06:28:56 PM PDT 24
Peak memory 206916 kb
Host smart-0163e714-1ead-45a6-9565-82b803de6569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178007080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2178007080
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3904880784
Short name T1053
Test name
Test status
Simulation time 85170513 ps
CPU time 1.13 seconds
Started Aug 16 06:28:54 PM PDT 24
Finished Aug 16 06:28:55 PM PDT 24
Peak memory 207112 kb
Host smart-66e21909-cec4-418f-81d8-39bacf31f4d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904880784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3904880784
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1334523222
Short name T1024
Test name
Test status
Simulation time 24842101 ps
CPU time 1.67 seconds
Started Aug 16 06:28:52 PM PDT 24
Finished Aug 16 06:28:54 PM PDT 24
Peak memory 215304 kb
Host smart-ebf31d16-2504-42da-9ba2-897f35a36733
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334523222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1334523222
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4026659909
Short name T1043
Test name
Test status
Simulation time 339594665 ps
CPU time 3.1 seconds
Started Aug 16 06:28:54 PM PDT 24
Finished Aug 16 06:28:57 PM PDT 24
Peak memory 215312 kb
Host smart-6ae3d449-6d57-4999-8512-531a34f5e80c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026659909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.4026659909
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3324012658
Short name T787
Test name
Test status
Simulation time 101786156 ps
CPU time 1.13 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:21:00 PM PDT 24
Peak memory 219708 kb
Host smart-753dd37c-d016-4ec8-a187-c9cbbaccb663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324012658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3324012658
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.134683620
Short name T573
Test name
Test status
Simulation time 20460697 ps
CPU time 0.9 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:21:00 PM PDT 24
Peak memory 206736 kb
Host smart-0e6ab947-00fa-4e17-a062-8dc4325e9060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134683620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.134683620
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3422788805
Short name T444
Test name
Test status
Simulation time 40307055 ps
CPU time 0.86 seconds
Started Aug 16 06:21:01 PM PDT 24
Finished Aug 16 06:21:02 PM PDT 24
Peak memory 215348 kb
Host smart-48d7dc68-f7da-4097-b555-92528d86921c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422788805 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3422788805
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.3414151371
Short name T434
Test name
Test status
Simulation time 41765238 ps
CPU time 0.93 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:21:00 PM PDT 24
Peak memory 219404 kb
Host smart-78c7175a-5975-421e-ab6e-75c805171652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414151371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3414151371
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_regwen.3430801753
Short name T441
Test name
Test status
Simulation time 19529366 ps
CPU time 1.08 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:20:59 PM PDT 24
Peak memory 207216 kb
Host smart-7ede7cb8-d411-4801-96b9-317727f283ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430801753 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3430801753
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1322625683
Short name T54
Test name
Test status
Simulation time 611637314 ps
CPU time 9.17 seconds
Started Aug 16 06:21:02 PM PDT 24
Finished Aug 16 06:21:11 PM PDT 24
Peak memory 240364 kb
Host smart-88aef5a4-1e4a-48b6-8573-7cb865f1c855
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322625683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1322625683
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2356393899
Short name T789
Test name
Test status
Simulation time 42357645 ps
CPU time 0.99 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:20:59 PM PDT 24
Peak memory 215376 kb
Host smart-f34171c1-c2d8-4171-b380-9f31f7d4e231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356393899 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2356393899
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3673259543
Short name T713
Test name
Test status
Simulation time 280521678 ps
CPU time 5.52 seconds
Started Aug 16 06:20:56 PM PDT 24
Finished Aug 16 06:21:02 PM PDT 24
Peak memory 215372 kb
Host smart-59a4a0b9-9c48-44c2-b8ad-a97564afbc17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673259543 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3673259543
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2496638680
Short name T222
Test name
Test status
Simulation time 2295188979 ps
CPU time 49.05 seconds
Started Aug 16 06:21:05 PM PDT 24
Finished Aug 16 06:21:54 PM PDT 24
Peak memory 218272 kb
Host smart-4df13a4f-012f-4609-bca2-18daf171c3a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496638680 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2496638680
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1773857189
Short name T414
Test name
Test status
Simulation time 64014759 ps
CPU time 1.14 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:20:59 PM PDT 24
Peak memory 219996 kb
Host smart-da9700cb-a4c6-4a60-8722-63f5edabb739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773857189 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1773857189
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.672932130
Short name T628
Test name
Test status
Simulation time 131119814 ps
CPU time 0.89 seconds
Started Aug 16 06:21:00 PM PDT 24
Finished Aug 16 06:21:01 PM PDT 24
Peak memory 206448 kb
Host smart-cf1018aa-1918-482b-b4b8-af674aeb6cff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672932130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.672932130
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1872608143
Short name T42
Test name
Test status
Simulation time 16621376 ps
CPU time 0.87 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:20:59 PM PDT 24
Peak memory 215128 kb
Host smart-710c2311-9f1c-423d-ad1c-a23daf717d17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872608143 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1872608143
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.3406363744
Short name T566
Test name
Test status
Simulation time 28465064 ps
CPU time 1.07 seconds
Started Aug 16 06:20:57 PM PDT 24
Finished Aug 16 06:20:58 PM PDT 24
Peak memory 218476 kb
Host smart-17e5aea9-39b6-46e5-bb76-7dcec86ed03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406363744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3406363744
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2280252095
Short name T832
Test name
Test status
Simulation time 43192904 ps
CPU time 1.49 seconds
Started Aug 16 06:21:03 PM PDT 24
Finished Aug 16 06:21:05 PM PDT 24
Peak memory 218484 kb
Host smart-16586651-740c-43a7-b4dd-1979c47ee23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280252095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2280252095
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2137068768
Short name T963
Test name
Test status
Simulation time 24012441 ps
CPU time 0.95 seconds
Started Aug 16 06:21:02 PM PDT 24
Finished Aug 16 06:21:03 PM PDT 24
Peak memory 215896 kb
Host smart-aa3d7379-014f-495a-91fe-2ba82259c763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137068768 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2137068768
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1634204767
Short name T297
Test name
Test status
Simulation time 36016504 ps
CPU time 1.05 seconds
Started Aug 16 06:21:00 PM PDT 24
Finished Aug 16 06:21:01 PM PDT 24
Peak memory 207188 kb
Host smart-34663880-eef3-49fe-8e65-da1c928ae72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634204767 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1634204767
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2910866158
Short name T14
Test name
Test status
Simulation time 952099996 ps
CPU time 7.72 seconds
Started Aug 16 06:21:02 PM PDT 24
Finished Aug 16 06:21:10 PM PDT 24
Peak memory 236516 kb
Host smart-0632432e-04f0-46e8-b4d0-3e16e068a746
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910866158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2910866158
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1421203829
Short name T553
Test name
Test status
Simulation time 25378732 ps
CPU time 1 seconds
Started Aug 16 06:20:57 PM PDT 24
Finished Aug 16 06:20:59 PM PDT 24
Peak memory 215364 kb
Host smart-c2945c17-a3fa-4982-a759-ec6afbb5ccac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421203829 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1421203829
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1751237853
Short name T91
Test name
Test status
Simulation time 210310995 ps
CPU time 4.71 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:11 PM PDT 24
Peak memory 217520 kb
Host smart-ae41261f-9f3c-4105-8ee1-c32a6bbb68cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751237853 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1751237853
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.1952974591
Short name T269
Test name
Test status
Simulation time 82878603 ps
CPU time 1.15 seconds
Started Aug 16 06:21:21 PM PDT 24
Finished Aug 16 06:21:22 PM PDT 24
Peak memory 219844 kb
Host smart-c0b971cf-6abf-40f2-af5a-2e3571b9a46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952974591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1952974591
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2038701426
Short name T505
Test name
Test status
Simulation time 40005573 ps
CPU time 0.89 seconds
Started Aug 16 06:21:17 PM PDT 24
Finished Aug 16 06:21:18 PM PDT 24
Peak memory 206784 kb
Host smart-16488382-e48b-4f00-b14b-7785dbc23be5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038701426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2038701426
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1991915573
Short name T751
Test name
Test status
Simulation time 14349414 ps
CPU time 0.93 seconds
Started Aug 16 06:21:20 PM PDT 24
Finished Aug 16 06:21:21 PM PDT 24
Peak memory 215592 kb
Host smart-94e97dad-10f4-49be-a490-b60874593395
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991915573 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1991915573
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2643387186
Short name T718
Test name
Test status
Simulation time 44284092 ps
CPU time 1.18 seconds
Started Aug 16 06:21:29 PM PDT 24
Finished Aug 16 06:21:30 PM PDT 24
Peak memory 215300 kb
Host smart-ece4c08b-b80a-4d8d-a8ac-1f46a3663b01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643387186 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2643387186
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2524741777
Short name T824
Test name
Test status
Simulation time 44175481 ps
CPU time 1.1 seconds
Started Aug 16 06:21:24 PM PDT 24
Finished Aug 16 06:21:25 PM PDT 24
Peak memory 219852 kb
Host smart-400e5392-f900-4abf-8ad2-98aff10ff843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524741777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2524741777
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.3187137686
Short name T625
Test name
Test status
Simulation time 21122044 ps
CPU time 1.14 seconds
Started Aug 16 06:21:17 PM PDT 24
Finished Aug 16 06:21:18 PM PDT 24
Peak memory 215496 kb
Host smart-eeecd52b-f20d-436e-8e12-e23387c5888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187137686 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3187137686
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1752373460
Short name T562
Test name
Test status
Simulation time 27232183 ps
CPU time 0.92 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 215308 kb
Host smart-4fa80cb0-ad1a-4c49-92bc-a912158b25e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752373460 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1752373460
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1910993639
Short name T354
Test name
Test status
Simulation time 553543154 ps
CPU time 8.34 seconds
Started Aug 16 06:21:17 PM PDT 24
Finished Aug 16 06:21:26 PM PDT 24
Peak memory 217416 kb
Host smart-a8a27d79-db3c-48a0-88e0-c4d914f4d898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910993639 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1910993639
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.3041206450
Short name T530
Test name
Test status
Simulation time 40279738 ps
CPU time 1.1 seconds
Started Aug 16 06:22:32 PM PDT 24
Finished Aug 16 06:22:33 PM PDT 24
Peak memory 219108 kb
Host smart-93007b3d-8011-4b5f-9d9e-d273a30e222b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041206450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.3041206450
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.4207849466
Short name T31
Test name
Test status
Simulation time 88940997 ps
CPU time 1.28 seconds
Started Aug 16 06:23:00 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 218832 kb
Host smart-8d578073-b0cd-4a4a-b541-431ab0e93e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207849466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4207849466
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3759565491
Short name T320
Test name
Test status
Simulation time 31215090 ps
CPU time 1.16 seconds
Started Aug 16 06:22:28 PM PDT 24
Finished Aug 16 06:22:29 PM PDT 24
Peak memory 218320 kb
Host smart-3cacd9ac-a450-4f75-95bf-1f9194bc443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759565491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3759565491
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.2278100569
Short name T216
Test name
Test status
Simulation time 119005496 ps
CPU time 1.26 seconds
Started Aug 16 06:22:37 PM PDT 24
Finished Aug 16 06:22:38 PM PDT 24
Peak memory 218476 kb
Host smart-2927922f-db3a-4836-8444-65d110981b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278100569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.2278100569
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/102.edn_genbits.1308810191
Short name T745
Test name
Test status
Simulation time 52845299 ps
CPU time 1.01 seconds
Started Aug 16 06:22:38 PM PDT 24
Finished Aug 16 06:22:39 PM PDT 24
Peak memory 217480 kb
Host smart-7014f9f1-7599-4fa8-890d-a8f07f02afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308810191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1308810191
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.4143469546
Short name T384
Test name
Test status
Simulation time 196953558 ps
CPU time 1.7 seconds
Started Aug 16 06:22:34 PM PDT 24
Finished Aug 16 06:22:36 PM PDT 24
Peak memory 218964 kb
Host smart-fad30940-a32a-4aeb-8542-125303491275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143469546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4143469546
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.4052668112
Short name T445
Test name
Test status
Simulation time 81417990 ps
CPU time 1.09 seconds
Started Aug 16 06:22:39 PM PDT 24
Finished Aug 16 06:22:40 PM PDT 24
Peak memory 219896 kb
Host smart-7f7bfabc-07d2-4794-a0f0-297d1ff3a260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052668112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.4052668112
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.4205089558
Short name T950
Test name
Test status
Simulation time 49809593 ps
CPU time 1.74 seconds
Started Aug 16 06:22:31 PM PDT 24
Finished Aug 16 06:22:33 PM PDT 24
Peak memory 218708 kb
Host smart-2174606f-00c6-4ed1-8396-90fa181fe0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205089558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.4205089558
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.3233992157
Short name T772
Test name
Test status
Simulation time 40513794 ps
CPU time 1.14 seconds
Started Aug 16 06:22:31 PM PDT 24
Finished Aug 16 06:22:32 PM PDT 24
Peak memory 217316 kb
Host smart-7639dfaa-60f7-4c51-b04e-922f95c3cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233992157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.3233992157
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3285921844
Short name T470
Test name
Test status
Simulation time 158560256 ps
CPU time 2.36 seconds
Started Aug 16 06:22:56 PM PDT 24
Finished Aug 16 06:22:59 PM PDT 24
Peak memory 219448 kb
Host smart-821231ea-d48f-4268-8533-b50b88a53a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285921844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3285921844
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.712397906
Short name T512
Test name
Test status
Simulation time 42851802 ps
CPU time 1.17 seconds
Started Aug 16 06:22:44 PM PDT 24
Finished Aug 16 06:22:46 PM PDT 24
Peak memory 219716 kb
Host smart-7ec0333b-33fb-4a0a-b924-a2055c11e29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712397906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.712397906
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/107.edn_genbits.1059967144
Short name T561
Test name
Test status
Simulation time 74293480 ps
CPU time 2.56 seconds
Started Aug 16 06:22:37 PM PDT 24
Finished Aug 16 06:22:40 PM PDT 24
Peak memory 218616 kb
Host smart-c44ffce0-ddfc-4d42-9ea6-8b60d50e3cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059967144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1059967144
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1355566826
Short name T649
Test name
Test status
Simulation time 99714366 ps
CPU time 1.27 seconds
Started Aug 16 06:22:50 PM PDT 24
Finished Aug 16 06:22:51 PM PDT 24
Peak memory 219140 kb
Host smart-9c8bff35-1be5-4d35-b78b-bb38fe531df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355566826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1355566826
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.3002623332
Short name T362
Test name
Test status
Simulation time 28380469 ps
CPU time 1.22 seconds
Started Aug 16 06:22:26 PM PDT 24
Finished Aug 16 06:22:28 PM PDT 24
Peak memory 219636 kb
Host smart-d0611c0c-30ac-4773-9211-5afa37542cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002623332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.3002623332
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.1287146221
Short name T453
Test name
Test status
Simulation time 117569853 ps
CPU time 1.45 seconds
Started Aug 16 06:22:28 PM PDT 24
Finished Aug 16 06:22:29 PM PDT 24
Peak memory 219260 kb
Host smart-b1bd15fc-183b-4454-b82d-1f0fb7d85726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287146221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1287146221
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_disable.3738230150
Short name T933
Test name
Test status
Simulation time 39587740 ps
CPU time 0.95 seconds
Started Aug 16 06:21:18 PM PDT 24
Finished Aug 16 06:21:19 PM PDT 24
Peak memory 215452 kb
Host smart-e8127613-5a5c-43ec-a60a-fc5e5412523a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738230150 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3738230150
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2525363576
Short name T57
Test name
Test status
Simulation time 77551509 ps
CPU time 1.06 seconds
Started Aug 16 06:21:15 PM PDT 24
Finished Aug 16 06:21:16 PM PDT 24
Peak memory 216908 kb
Host smart-59476879-5148-4517-8d0a-9b901858fef2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525363576 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2525363576
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3446403247
Short name T699
Test name
Test status
Simulation time 30858766 ps
CPU time 1.01 seconds
Started Aug 16 06:21:17 PM PDT 24
Finished Aug 16 06:21:18 PM PDT 24
Peak memory 224052 kb
Host smart-a2c8cfe2-5f97-49a3-8987-5fe6ef2d7923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446403247 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3446403247
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1899316711
Short name T30
Test name
Test status
Simulation time 50991409 ps
CPU time 1.77 seconds
Started Aug 16 06:21:16 PM PDT 24
Finished Aug 16 06:21:18 PM PDT 24
Peak memory 217648 kb
Host smart-263a0a92-ff97-4bd5-81d2-600af6c3fca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899316711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1899316711
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.4081635218
Short name T402
Test name
Test status
Simulation time 27615369 ps
CPU time 0.89 seconds
Started Aug 16 06:21:26 PM PDT 24
Finished Aug 16 06:21:27 PM PDT 24
Peak memory 215760 kb
Host smart-f891c0fe-26e9-439c-bc8f-c2e00cfdcde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081635218 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4081635218
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.221058834
Short name T454
Test name
Test status
Simulation time 43078348 ps
CPU time 0.87 seconds
Started Aug 16 06:21:15 PM PDT 24
Finished Aug 16 06:21:16 PM PDT 24
Peak memory 215356 kb
Host smart-8b70f33f-0060-4f69-bd45-45fb0648e61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221058834 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.221058834
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.4068322754
Short name T237
Test name
Test status
Simulation time 714025624 ps
CPU time 4.02 seconds
Started Aug 16 06:21:15 PM PDT 24
Finished Aug 16 06:21:19 PM PDT 24
Peak memory 217428 kb
Host smart-75ebc338-5d84-4478-aed9-4e86a89f9517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068322754 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4068322754
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2545500205
Short name T549
Test name
Test status
Simulation time 2429395738 ps
CPU time 68.93 seconds
Started Aug 16 06:21:16 PM PDT 24
Finished Aug 16 06:22:25 PM PDT 24
Peak memory 220864 kb
Host smart-47125b8d-2324-4709-a0fc-40b8a6dc57b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545500205 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2545500205
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1923163500
Short name T215
Test name
Test status
Simulation time 59602465 ps
CPU time 1.19 seconds
Started Aug 16 06:22:27 PM PDT 24
Finished Aug 16 06:22:29 PM PDT 24
Peak memory 220476 kb
Host smart-e11e07d2-5aaf-446e-bb13-1c565fe75090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923163500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1923163500
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.312184345
Short name T851
Test name
Test status
Simulation time 60892693 ps
CPU time 1.18 seconds
Started Aug 16 06:22:29 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 218848 kb
Host smart-78548700-860d-4667-ba20-0cd018c71509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312184345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.312184345
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_alert.1023458094
Short name T582
Test name
Test status
Simulation time 72019582 ps
CPU time 1.21 seconds
Started Aug 16 06:22:44 PM PDT 24
Finished Aug 16 06:22:45 PM PDT 24
Peak memory 220596 kb
Host smart-26ba6f71-f625-42d6-b7b7-f8d12b7403ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023458094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.1023458094
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/111.edn_genbits.1293042229
Short name T608
Test name
Test status
Simulation time 47207498 ps
CPU time 1.58 seconds
Started Aug 16 06:22:57 PM PDT 24
Finished Aug 16 06:22:58 PM PDT 24
Peak memory 218748 kb
Host smart-5d0bd04b-4c8f-44cd-9b7e-8d42f04e473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293042229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1293042229
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.3464648865
Short name T817
Test name
Test status
Simulation time 26180100 ps
CPU time 1.19 seconds
Started Aug 16 06:22:50 PM PDT 24
Finished Aug 16 06:22:51 PM PDT 24
Peak memory 218448 kb
Host smart-cebee684-527f-4f9e-a85b-f2b8b2e8aa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464648865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.3464648865
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.3113737910
Short name T563
Test name
Test status
Simulation time 30555881 ps
CPU time 1.2 seconds
Started Aug 16 06:22:54 PM PDT 24
Finished Aug 16 06:22:56 PM PDT 24
Peak memory 218676 kb
Host smart-7a746d91-aef2-41c0-8d2a-9ab85ec54378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113737910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3113737910
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.1193135098
Short name T70
Test name
Test status
Simulation time 77999917 ps
CPU time 1.15 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 219688 kb
Host smart-b6430695-8043-4776-bcdb-fea55389dbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193135098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1193135098
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.3364937296
Short name T37
Test name
Test status
Simulation time 51597757 ps
CPU time 1.33 seconds
Started Aug 16 06:22:39 PM PDT 24
Finished Aug 16 06:22:40 PM PDT 24
Peak memory 218688 kb
Host smart-10a2d564-b5da-44c2-acc1-a9b582825392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364937296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3364937296
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.327334351
Short name T61
Test name
Test status
Simulation time 87151862 ps
CPU time 1.21 seconds
Started Aug 16 06:22:39 PM PDT 24
Finished Aug 16 06:22:41 PM PDT 24
Peak memory 218928 kb
Host smart-6aa3cfcb-56de-42f8-b0f8-f919c41c0d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327334351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.327334351
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_alert.1709872321
Short name T770
Test name
Test status
Simulation time 32613805 ps
CPU time 1.39 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 215752 kb
Host smart-d209ca1a-6912-4322-9dc8-f50045ba22ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709872321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.1709872321
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.3634641165
Short name T906
Test name
Test status
Simulation time 44458668 ps
CPU time 1.64 seconds
Started Aug 16 06:22:38 PM PDT 24
Finished Aug 16 06:22:40 PM PDT 24
Peak memory 218640 kb
Host smart-f033f3bc-adcf-4efa-836d-cbb34ea4e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634641165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3634641165
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.1414565933
Short name T631
Test name
Test status
Simulation time 27028791 ps
CPU time 1.24 seconds
Started Aug 16 06:22:37 PM PDT 24
Finished Aug 16 06:22:38 PM PDT 24
Peak memory 218888 kb
Host smart-ac3270e0-79a4-41c6-ab57-1a70accf7e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414565933 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.1414565933
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.908532644
Short name T904
Test name
Test status
Simulation time 79382010 ps
CPU time 2.57 seconds
Started Aug 16 06:22:37 PM PDT 24
Finished Aug 16 06:22:40 PM PDT 24
Peak memory 218644 kb
Host smart-e38aa1e2-23bd-4a19-86c0-c44445861775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908532644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.908532644
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1826819794
Short name T404
Test name
Test status
Simulation time 23655757 ps
CPU time 1.14 seconds
Started Aug 16 06:22:36 PM PDT 24
Finished Aug 16 06:22:37 PM PDT 24
Peak memory 220068 kb
Host smart-463ac694-f66c-4025-9b6d-a8770624567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826819794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1826819794
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.882719907
Short name T973
Test name
Test status
Simulation time 83027195 ps
CPU time 1.63 seconds
Started Aug 16 06:22:49 PM PDT 24
Finished Aug 16 06:22:50 PM PDT 24
Peak memory 219072 kb
Host smart-615a6d14-d866-4dba-9438-129b97b89926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882719907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.882719907
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.3591356389
Short name T449
Test name
Test status
Simulation time 27518014 ps
CPU time 1.31 seconds
Started Aug 16 06:22:36 PM PDT 24
Finished Aug 16 06:22:37 PM PDT 24
Peak memory 220244 kb
Host smart-b8179038-848a-4405-9fb2-3ff95186f814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591356389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3591356389
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.1893123610
Short name T946
Test name
Test status
Simulation time 71554922 ps
CPU time 1.4 seconds
Started Aug 16 06:22:37 PM PDT 24
Finished Aug 16 06:22:39 PM PDT 24
Peak memory 219140 kb
Host smart-ba507746-f37c-4ba4-8329-a90439cb4010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893123610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1893123610
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.4183358969
Short name T722
Test name
Test status
Simulation time 32125720 ps
CPU time 1.36 seconds
Started Aug 16 06:22:35 PM PDT 24
Finished Aug 16 06:22:37 PM PDT 24
Peak memory 220712 kb
Host smart-6d318ed2-0f3e-45fd-a8a2-11028ac084c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183358969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.4183358969
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.1159282290
Short name T319
Test name
Test status
Simulation time 80163713 ps
CPU time 1.14 seconds
Started Aug 16 06:22:35 PM PDT 24
Finished Aug 16 06:22:37 PM PDT 24
Peak memory 217364 kb
Host smart-ea572dd2-06e4-4158-b5fb-7c4ed90b41c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159282290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1159282290
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3675983448
Short name T590
Test name
Test status
Simulation time 27316692 ps
CPU time 1.28 seconds
Started Aug 16 06:21:30 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 219656 kb
Host smart-635e40fe-4399-441e-b61b-24cd24babed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675983448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3675983448
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1028431458
Short name T432
Test name
Test status
Simulation time 40743670 ps
CPU time 0.85 seconds
Started Aug 16 06:21:15 PM PDT 24
Finished Aug 16 06:21:16 PM PDT 24
Peak memory 206776 kb
Host smart-13a8ddae-1437-4cbb-a4ba-7b3a3b4791a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028431458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1028431458
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1858338519
Short name T381
Test name
Test status
Simulation time 18073605 ps
CPU time 0.84 seconds
Started Aug 16 06:21:29 PM PDT 24
Finished Aug 16 06:21:29 PM PDT 24
Peak memory 215144 kb
Host smart-850800a9-f442-419d-94b0-40c21cff9137
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858338519 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1858338519
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1610140654
Short name T146
Test name
Test status
Simulation time 71581465 ps
CPU time 1.25 seconds
Started Aug 16 06:21:27 PM PDT 24
Finished Aug 16 06:21:28 PM PDT 24
Peak memory 216972 kb
Host smart-fd8ab54e-0152-4f11-9c32-2eaae8562579
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610140654 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1610140654
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2931607813
Short name T541
Test name
Test status
Simulation time 18603428 ps
CPU time 1.16 seconds
Started Aug 16 06:21:15 PM PDT 24
Finished Aug 16 06:21:16 PM PDT 24
Peak memory 224100 kb
Host smart-f656520b-e788-46da-9106-91145e820a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931607813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2931607813
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3843019372
Short name T570
Test name
Test status
Simulation time 119281370 ps
CPU time 1.04 seconds
Started Aug 16 06:21:24 PM PDT 24
Finished Aug 16 06:21:25 PM PDT 24
Peak memory 217332 kb
Host smart-82ff6815-0e4d-45a5-8e6c-6125d72fe1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843019372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3843019372
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1214653726
Short name T957
Test name
Test status
Simulation time 22303182 ps
CPU time 1.29 seconds
Started Aug 16 06:21:15 PM PDT 24
Finished Aug 16 06:21:16 PM PDT 24
Peak memory 224264 kb
Host smart-78a60031-3b5f-46e4-a975-0dc43cf4e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214653726 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1214653726
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2242838388
Short name T837
Test name
Test status
Simulation time 51770976 ps
CPU time 0.98 seconds
Started Aug 16 06:21:14 PM PDT 24
Finished Aug 16 06:21:16 PM PDT 24
Peak memory 215352 kb
Host smart-0ceca65a-51dd-4908-b044-3b85ce803050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242838388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2242838388
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.353870934
Short name T664
Test name
Test status
Simulation time 322649337 ps
CPU time 6.27 seconds
Started Aug 16 06:21:22 PM PDT 24
Finished Aug 16 06:21:28 PM PDT 24
Peak memory 215432 kb
Host smart-c3305fd7-31c4-430c-ab96-aaa7b5bf033a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353870934 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.353870934
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1147978489
Short name T564
Test name
Test status
Simulation time 4247206511 ps
CPU time 28.59 seconds
Started Aug 16 06:21:14 PM PDT 24
Finished Aug 16 06:21:43 PM PDT 24
Peak memory 220060 kb
Host smart-1c940a7c-60b2-4f0b-824c-ab6552116ff9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147978489 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1147978489
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.1905556095
Short name T72
Test name
Test status
Simulation time 27075423 ps
CPU time 1.3 seconds
Started Aug 16 06:22:55 PM PDT 24
Finished Aug 16 06:22:56 PM PDT 24
Peak memory 219644 kb
Host smart-85d46eca-e70d-4e60-98ad-a6df99d9b50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905556095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.1905556095
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.1292023309
Short name T769
Test name
Test status
Simulation time 53515387 ps
CPU time 1.17 seconds
Started Aug 16 06:22:42 PM PDT 24
Finished Aug 16 06:22:43 PM PDT 24
Peak memory 218460 kb
Host smart-d32d82ec-00dc-4479-84d7-8ae7ae099222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292023309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1292023309
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.2473328032
Short name T173
Test name
Test status
Simulation time 66656794 ps
CPU time 1.08 seconds
Started Aug 16 06:22:37 PM PDT 24
Finished Aug 16 06:22:39 PM PDT 24
Peak memory 219856 kb
Host smart-aa5c66a1-7fe3-44db-bb47-05d007dcd86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473328032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.2473328032
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.2306658390
Short name T613
Test name
Test status
Simulation time 87521765 ps
CPU time 1.17 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 217280 kb
Host smart-eef6ecc8-1759-4f2d-946e-acbe6d247017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306658390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2306658390
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_alert.1506442328
Short name T382
Test name
Test status
Simulation time 189337286 ps
CPU time 1.17 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 219016 kb
Host smart-794742d8-308f-4ffd-9e21-b1958c29da8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506442328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.1506442328
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.714112208
Short name T394
Test name
Test status
Simulation time 64271031 ps
CPU time 1.38 seconds
Started Aug 16 06:22:35 PM PDT 24
Finished Aug 16 06:22:37 PM PDT 24
Peak memory 217476 kb
Host smart-bd0b84b7-77e7-4776-8dd9-419458144f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714112208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.714112208
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.542789885
Short name T39
Test name
Test status
Simulation time 30127410 ps
CPU time 1.09 seconds
Started Aug 16 06:22:52 PM PDT 24
Finished Aug 16 06:22:53 PM PDT 24
Peak memory 218748 kb
Host smart-25b8737b-393d-4ad2-bc3b-f40396204ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542789885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.542789885
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1626866669
Short name T743
Test name
Test status
Simulation time 145400319 ps
CPU time 1.19 seconds
Started Aug 16 06:22:55 PM PDT 24
Finished Aug 16 06:22:56 PM PDT 24
Peak memory 217360 kb
Host smart-3182a356-96d8-4d7b-aed8-fcdc09ba6db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626866669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1626866669
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.1915622596
Short name T409
Test name
Test status
Simulation time 30828483 ps
CPU time 1.38 seconds
Started Aug 16 06:22:36 PM PDT 24
Finished Aug 16 06:22:37 PM PDT 24
Peak memory 219904 kb
Host smart-8ac97cfa-ef22-4e2d-a0c8-c5c3daa63d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915622596 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1915622596
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.108396567
Short name T333
Test name
Test status
Simulation time 175160977 ps
CPU time 2.58 seconds
Started Aug 16 06:22:57 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 220720 kb
Host smart-a75c7e7c-c56a-4a98-a3e7-bda89a978c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108396567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.108396567
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.864218688
Short name T457
Test name
Test status
Simulation time 68742740 ps
CPU time 1.1 seconds
Started Aug 16 06:22:35 PM PDT 24
Finished Aug 16 06:22:36 PM PDT 24
Peak memory 218576 kb
Host smart-2a0fa191-d9c4-4642-99da-a80b79e0a5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864218688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.864218688
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.2533565112
Short name T645
Test name
Test status
Simulation time 37767413 ps
CPU time 1.1 seconds
Started Aug 16 06:22:49 PM PDT 24
Finished Aug 16 06:22:50 PM PDT 24
Peak memory 219192 kb
Host smart-8e719ad1-6b58-4a30-9474-4597c44c0a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533565112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.2533565112
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.511118163
Short name T12
Test name
Test status
Simulation time 40267461 ps
CPU time 1.87 seconds
Started Aug 16 06:22:39 PM PDT 24
Finished Aug 16 06:22:41 PM PDT 24
Peak memory 220388 kb
Host smart-84b8a116-3a46-4ec6-b3a1-c7993d0d9149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511118163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.511118163
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.515901703
Short name T678
Test name
Test status
Simulation time 79753368 ps
CPU time 1.1 seconds
Started Aug 16 06:22:34 PM PDT 24
Finished Aug 16 06:22:35 PM PDT 24
Peak memory 219744 kb
Host smart-27e84f8f-f8e3-4456-befd-d4a8666e3e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515901703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.515901703
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.1840908055
Short name T533
Test name
Test status
Simulation time 101740530 ps
CPU time 1.18 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:22:59 PM PDT 24
Peak memory 217392 kb
Host smart-512b3fc0-e4bd-4cf0-a064-894ad5cb446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840908055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1840908055
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.402238291
Short name T603
Test name
Test status
Simulation time 122465930 ps
CPU time 1.34 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 218492 kb
Host smart-e960abda-a0ca-44e9-9981-c80da993b6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402238291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.402238291
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.1980755519
Short name T965
Test name
Test status
Simulation time 37594091 ps
CPU time 1.58 seconds
Started Aug 16 06:22:54 PM PDT 24
Finished Aug 16 06:22:56 PM PDT 24
Peak memory 218752 kb
Host smart-8eddc6ba-f3cc-494a-8739-00b640233c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980755519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1980755519
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2307097086
Short name T606
Test name
Test status
Simulation time 109586890 ps
CPU time 1.01 seconds
Started Aug 16 06:22:36 PM PDT 24
Finished Aug 16 06:22:37 PM PDT 24
Peak memory 217548 kb
Host smart-5260aafb-0393-42a1-a9a2-a01ae7474417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307097086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2307097086
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.775908620
Short name T134
Test name
Test status
Simulation time 29382294 ps
CPU time 1.26 seconds
Started Aug 16 06:21:14 PM PDT 24
Finished Aug 16 06:21:16 PM PDT 24
Peak memory 218708 kb
Host smart-d84bffc8-ecb5-4374-bdb8-7dc6148e42b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775908620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.775908620
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.715955509
Short name T339
Test name
Test status
Simulation time 119426786 ps
CPU time 1.06 seconds
Started Aug 16 06:21:26 PM PDT 24
Finished Aug 16 06:21:27 PM PDT 24
Peak memory 206904 kb
Host smart-8da06b54-06f8-4c02-9403-c691ffe5c51f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715955509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.715955509
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1444681055
Short name T815
Test name
Test status
Simulation time 12161180 ps
CPU time 0.92 seconds
Started Aug 16 06:21:17 PM PDT 24
Finished Aug 16 06:21:18 PM PDT 24
Peak memory 215428 kb
Host smart-ca51a5bf-03b3-49b7-a23f-409544e4ccda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444681055 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1444681055
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.1784770967
Short name T191
Test name
Test status
Simulation time 23205935 ps
CPU time 0.95 seconds
Started Aug 16 06:21:18 PM PDT 24
Finished Aug 16 06:21:19 PM PDT 24
Peak memory 218496 kb
Host smart-7d69c5a2-fb51-4282-aebd-9a205fea77fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784770967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1784770967
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3290561749
Short name T657
Test name
Test status
Simulation time 77322147 ps
CPU time 1.56 seconds
Started Aug 16 06:21:15 PM PDT 24
Finished Aug 16 06:21:17 PM PDT 24
Peak memory 218652 kb
Host smart-41e31f44-9f72-4b32-8db9-627bd067d742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290561749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3290561749
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.83258947
Short name T588
Test name
Test status
Simulation time 37192051 ps
CPU time 0.95 seconds
Started Aug 16 06:21:21 PM PDT 24
Finished Aug 16 06:21:22 PM PDT 24
Peak memory 215396 kb
Host smart-6a40d2d2-8435-4c92-b4b8-18e94116ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83258947 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.83258947
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1770261877
Short name T914
Test name
Test status
Simulation time 1813387324 ps
CPU time 4.07 seconds
Started Aug 16 06:21:13 PM PDT 24
Finished Aug 16 06:21:17 PM PDT 24
Peak memory 217256 kb
Host smart-93b596c6-ddcb-4a7d-a43a-544457939f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770261877 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1770261877
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_alert.3210869018
Short name T212
Test name
Test status
Simulation time 74480150 ps
CPU time 1.21 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 220448 kb
Host smart-6da4e043-96d5-45b2-afc4-bf26b6503afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210869018 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3210869018
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.1554474327
Short name T496
Test name
Test status
Simulation time 35913702 ps
CPU time 1.29 seconds
Started Aug 16 06:22:53 PM PDT 24
Finished Aug 16 06:22:54 PM PDT 24
Peak memory 217452 kb
Host smart-bfd701ce-859d-421f-bbcb-f4a6ef74f213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554474327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1554474327
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.1715724867
Short name T126
Test name
Test status
Simulation time 128980636 ps
CPU time 1.27 seconds
Started Aug 16 06:23:00 PM PDT 24
Finished Aug 16 06:23:02 PM PDT 24
Peak memory 220280 kb
Host smart-edcbc9ab-c0ba-422e-b27f-d34ccde7ca12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715724867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.1715724867
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/132.edn_alert.912861213
Short name T917
Test name
Test status
Simulation time 39390104 ps
CPU time 1.26 seconds
Started Aug 16 06:22:52 PM PDT 24
Finished Aug 16 06:22:53 PM PDT 24
Peak memory 221600 kb
Host smart-47419153-75ff-49a7-8dd7-96ea0b749067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912861213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.912861213
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.2900549953
Short name T581
Test name
Test status
Simulation time 75570651 ps
CPU time 1.5 seconds
Started Aug 16 06:22:56 PM PDT 24
Finished Aug 16 06:22:57 PM PDT 24
Peak memory 218952 kb
Host smart-4093d744-c3a3-4c81-8608-388585aef288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900549953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2900549953
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.1290402634
Short name T268
Test name
Test status
Simulation time 29490142 ps
CPU time 1.41 seconds
Started Aug 16 06:22:49 PM PDT 24
Finished Aug 16 06:22:50 PM PDT 24
Peak memory 220008 kb
Host smart-676d1064-9a2c-471c-a023-48bb74b30e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290402634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.1290402634
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/133.edn_genbits.1310346478
Short name T504
Test name
Test status
Simulation time 56941128 ps
CPU time 1.35 seconds
Started Aug 16 06:22:46 PM PDT 24
Finished Aug 16 06:22:47 PM PDT 24
Peak memory 218700 kb
Host smart-2d164232-d488-4cc0-8f76-621248e86b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310346478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1310346478
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_alert.1647020254
Short name T172
Test name
Test status
Simulation time 188607893 ps
CPU time 1.16 seconds
Started Aug 16 06:22:48 PM PDT 24
Finished Aug 16 06:22:49 PM PDT 24
Peak memory 218472 kb
Host smart-ead46f91-ab44-4233-b2b5-4821959ef054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647020254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.1647020254
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3854738199
Short name T315
Test name
Test status
Simulation time 71497012 ps
CPU time 1.1 seconds
Started Aug 16 06:22:52 PM PDT 24
Finished Aug 16 06:22:53 PM PDT 24
Peak memory 217536 kb
Host smart-835f250c-b90c-4433-9bfe-8cb25a8e93bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854738199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3854738199
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_alert.3574225266
Short name T74
Test name
Test status
Simulation time 100925829 ps
CPU time 1.27 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 219760 kb
Host smart-3611c4a2-47db-4a95-a688-92eb95b87a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574225266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.3574225266
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/135.edn_genbits.338360745
Short name T630
Test name
Test status
Simulation time 113736242 ps
CPU time 1.15 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 215508 kb
Host smart-14c2be94-9fce-4ff5-bc58-bb1ab92b9427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338360745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.338360745
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1339480380
Short name T102
Test name
Test status
Simulation time 35439026 ps
CPU time 1.1 seconds
Started Aug 16 06:22:50 PM PDT 24
Finished Aug 16 06:22:51 PM PDT 24
Peak memory 219984 kb
Host smart-f29117e0-972f-4a36-85ab-de091a26d3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339480380 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1339480380
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.2552230541
Short name T233
Test name
Test status
Simulation time 57630127 ps
CPU time 1.36 seconds
Started Aug 16 06:22:50 PM PDT 24
Finished Aug 16 06:22:52 PM PDT 24
Peak memory 218888 kb
Host smart-587e4976-1da6-434b-bcac-a3b747470390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552230541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2552230541
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.3769626784
Short name T574
Test name
Test status
Simulation time 39293286 ps
CPU time 1.08 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 218464 kb
Host smart-12fdb19a-48d1-48e1-b620-90a8f4a22889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769626784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.3769626784
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2844018010
Short name T472
Test name
Test status
Simulation time 64644895 ps
CPU time 0.97 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 217204 kb
Host smart-4aab6b33-7c8e-495e-b961-adbb83ccfabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844018010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2844018010
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.198465521
Short name T481
Test name
Test status
Simulation time 36172754 ps
CPU time 1.16 seconds
Started Aug 16 06:22:50 PM PDT 24
Finished Aug 16 06:22:51 PM PDT 24
Peak memory 218796 kb
Host smart-1be368ce-0633-4ba3-94c5-345334413112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198465521 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.198465521
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.2497495964
Short name T840
Test name
Test status
Simulation time 79900119 ps
CPU time 1.32 seconds
Started Aug 16 06:22:49 PM PDT 24
Finished Aug 16 06:22:51 PM PDT 24
Peak memory 218828 kb
Host smart-0c4a98ad-d92e-4286-868e-9ab824338ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497495964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2497495964
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.1249135756
Short name T910
Test name
Test status
Simulation time 88186083 ps
CPU time 1.35 seconds
Started Aug 16 06:23:00 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 219968 kb
Host smart-00423b7c-0456-4329-991e-05d43f18c2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249135756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.1249135756
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3206576142
Short name T443
Test name
Test status
Simulation time 20025696 ps
CPU time 1.13 seconds
Started Aug 16 06:21:16 PM PDT 24
Finished Aug 16 06:21:17 PM PDT 24
Peak memory 215120 kb
Host smart-42a0e551-4a97-4d52-a026-f85e0a7332c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206576142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3206576142
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3245697965
Short name T849
Test name
Test status
Simulation time 11011393 ps
CPU time 0.89 seconds
Started Aug 16 06:21:28 PM PDT 24
Finished Aug 16 06:21:29 PM PDT 24
Peak memory 215184 kb
Host smart-2aca830d-bb34-4ee9-98bb-dd7d9d8a8020
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245697965 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3245697965
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.3993911647
Short name T142
Test name
Test status
Simulation time 35012688 ps
CPU time 1.22 seconds
Started Aug 16 06:21:14 PM PDT 24
Finished Aug 16 06:21:15 PM PDT 24
Peak memory 229796 kb
Host smart-86e8f210-6093-428c-a178-81c659cddd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993911647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3993911647
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3014415332
Short name T843
Test name
Test status
Simulation time 23778089 ps
CPU time 1.26 seconds
Started Aug 16 06:21:17 PM PDT 24
Finished Aug 16 06:21:18 PM PDT 24
Peak memory 219744 kb
Host smart-c1800bef-f8f5-4acb-8cb7-3e6ecfe304d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014415332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3014415332
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.167123356
Short name T469
Test name
Test status
Simulation time 59405282 ps
CPU time 0.83 seconds
Started Aug 16 06:21:24 PM PDT 24
Finished Aug 16 06:21:25 PM PDT 24
Peak memory 215484 kb
Host smart-85c6e76e-de60-4a70-9c76-3a73d467cfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167123356 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.167123356
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1516025489
Short name T340
Test name
Test status
Simulation time 17928513 ps
CPU time 1.03 seconds
Started Aug 16 06:21:24 PM PDT 24
Finished Aug 16 06:21:25 PM PDT 24
Peak memory 215320 kb
Host smart-9cd8c8d8-7cc5-4bd2-abe5-91b85a013a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516025489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1516025489
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3984732580
Short name T236
Test name
Test status
Simulation time 1836952180 ps
CPU time 4.78 seconds
Started Aug 16 06:21:32 PM PDT 24
Finished Aug 16 06:21:36 PM PDT 24
Peak memory 215312 kb
Host smart-b5f579af-a099-422e-b5fc-67907657b66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984732580 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3984732580
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_alert.4104210654
Short name T735
Test name
Test status
Simulation time 30687613 ps
CPU time 1.12 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 218748 kb
Host smart-b47277d5-cd21-40a4-8250-f2b1b77894a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104210654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.4104210654
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3540911615
Short name T739
Test name
Test status
Simulation time 29758537 ps
CPU time 1.48 seconds
Started Aug 16 06:22:51 PM PDT 24
Finished Aug 16 06:22:52 PM PDT 24
Peak memory 218568 kb
Host smart-5427b722-2319-4341-98db-84d4a08e829e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540911615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3540911615
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.1493815688
Short name T425
Test name
Test status
Simulation time 144017889 ps
CPU time 1.1 seconds
Started Aug 16 06:22:48 PM PDT 24
Finished Aug 16 06:22:49 PM PDT 24
Peak memory 218644 kb
Host smart-fad03d82-f1a4-4fc9-9e15-e6f56a781a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493815688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.1493815688
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.852980996
Short name T641
Test name
Test status
Simulation time 35184029 ps
CPU time 1.29 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 217376 kb
Host smart-72a3589f-e164-43a6-84dc-b667ec371070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852980996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.852980996
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2923818279
Short name T20
Test name
Test status
Simulation time 24211234 ps
CPU time 1.21 seconds
Started Aug 16 06:22:52 PM PDT 24
Finished Aug 16 06:22:54 PM PDT 24
Peak memory 218788 kb
Host smart-0de121af-6a47-4255-9dae-41953ebea2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923818279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2923818279
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.1378224320
Short name T781
Test name
Test status
Simulation time 124135336 ps
CPU time 1.3 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 217584 kb
Host smart-6f77d31a-0e57-4e51-bae2-78213201ee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378224320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1378224320
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.1322797885
Short name T667
Test name
Test status
Simulation time 80356147 ps
CPU time 1.19 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 219236 kb
Host smart-26b5bd6a-2d19-4a6c-903f-2d6c82a0239c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322797885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.1322797885
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.2195996992
Short name T534
Test name
Test status
Simulation time 40371708 ps
CPU time 1.52 seconds
Started Aug 16 06:22:47 PM PDT 24
Finished Aug 16 06:22:49 PM PDT 24
Peak memory 218596 kb
Host smart-c0ec0acc-9cc5-4d66-9499-21019259a072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195996992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2195996992
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.2432879280
Short name T293
Test name
Test status
Simulation time 46378228 ps
CPU time 1.26 seconds
Started Aug 16 06:22:52 PM PDT 24
Finished Aug 16 06:22:54 PM PDT 24
Peak memory 219908 kb
Host smart-735436d3-fa09-4046-98a1-fdadf2a2b9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432879280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.2432879280
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.2295380292
Short name T80
Test name
Test status
Simulation time 32982033 ps
CPU time 1.41 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 218844 kb
Host smart-1777bfb6-aebb-4049-94bb-50f41a007605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295380292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2295380292
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.843179356
Short name T507
Test name
Test status
Simulation time 28361219 ps
CPU time 1.27 seconds
Started Aug 16 06:23:00 PM PDT 24
Finished Aug 16 06:23:02 PM PDT 24
Peak memory 219812 kb
Host smart-dedd4621-331f-4973-8a3a-b3a85a8423ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843179356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.843179356
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.849325293
Short name T463
Test name
Test status
Simulation time 74985144 ps
CPU time 1.16 seconds
Started Aug 16 06:22:49 PM PDT 24
Finished Aug 16 06:22:51 PM PDT 24
Peak memory 220496 kb
Host smart-7571cb3f-9ca7-446b-8edb-0a4a3a92329b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849325293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.849325293
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.4244153931
Short name T975
Test name
Test status
Simulation time 30024351 ps
CPU time 1.35 seconds
Started Aug 16 06:22:50 PM PDT 24
Finished Aug 16 06:22:51 PM PDT 24
Peak memory 220492 kb
Host smart-6583f00e-f9df-49bf-bbca-420d5ee478f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244153931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.4244153931
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/148.edn_alert.782852178
Short name T932
Test name
Test status
Simulation time 61934051 ps
CPU time 1.16 seconds
Started Aug 16 06:22:49 PM PDT 24
Finished Aug 16 06:22:50 PM PDT 24
Peak memory 218568 kb
Host smart-525120b2-d735-4b8c-b15e-4303fcd855bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782852178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.782852178
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.3742923861
Short name T542
Test name
Test status
Simulation time 34202021 ps
CPU time 1.42 seconds
Started Aug 16 06:22:49 PM PDT 24
Finished Aug 16 06:22:51 PM PDT 24
Peak memory 218560 kb
Host smart-0b47a943-1fee-429d-ae94-65e3cd5a9dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742923861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3742923861
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.559256447
Short name T640
Test name
Test status
Simulation time 72328452 ps
CPU time 1.2 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218792 kb
Host smart-f5fc4988-01ad-49f4-b1fb-348b136c7b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559256447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.559256447
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.830998126
Short name T865
Test name
Test status
Simulation time 137391714 ps
CPU time 1.36 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:09 PM PDT 24
Peak memory 218680 kb
Host smart-c6d49ed5-c374-4ab2-af39-51da69427bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830998126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.830998126
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1557721542
Short name T471
Test name
Test status
Simulation time 39753284 ps
CPU time 1.17 seconds
Started Aug 16 06:21:22 PM PDT 24
Finished Aug 16 06:21:24 PM PDT 24
Peak memory 219472 kb
Host smart-e2580aa2-f6ce-4903-9123-d029d4791ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557721542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1557721542
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.1830622447
Short name T490
Test name
Test status
Simulation time 22229539 ps
CPU time 0.91 seconds
Started Aug 16 06:21:14 PM PDT 24
Finished Aug 16 06:21:16 PM PDT 24
Peak memory 206724 kb
Host smart-6c9a5799-e98e-42d0-8505-c70b46be27e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830622447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1830622447
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3608327952
Short name T847
Test name
Test status
Simulation time 32415561 ps
CPU time 1.18 seconds
Started Aug 16 06:21:27 PM PDT 24
Finished Aug 16 06:21:28 PM PDT 24
Peak memory 218432 kb
Host smart-fb9cf8cf-0bf6-43c9-9e9b-4aea643433e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608327952 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3608327952
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_intr.323031990
Short name T937
Test name
Test status
Simulation time 22616660 ps
CPU time 1.12 seconds
Started Aug 16 06:21:17 PM PDT 24
Finished Aug 16 06:21:18 PM PDT 24
Peak memory 215916 kb
Host smart-efe56606-1c1b-46c0-b7b1-6695a27eea5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323031990 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.323031990
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2937108113
Short name T684
Test name
Test status
Simulation time 34544862 ps
CPU time 1.01 seconds
Started Aug 16 06:21:18 PM PDT 24
Finished Aug 16 06:21:19 PM PDT 24
Peak memory 215376 kb
Host smart-2a6e9cce-ccb2-440c-8336-b5b231754e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937108113 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2937108113
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.960292996
Short name T415
Test name
Test status
Simulation time 99518152 ps
CPU time 2.41 seconds
Started Aug 16 06:21:32 PM PDT 24
Finished Aug 16 06:21:35 PM PDT 24
Peak memory 215416 kb
Host smart-961265ba-428d-4e98-a7d6-823bf8aa3f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960292996 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.960292996
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.158662361
Short name T863
Test name
Test status
Simulation time 7777487527 ps
CPU time 106.91 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:23:19 PM PDT 24
Peak memory 217892 kb
Host smart-11d71afa-14be-4219-b265-297137d4c43f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158662361 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.158662361
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.1048928087
Short name T518
Test name
Test status
Simulation time 46332902 ps
CPU time 1.24 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 219864 kb
Host smart-42cb1780-b917-4feb-ac20-9d7dc19ca4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048928087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.1048928087
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.1965492058
Short name T926
Test name
Test status
Simulation time 177818289 ps
CPU time 1.71 seconds
Started Aug 16 06:22:55 PM PDT 24
Finished Aug 16 06:22:57 PM PDT 24
Peak memory 219100 kb
Host smart-39a16a72-f823-407a-a64a-53d27ba0766a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965492058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1965492058
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.676413873
Short name T825
Test name
Test status
Simulation time 40503563 ps
CPU time 1.06 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 220340 kb
Host smart-c6dbca56-fa6b-4f45-bac0-66571df753e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676413873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.676413873
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3128473805
Short name T774
Test name
Test status
Simulation time 22937643 ps
CPU time 1.15 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 219920 kb
Host smart-60e11f19-ef2d-40ed-9ba2-e30ebefbdceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128473805 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3128473805
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.3542989976
Short name T895
Test name
Test status
Simulation time 42193909 ps
CPU time 1.41 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:06 PM PDT 24
Peak memory 217328 kb
Host smart-9df9e9c0-ebd6-45c3-a2cf-3ae4d760c792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542989976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3542989976
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.2132999259
Short name T522
Test name
Test status
Simulation time 61001978 ps
CPU time 1.17 seconds
Started Aug 16 06:23:00 PM PDT 24
Finished Aug 16 06:23:02 PM PDT 24
Peak memory 221076 kb
Host smart-4deb3e5b-eae8-45a5-a2c1-7213d3793a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132999259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.2132999259
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.2981282902
Short name T405
Test name
Test status
Simulation time 51450725 ps
CPU time 1.21 seconds
Started Aug 16 06:23:05 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 217256 kb
Host smart-0ea733fd-73b4-4fd9-a9c4-4ee35207a1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981282902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2981282902
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.2493517963
Short name T656
Test name
Test status
Simulation time 29696518 ps
CPU time 1.28 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 218596 kb
Host smart-ba206f66-ae79-4d4e-a7bf-f2bf77aeeabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493517963 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.2493517963
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.898149419
Short name T892
Test name
Test status
Simulation time 49725739 ps
CPU time 1.2 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:09 PM PDT 24
Peak memory 217524 kb
Host smart-9270c245-1200-4d0f-a4df-78cb44fcd81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898149419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.898149419
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.627676884
Short name T209
Test name
Test status
Simulation time 90488157 ps
CPU time 1.29 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218608 kb
Host smart-89d2a834-2d44-4be8-8a2b-11351a37d518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627676884 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.627676884
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/155.edn_genbits.2434254096
Short name T891
Test name
Test status
Simulation time 61811421 ps
CPU time 1.69 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 218540 kb
Host smart-da9053e5-8e26-438c-af5b-535c42b31bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434254096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2434254096
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_alert.679320553
Short name T245
Test name
Test status
Simulation time 60798256 ps
CPU time 1.31 seconds
Started Aug 16 06:22:57 PM PDT 24
Finished Aug 16 06:22:58 PM PDT 24
Peak memory 219860 kb
Host smart-c68622b1-2d50-4af4-8ce2-2e298a8f4f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679320553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.679320553
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.168049
Short name T75
Test name
Test status
Simulation time 64994532 ps
CPU time 1.05 seconds
Started Aug 16 06:23:06 PM PDT 24
Finished Aug 16 06:23:07 PM PDT 24
Peak memory 217280 kb
Host smart-7a91cbe4-568b-4908-b1f1-405ccc8c4910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.168049
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.4105104024
Short name T673
Test name
Test status
Simulation time 322005234 ps
CPU time 1.06 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:09 PM PDT 24
Peak memory 218820 kb
Host smart-471658cd-5827-43b6-b9ec-dea486249118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105104024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.4105104024
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.2597227498
Short name T379
Test name
Test status
Simulation time 92554720 ps
CPU time 1.08 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 217308 kb
Host smart-f6d73d5b-8019-4dd8-a960-3a277f3acf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597227498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2597227498
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_alert.3704100445
Short name T560
Test name
Test status
Simulation time 86844026 ps
CPU time 1.16 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 220892 kb
Host smart-f34b92d4-bcfe-4889-882b-caa4a99f7fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704100445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.3704100445
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/158.edn_genbits.3035089096
Short name T776
Test name
Test status
Simulation time 111544447 ps
CPU time 1.42 seconds
Started Aug 16 06:22:54 PM PDT 24
Finished Aug 16 06:22:56 PM PDT 24
Peak memory 220296 kb
Host smart-30c785bc-4d19-46ae-a4db-058b95c35e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035089096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3035089096
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.2654470943
Short name T155
Test name
Test status
Simulation time 27682451 ps
CPU time 1.31 seconds
Started Aug 16 06:23:32 PM PDT 24
Finished Aug 16 06:23:33 PM PDT 24
Peak memory 219992 kb
Host smart-79ac764d-f812-4716-93c4-20ab12801b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654470943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.2654470943
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.1247404692
Short name T734
Test name
Test status
Simulation time 53780220 ps
CPU time 1.11 seconds
Started Aug 16 06:23:26 PM PDT 24
Finished Aug 16 06:23:27 PM PDT 24
Peak memory 217488 kb
Host smart-fe86ff81-dd15-42be-a9e1-f20541bb2cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247404692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1247404692
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1918396231
Short name T447
Test name
Test status
Simulation time 26242515 ps
CPU time 1.22 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:33 PM PDT 24
Peak memory 220668 kb
Host smart-2919c004-9aef-4b3f-a8d1-5df0fafb82a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918396231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1918396231
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3940515833
Short name T701
Test name
Test status
Simulation time 36490278 ps
CPU time 1.24 seconds
Started Aug 16 06:21:35 PM PDT 24
Finished Aug 16 06:21:36 PM PDT 24
Peak memory 215100 kb
Host smart-4103bf9f-7ee1-4ffc-970e-a4c109eba0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940515833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3940515833
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3002026924
Short name T700
Test name
Test status
Simulation time 50513519 ps
CPU time 0.84 seconds
Started Aug 16 06:21:22 PM PDT 24
Finished Aug 16 06:21:23 PM PDT 24
Peak memory 215480 kb
Host smart-104f7076-83cd-4bc0-9630-68905cb73919
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002026924 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3002026924
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.4196147543
Short name T128
Test name
Test status
Simulation time 57896921 ps
CPU time 1.14 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 218448 kb
Host smart-9380a5a1-358f-4d9b-bb06-6f63a24b6fe1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196147543 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.4196147543
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.294853445
Short name T162
Test name
Test status
Simulation time 45401111 ps
CPU time 0.84 seconds
Started Aug 16 06:21:21 PM PDT 24
Finished Aug 16 06:21:22 PM PDT 24
Peak memory 218240 kb
Host smart-f471a220-a2b7-4599-830f-241e6dfbeb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294853445 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.294853445
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3613221380
Short name T224
Test name
Test status
Simulation time 64111525 ps
CPU time 1.31 seconds
Started Aug 16 06:21:17 PM PDT 24
Finished Aug 16 06:21:18 PM PDT 24
Peak memory 218528 kb
Host smart-f25bbbb9-3fed-49d5-b3cd-57344854d25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613221380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3613221380
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2462778175
Short name T50
Test name
Test status
Simulation time 31455949 ps
CPU time 1.05 seconds
Started Aug 16 06:21:28 PM PDT 24
Finished Aug 16 06:21:29 PM PDT 24
Peak memory 224340 kb
Host smart-a859d2dd-e6cb-4ba1-9ad9-f60c434d3404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462778175 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2462778175
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1540606729
Short name T64
Test name
Test status
Simulation time 18019625 ps
CPU time 0.94 seconds
Started Aug 16 06:21:22 PM PDT 24
Finished Aug 16 06:21:23 PM PDT 24
Peak memory 215336 kb
Host smart-74700c91-11c8-4919-b849-8097284f490a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540606729 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1540606729
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1228640683
Short name T791
Test name
Test status
Simulation time 1760708288 ps
CPU time 4.2 seconds
Started Aug 16 06:21:22 PM PDT 24
Finished Aug 16 06:21:26 PM PDT 24
Peak memory 215316 kb
Host smart-0c267c69-3886-44b1-b5a5-14e4ea697f87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228640683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1228640683
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3641874658
Short name T98
Test name
Test status
Simulation time 16963885563 ps
CPU time 102.55 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:23:16 PM PDT 24
Peak memory 218140 kb
Host smart-27184757-1f04-43b3-a545-64969a59669d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641874658 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3641874658
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_alert.3495714208
Short name T103
Test name
Test status
Simulation time 40617553 ps
CPU time 1.48 seconds
Started Aug 16 06:22:57 PM PDT 24
Finished Aug 16 06:22:58 PM PDT 24
Peak memory 220520 kb
Host smart-aa214ef6-6712-459d-aab9-dc7750b245da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495714208 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3495714208
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.2459008719
Short name T416
Test name
Test status
Simulation time 316184680 ps
CPU time 1.38 seconds
Started Aug 16 06:22:56 PM PDT 24
Finished Aug 16 06:22:58 PM PDT 24
Peak memory 217420 kb
Host smart-7010d1da-1121-49a1-868e-e26f5f8086aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459008719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2459008719
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.710805752
Short name T514
Test name
Test status
Simulation time 65171389 ps
CPU time 1.2 seconds
Started Aug 16 06:23:29 PM PDT 24
Finished Aug 16 06:23:30 PM PDT 24
Peak memory 216884 kb
Host smart-0c85a143-9773-4b7d-95b8-c0784b93aff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710805752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.710805752
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/162.edn_alert.806249531
Short name T99
Test name
Test status
Simulation time 31617892 ps
CPU time 1.2 seconds
Started Aug 16 06:22:57 PM PDT 24
Finished Aug 16 06:22:58 PM PDT 24
Peak memory 220040 kb
Host smart-39dd2f0c-90f2-44b1-94b2-1120fb5d8e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806249531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.806249531
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.3418340422
Short name T69
Test name
Test status
Simulation time 222374830 ps
CPU time 1.08 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 217360 kb
Host smart-c18f212d-a353-4339-bce1-4914044523db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418340422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3418340422
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.220073450
Short name T184
Test name
Test status
Simulation time 78775574 ps
CPU time 1.21 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:02 PM PDT 24
Peak memory 220200 kb
Host smart-a2ffe444-d4d8-45d4-9c7f-f07cd425fefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220073450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.220073450
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.456018049
Short name T790
Test name
Test status
Simulation time 39547935 ps
CPU time 1.68 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:09 PM PDT 24
Peak memory 217700 kb
Host smart-d5780c51-6e3e-4802-8e62-f99a9380e802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456018049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.456018049
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.1328947554
Short name T841
Test name
Test status
Simulation time 294053554 ps
CPU time 1.2 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:08 PM PDT 24
Peak memory 215796 kb
Host smart-e27b3d70-c7d8-4690-8624-dc269a0fcfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328947554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.1328947554
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.1120257802
Short name T373
Test name
Test status
Simulation time 41860103 ps
CPU time 1.39 seconds
Started Aug 16 06:22:56 PM PDT 24
Finished Aug 16 06:22:58 PM PDT 24
Peak memory 218456 kb
Host smart-c3f75bd6-a3fe-4d94-b755-6fdf02b001ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120257802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1120257802
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.2786279302
Short name T213
Test name
Test status
Simulation time 25969235 ps
CPU time 1.19 seconds
Started Aug 16 06:22:54 PM PDT 24
Finished Aug 16 06:22:55 PM PDT 24
Peak memory 220044 kb
Host smart-f77527cc-ca82-49c3-a228-9bc4651d8a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786279302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.2786279302
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1284574155
Short name T633
Test name
Test status
Simulation time 1186096181 ps
CPU time 9.01 seconds
Started Aug 16 06:23:05 PM PDT 24
Finished Aug 16 06:23:14 PM PDT 24
Peak memory 217692 kb
Host smart-2354583b-4f58-4c12-b327-9c426c50b879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284574155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1284574155
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.903719182
Short name T177
Test name
Test status
Simulation time 98844336 ps
CPU time 1.27 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:08 PM PDT 24
Peak memory 215764 kb
Host smart-541e7999-0985-467c-ab86-55b2615c59e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903719182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.903719182
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.464502104
Short name T305
Test name
Test status
Simulation time 46652725 ps
CPU time 1.22 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 217340 kb
Host smart-5ef04d88-c9fb-4ba5-aa58-08c3065faee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464502104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.464502104
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.262596650
Short name T73
Test name
Test status
Simulation time 27634156 ps
CPU time 1.25 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 218920 kb
Host smart-50b0c64d-a98e-4165-b004-843bfb75f476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262596650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.262596650
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/167.edn_genbits.2917794193
Short name T924
Test name
Test status
Simulation time 30720734 ps
CPU time 1.26 seconds
Started Aug 16 06:23:27 PM PDT 24
Finished Aug 16 06:23:29 PM PDT 24
Peak memory 217464 kb
Host smart-e371e01f-dbaa-40f7-803a-7a850076d104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917794193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2917794193
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.414135757
Short name T872
Test name
Test status
Simulation time 91308792 ps
CPU time 1.04 seconds
Started Aug 16 06:22:56 PM PDT 24
Finished Aug 16 06:22:57 PM PDT 24
Peak memory 218496 kb
Host smart-e933892c-c759-4a40-94d7-37bbcc193dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414135757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.414135757
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.436209407
Short name T359
Test name
Test status
Simulation time 49283587 ps
CPU time 1.55 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 218692 kb
Host smart-67e41805-5fbd-41b6-a0ab-007f7a6d11c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436209407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.436209407
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.3637965926
Short name T537
Test name
Test status
Simulation time 43134988 ps
CPU time 1.17 seconds
Started Aug 16 06:23:17 PM PDT 24
Finished Aug 16 06:23:18 PM PDT 24
Peak memory 219816 kb
Host smart-e3f5217c-9a68-49f8-9a72-a3b0bb580ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637965926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.3637965926
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.615242357
Short name T33
Test name
Test status
Simulation time 53680017 ps
CPU time 1.23 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:02 PM PDT 24
Peak memory 217332 kb
Host smart-fb2a14ce-31c8-4d68-a1b6-638f2b6f9d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615242357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.615242357
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3387535622
Short name T899
Test name
Test status
Simulation time 31970782 ps
CPU time 1.34 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:33 PM PDT 24
Peak memory 215704 kb
Host smart-b263d314-3f18-4a7d-b9fa-cff57f9b2e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387535622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3387535622
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2153069951
Short name T528
Test name
Test status
Simulation time 52457404 ps
CPU time 0.86 seconds
Started Aug 16 06:21:28 PM PDT 24
Finished Aug 16 06:21:29 PM PDT 24
Peak memory 214976 kb
Host smart-4f9a1db5-f71f-4bcf-a4ea-980da3273cd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153069951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2153069951
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3176277716
Short name T113
Test name
Test status
Simulation time 137882424 ps
CPU time 1.16 seconds
Started Aug 16 06:21:26 PM PDT 24
Finished Aug 16 06:21:27 PM PDT 24
Peak memory 217120 kb
Host smart-32146425-62ce-4ccf-b845-3c24b97e458a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176277716 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3176277716
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2435006886
Short name T492
Test name
Test status
Simulation time 30756127 ps
CPU time 0.91 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:34 PM PDT 24
Peak memory 218572 kb
Host smart-26f88b9b-28b2-4f80-a961-cf149bdbe57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435006886 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2435006886
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1809393609
Short name T818
Test name
Test status
Simulation time 39365417 ps
CPU time 1.43 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 218720 kb
Host smart-abd8fa0c-61cc-43ba-b959-50cba0ea1fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809393609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1809393609
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.4215525577
Short name T548
Test name
Test status
Simulation time 20070845 ps
CPU time 1.09 seconds
Started Aug 16 06:21:32 PM PDT 24
Finished Aug 16 06:21:34 PM PDT 24
Peak memory 215800 kb
Host smart-168c74f9-7544-47d3-a678-94aac81f9c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215525577 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.4215525577
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.632219909
Short name T600
Test name
Test status
Simulation time 149633062 ps
CPU time 0.93 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:34 PM PDT 24
Peak memory 215364 kb
Host smart-7ab94b04-741c-470b-8981-e3d4e700c66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632219909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.632219909
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1096874942
Short name T63
Test name
Test status
Simulation time 241946746 ps
CPU time 2.85 seconds
Started Aug 16 06:21:28 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 215356 kb
Host smart-2748ccff-1cce-4c18-a73f-caabba52c407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096874942 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1096874942
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.32592497
Short name T231
Test name
Test status
Simulation time 1265192915 ps
CPU time 29.76 seconds
Started Aug 16 06:21:32 PM PDT 24
Finished Aug 16 06:22:02 PM PDT 24
Peak memory 217652 kb
Host smart-b52ecc85-0891-44ff-8bf2-7815d2da914b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32592497 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.32592497
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.1944316382
Short name T557
Test name
Test status
Simulation time 24266913 ps
CPU time 1.2 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 219432 kb
Host smart-659cb6ee-9423-4a7f-a727-f32b098e758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944316382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.1944316382
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/170.edn_genbits.783253596
Short name T347
Test name
Test status
Simulation time 65140748 ps
CPU time 1.27 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:22:59 PM PDT 24
Peak memory 217420 kb
Host smart-4e3f302c-cc7a-4979-8a27-32e5d42c8c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783253596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.783253596
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_alert.85771729
Short name T386
Test name
Test status
Simulation time 35158873 ps
CPU time 1.36 seconds
Started Aug 16 06:23:27 PM PDT 24
Finished Aug 16 06:23:29 PM PDT 24
Peak memory 220172 kb
Host smart-985aa0f8-88d3-413c-b3be-b5dce6de9327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85771729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.85771729
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.4070240842
Short name T670
Test name
Test status
Simulation time 126445988 ps
CPU time 1.29 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 217552 kb
Host smart-ba3079c3-0bda-4b4e-b06f-a6f7355f4766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070240842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4070240842
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.3247011278
Short name T440
Test name
Test status
Simulation time 96332240 ps
CPU time 1.1 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:08 PM PDT 24
Peak memory 219692 kb
Host smart-9ec9f4e4-0d2c-48b6-b68b-2e91e4f2181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247011278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.3247011278
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3754562470
Short name T593
Test name
Test status
Simulation time 48889844 ps
CPU time 1.1 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 217156 kb
Host smart-823a70da-251e-4ec3-9ccd-a222adb227a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754562470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3754562470
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_alert.2537716890
Short name T465
Test name
Test status
Simulation time 39443578 ps
CPU time 1.15 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 220264 kb
Host smart-d7e9c2ae-5190-4356-8a76-247074d2826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537716890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.2537716890
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1647724701
Short name T712
Test name
Test status
Simulation time 158542991 ps
CPU time 2.53 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:06 PM PDT 24
Peak memory 220492 kb
Host smart-be90103d-31bb-4716-a327-4f892f1897d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647724701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1647724701
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.4278496433
Short name T141
Test name
Test status
Simulation time 57478700 ps
CPU time 1.15 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:22:59 PM PDT 24
Peak memory 218784 kb
Host smart-b3fd4feb-21ca-4cd7-a402-1b6bd0b50887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278496433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.4278496433
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.2086438142
Short name T317
Test name
Test status
Simulation time 439081778 ps
CPU time 4.03 seconds
Started Aug 16 06:23:17 PM PDT 24
Finished Aug 16 06:23:21 PM PDT 24
Peak memory 220628 kb
Host smart-b4f8c9eb-274c-49ed-bc66-f8b68bc84e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086438142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2086438142
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.2201962932
Short name T663
Test name
Test status
Simulation time 29810436 ps
CPU time 1.27 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 221144 kb
Host smart-f20ef65e-8b50-4459-8372-201c24bf114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201962932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.2201962932
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.3670685849
Short name T746
Test name
Test status
Simulation time 65415303 ps
CPU time 1.56 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 218832 kb
Host smart-336e1dcb-6c48-4ebe-bdcc-0cc21030ae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670685849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3670685849
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.3244764505
Short name T150
Test name
Test status
Simulation time 27328498 ps
CPU time 1.26 seconds
Started Aug 16 06:22:57 PM PDT 24
Finished Aug 16 06:22:58 PM PDT 24
Peak memory 219204 kb
Host smart-a8940a62-7653-40e1-ab01-cba0f2773d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244764505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.3244764505
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.869492897
Short name T748
Test name
Test status
Simulation time 36197909 ps
CPU time 1.37 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:14 PM PDT 24
Peak memory 219208 kb
Host smart-c81eea96-0d12-478f-953e-c283cac17797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869492897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.869492897
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.41843443
Short name T690
Test name
Test status
Simulation time 52791799 ps
CPU time 1.2 seconds
Started Aug 16 06:23:00 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 220880 kb
Host smart-100dd981-2bc5-41d9-ae88-08688d34f1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41843443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.41843443
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.2230509947
Short name T439
Test name
Test status
Simulation time 52988832 ps
CPU time 1.19 seconds
Started Aug 16 06:22:57 PM PDT 24
Finished Aug 16 06:22:58 PM PDT 24
Peak memory 217428 kb
Host smart-1132dcb7-f5cf-4c25-9642-d2b85daba065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230509947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2230509947
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.972494351
Short name T76
Test name
Test status
Simulation time 142162281 ps
CPU time 1.28 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 219824 kb
Host smart-d8b327da-424f-4b94-ba96-c28676276578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972494351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.972494351
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.1710080934
Short name T653
Test name
Test status
Simulation time 120882725 ps
CPU time 2.43 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 218708 kb
Host smart-07aa448a-df08-4b46-acec-f5f81cb7458c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710080934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1710080934
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.2381160260
Short name T270
Test name
Test status
Simulation time 42314926 ps
CPU time 1.18 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:22:59 PM PDT 24
Peak memory 219748 kb
Host smart-a54d0cf3-d0ec-44dd-bc1a-e403b3dcd301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381160260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.2381160260
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.2080758990
Short name T502
Test name
Test status
Simulation time 60490246 ps
CPU time 1.55 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 219472 kb
Host smart-ea651375-4d9b-4c1b-8907-3d11dd3c5fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080758990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2080758990
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.7844172
Short name T634
Test name
Test status
Simulation time 21220718 ps
CPU time 0.92 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 215112 kb
Host smart-33df6520-3746-4192-ba72-9d557258cdd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7844172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.7844172
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2836761787
Short name T860
Test name
Test status
Simulation time 17950546 ps
CPU time 0.88 seconds
Started Aug 16 06:21:22 PM PDT 24
Finished Aug 16 06:21:23 PM PDT 24
Peak memory 215392 kb
Host smart-e371855b-dcff-449d-b49a-ed919356d3e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836761787 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2836761787
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.879962321
Short name T6
Test name
Test status
Simulation time 38917677 ps
CPU time 1.05 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:34 PM PDT 24
Peak memory 229996 kb
Host smart-3c29c3e6-dde2-4c2c-b9e3-79fa01f16c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879962321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.879962321
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2825797403
Short name T960
Test name
Test status
Simulation time 44575321 ps
CPU time 1.8 seconds
Started Aug 16 06:21:23 PM PDT 24
Finished Aug 16 06:21:25 PM PDT 24
Peak memory 218608 kb
Host smart-e186397d-afc2-47db-818f-39c6c1797cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825797403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2825797403
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1508371817
Short name T370
Test name
Test status
Simulation time 38857919 ps
CPU time 0.93 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:34 PM PDT 24
Peak memory 215496 kb
Host smart-3338fc76-4183-4d95-87d9-44a587bcef83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508371817 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1508371817
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1197472473
Short name T949
Test name
Test status
Simulation time 16262643 ps
CPU time 1.06 seconds
Started Aug 16 06:21:23 PM PDT 24
Finished Aug 16 06:21:25 PM PDT 24
Peak memory 215408 kb
Host smart-404c6920-8ec0-4f89-8801-6e86fb7d1cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197472473 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1197472473
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1235121377
Short name T274
Test name
Test status
Simulation time 1109643029 ps
CPU time 3.2 seconds
Started Aug 16 06:21:28 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 217532 kb
Host smart-62fdd691-fd66-414b-9255-3be3a7786856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235121377 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1235121377
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1872580302
Short name T755
Test name
Test status
Simulation time 16318015660 ps
CPU time 96.15 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:23:09 PM PDT 24
Peak memory 219148 kb
Host smart-30e1596f-f08e-42c8-999c-04fa50676e67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872580302 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1872580302
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_alert.895373973
Short name T295
Test name
Test status
Simulation time 28424915 ps
CPU time 1.24 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 219748 kb
Host smart-c2804e13-cafd-4f3c-bdc2-e0549cd99453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895373973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.895373973
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.657721985
Short name T480
Test name
Test status
Simulation time 33667495 ps
CPU time 1.48 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 218592 kb
Host smart-a01d2f98-6efa-4992-b2cd-e955c88cb4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657721985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.657721985
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.1577949230
Short name T846
Test name
Test status
Simulation time 27118974 ps
CPU time 1.24 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 219564 kb
Host smart-a6037c44-8b84-4b6f-a11b-a097b0536983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577949230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.1577949230
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3213207560
Short name T311
Test name
Test status
Simulation time 92955167 ps
CPU time 1.23 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 217468 kb
Host smart-746669a4-3b9a-41b6-94a3-45d46b6d8c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213207560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3213207560
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.2586081585
Short name T294
Test name
Test status
Simulation time 29717220 ps
CPU time 1.28 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 215916 kb
Host smart-f927e439-f514-42cb-941b-c7a3350a5c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586081585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.2586081585
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.2798822360
Short name T35
Test name
Test status
Simulation time 267024785 ps
CPU time 3.39 seconds
Started Aug 16 06:22:57 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 220752 kb
Host smart-ff8587a5-31d3-4704-90fd-7b706cab76c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798822360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2798822360
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.415742898
Short name T446
Test name
Test status
Simulation time 49067035 ps
CPU time 1.53 seconds
Started Aug 16 06:23:05 PM PDT 24
Finished Aug 16 06:23:07 PM PDT 24
Peak memory 218428 kb
Host smart-24bf1249-e30b-4300-a3c1-224f4aeb13ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415742898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.415742898
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.4254302787
Short name T498
Test name
Test status
Simulation time 66669547 ps
CPU time 1.12 seconds
Started Aug 16 06:23:00 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 217448 kb
Host smart-9f9cbbfe-b61c-455e-98cd-0577a6edf15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254302787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.4254302787
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.1602637695
Short name T296
Test name
Test status
Simulation time 403550250 ps
CPU time 1.21 seconds
Started Aug 16 06:23:00 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 219776 kb
Host smart-802bcb3f-235d-4eb1-a9cd-15cf367a2af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602637695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.1602637695
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.3385411625
Short name T627
Test name
Test status
Simulation time 235202912 ps
CPU time 1.56 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:06 PM PDT 24
Peak memory 219448 kb
Host smart-5663d762-a71a-45e9-8270-f8a11ff97407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385411625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3385411625
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3237139449
Short name T920
Test name
Test status
Simulation time 45415954 ps
CPU time 1.23 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 219792 kb
Host smart-6aa2f861-3ce3-4536-aade-0f16faa55859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237139449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3237139449
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.4223521206
Short name T726
Test name
Test status
Simulation time 65935013 ps
CPU time 2.47 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 220668 kb
Host smart-7579cf42-26f3-49bb-a3f0-dcb65d4fd889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223521206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4223521206
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.2578237694
Short name T242
Test name
Test status
Simulation time 102770321 ps
CPU time 1.31 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 219048 kb
Host smart-114f29c7-fbf0-4ead-a7a8-8f7aaff8192b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578237694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2578237694
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.426526260
Short name T935
Test name
Test status
Simulation time 50200664 ps
CPU time 1.14 seconds
Started Aug 16 06:23:06 PM PDT 24
Finished Aug 16 06:23:08 PM PDT 24
Peak memory 217348 kb
Host smart-b1fc9ec2-ebcd-490e-85c9-a10d39bb6cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426526260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.426526260
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.1304759507
Short name T210
Test name
Test status
Simulation time 52951607 ps
CPU time 1.27 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 215764 kb
Host smart-3650d7a1-d069-49db-a65d-0603ce4c1903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304759507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.1304759507
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.521666987
Short name T572
Test name
Test status
Simulation time 28542368 ps
CPU time 1.03 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 220340 kb
Host smart-341c7516-0e06-417e-9ebd-dd1dbaf10a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521666987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.521666987
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.2918044085
Short name T71
Test name
Test status
Simulation time 48751547 ps
CPU time 1.16 seconds
Started Aug 16 06:23:29 PM PDT 24
Finished Aug 16 06:23:30 PM PDT 24
Peak memory 220188 kb
Host smart-b3ee4f32-bb23-4049-932f-805a623b8284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918044085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.2918044085
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.1316915300
Short name T720
Test name
Test status
Simulation time 31907469 ps
CPU time 1.3 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:22:59 PM PDT 24
Peak memory 218448 kb
Host smart-301280b8-42ae-4082-9bab-b27d84bace50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316915300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1316915300
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.435784318
Short name T939
Test name
Test status
Simulation time 22558841 ps
CPU time 1.1 seconds
Started Aug 16 06:21:23 PM PDT 24
Finished Aug 16 06:21:24 PM PDT 24
Peak memory 218764 kb
Host smart-22f31b9d-2041-4eaa-8f44-ad6ca3a3e00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435784318 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.435784318
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3523523537
Short name T703
Test name
Test status
Simulation time 32271289 ps
CPU time 0.88 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 206796 kb
Host smart-3d3d8af3-fabd-4225-bb6e-bf3b2a13d990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523523537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3523523537
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.717491074
Short name T714
Test name
Test status
Simulation time 10878991 ps
CPU time 0.9 seconds
Started Aug 16 06:21:20 PM PDT 24
Finished Aug 16 06:21:21 PM PDT 24
Peak memory 215448 kb
Host smart-1664519d-90b8-4ad3-9603-8be5ef25f11b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717491074 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.717491074
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3281844230
Short name T361
Test name
Test status
Simulation time 84629619 ps
CPU time 1.05 seconds
Started Aug 16 06:21:30 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 218408 kb
Host smart-edad3ca2-05bf-4eda-884b-e3bf0a4e9fd2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281844230 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3281844230
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.226021776
Short name T48
Test name
Test status
Simulation time 38499410 ps
CPU time 1.07 seconds
Started Aug 16 06:21:24 PM PDT 24
Finished Aug 16 06:21:25 PM PDT 24
Peak memory 229756 kb
Host smart-29014923-911f-4370-931f-e17c65e7078d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226021776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.226021776
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.414352344
Short name T833
Test name
Test status
Simulation time 119293513 ps
CPU time 1.37 seconds
Started Aug 16 06:21:24 PM PDT 24
Finished Aug 16 06:21:25 PM PDT 24
Peak memory 219032 kb
Host smart-1ab784d7-abd4-434d-b570-86f0b8108622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414352344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.414352344
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3356401596
Short name T589
Test name
Test status
Simulation time 26598805 ps
CPU time 1.09 seconds
Started Aug 16 06:21:29 PM PDT 24
Finished Aug 16 06:21:30 PM PDT 24
Peak memory 222780 kb
Host smart-7822fc92-3607-44bd-9616-e750c1d8b8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356401596 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3356401596
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3730828649
Short name T554
Test name
Test status
Simulation time 38564079 ps
CPU time 0.91 seconds
Started Aug 16 06:21:24 PM PDT 24
Finished Aug 16 06:21:25 PM PDT 24
Peak memory 215352 kb
Host smart-597f4198-b281-4825-b04b-d441a8572c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730828649 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3730828649
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.4156479185
Short name T897
Test name
Test status
Simulation time 38578577 ps
CPU time 1.01 seconds
Started Aug 16 06:21:25 PM PDT 24
Finished Aug 16 06:21:26 PM PDT 24
Peak memory 206492 kb
Host smart-45b391a7-041e-4ba6-b48a-251e081cfdb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156479185 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4156479185
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_alert.1432887487
Short name T728
Test name
Test status
Simulation time 55730266 ps
CPU time 1.37 seconds
Started Aug 16 06:23:24 PM PDT 24
Finished Aug 16 06:23:26 PM PDT 24
Peak memory 219936 kb
Host smart-5cfc0ee2-244a-400a-ae0e-63c65d47ccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432887487 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1432887487
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.2951498620
Short name T971
Test name
Test status
Simulation time 330688289 ps
CPU time 1.63 seconds
Started Aug 16 06:23:43 PM PDT 24
Finished Aug 16 06:23:44 PM PDT 24
Peak memory 219224 kb
Host smart-2c620b0b-75ff-4599-9637-6f58eb8161d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951498620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2951498620
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.3897739479
Short name T617
Test name
Test status
Simulation time 158111352 ps
CPU time 1.39 seconds
Started Aug 16 06:23:05 PM PDT 24
Finished Aug 16 06:23:06 PM PDT 24
Peak memory 218776 kb
Host smart-3211d9dd-97ba-459c-ba2d-b841a57a66ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897739479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.3897739479
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.33186842
Short name T622
Test name
Test status
Simulation time 104704091 ps
CPU time 1.45 seconds
Started Aug 16 06:23:06 PM PDT 24
Finished Aug 16 06:23:07 PM PDT 24
Peak memory 218872 kb
Host smart-4cdc81bc-dec6-4cad-a1b3-b764c456ab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33186842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.33186842
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.2065554928
Short name T401
Test name
Test status
Simulation time 28015450 ps
CPU time 1.27 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 218132 kb
Host smart-7196297f-3573-4dcf-970c-25f47ec2d1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065554928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.2065554928
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.1583171463
Short name T390
Test name
Test status
Simulation time 96447628 ps
CPU time 1.16 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 217372 kb
Host smart-bff3e162-9cf4-428e-983a-6e0aac7a0862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583171463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1583171463
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_alert.26951198
Short name T406
Test name
Test status
Simulation time 72234846 ps
CPU time 1.14 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 219540 kb
Host smart-322da528-6d56-458f-a8b3-e6e93e99eaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26951198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.26951198
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/193.edn_genbits.3083411572
Short name T388
Test name
Test status
Simulation time 47906163 ps
CPU time 1.2 seconds
Started Aug 16 06:23:30 PM PDT 24
Finished Aug 16 06:23:31 PM PDT 24
Peak memory 218816 kb
Host smart-9ce653a4-5827-464c-b999-8ecba83c281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083411572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3083411572
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3982964025
Short name T767
Test name
Test status
Simulation time 38018667 ps
CPU time 1.22 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 219896 kb
Host smart-b403c11d-a584-456a-985c-74e7011512cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982964025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3982964025
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3200654870
Short name T358
Test name
Test status
Simulation time 30182974 ps
CPU time 1.26 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 218384 kb
Host smart-fb4f3494-50f7-4b0e-adbe-2b852401f3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200654870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3200654870
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.2188014853
Short name T345
Test name
Test status
Simulation time 23475510 ps
CPU time 1.15 seconds
Started Aug 16 06:23:00 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 219848 kb
Host smart-1894ba0c-d134-4169-bb3f-8ab968b6b9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188014853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.2188014853
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.3019857078
Short name T41
Test name
Test status
Simulation time 37836871 ps
CPU time 1.47 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 218404 kb
Host smart-dc276b9d-4721-4589-9d1a-5371777ffaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019857078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3019857078
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_alert.1774447425
Short name T244
Test name
Test status
Simulation time 152443750 ps
CPU time 1.33 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:22:59 PM PDT 24
Peak memory 215700 kb
Host smart-913bf0bb-602b-47b2-8dbb-03b0201336f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774447425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.1774447425
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/196.edn_genbits.706114668
Short name T474
Test name
Test status
Simulation time 34904039 ps
CPU time 1.36 seconds
Started Aug 16 06:23:16 PM PDT 24
Finished Aug 16 06:23:18 PM PDT 24
Peak memory 217620 kb
Host smart-94c6c04f-e898-4ad6-a0d3-88ad0498f1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706114668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.706114668
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.1825851188
Short name T127
Test name
Test status
Simulation time 72543113 ps
CPU time 1.13 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 219748 kb
Host smart-dbf2e030-99c3-4b5b-ab1a-07cbf0999b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825851188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.1825851188
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.574296915
Short name T278
Test name
Test status
Simulation time 96598889 ps
CPU time 1.18 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:23:00 PM PDT 24
Peak memory 217308 kb
Host smart-2d5d7f36-26d7-4a94-a5cf-0d2fd80cc32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574296915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.574296915
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.3546748138
Short name T185
Test name
Test status
Simulation time 27613343 ps
CPU time 1.27 seconds
Started Aug 16 06:23:00 PM PDT 24
Finished Aug 16 06:23:02 PM PDT 24
Peak memory 215748 kb
Host smart-06d1e137-5a8b-447e-89b9-971e37488dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546748138 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.3546748138
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/199.edn_alert.2908480883
Short name T451
Test name
Test status
Simulation time 89921992 ps
CPU time 1.15 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 215752 kb
Host smart-09572b25-b99e-45f4-8a28-56aab043325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908480883 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.2908480883
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/199.edn_genbits.4101517828
Short name T575
Test name
Test status
Simulation time 75338567 ps
CPU time 1.49 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218924 kb
Host smart-d762d916-650c-4481-a9cc-03a2c87b71f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101517828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4101517828
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3740707937
Short name T165
Test name
Test status
Simulation time 22575285 ps
CPU time 1.11 seconds
Started Aug 16 06:21:00 PM PDT 24
Finished Aug 16 06:21:02 PM PDT 24
Peak memory 219596 kb
Host smart-a1286cf2-18ae-4f4e-809c-74496de07f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740707937 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3740707937
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3726151977
Short name T412
Test name
Test status
Simulation time 62195877 ps
CPU time 0.94 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:20:59 PM PDT 24
Peak memory 206776 kb
Host smart-ea420dcb-38b7-4dec-9c99-f30f197f80ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726151977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3726151977
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.4057446555
Short name T567
Test name
Test status
Simulation time 25802001 ps
CPU time 0.86 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:20:59 PM PDT 24
Peak memory 206964 kb
Host smart-a8dd337d-0ec4-47c1-b436-0ec6c2ba58c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057446555 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.4057446555
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.53978810
Short name T719
Test name
Test status
Simulation time 42135963 ps
CPU time 1.14 seconds
Started Aug 16 06:21:03 PM PDT 24
Finished Aug 16 06:21:04 PM PDT 24
Peak memory 216860 kb
Host smart-305c30d4-59dc-4c8e-95fd-d3e5f786fb75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53978810 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disa
ble_auto_req_mode.53978810
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3192993479
Short name T175
Test name
Test status
Simulation time 20053091 ps
CPU time 1.11 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:20:59 PM PDT 24
Peak memory 218520 kb
Host smart-be146fab-c2cb-4ec4-a0ba-c52f4ea4c8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192993479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3192993479
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3959758011
Short name T506
Test name
Test status
Simulation time 105965586 ps
CPU time 1.49 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:20:59 PM PDT 24
Peak memory 218696 kb
Host smart-79a1b60b-1b80-40b7-aacd-fabcf9da95e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959758011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3959758011
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1263747524
Short name T889
Test name
Test status
Simulation time 22983573 ps
CPU time 1.02 seconds
Started Aug 16 06:21:03 PM PDT 24
Finished Aug 16 06:21:05 PM PDT 24
Peak memory 215580 kb
Host smart-5e15c69d-ccf3-44cf-835a-bb402835a31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263747524 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1263747524
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3663089952
Short name T679
Test name
Test status
Simulation time 46632709 ps
CPU time 0.96 seconds
Started Aug 16 06:21:04 PM PDT 24
Finished Aug 16 06:21:05 PM PDT 24
Peak memory 207144 kb
Host smart-7afe0f7d-c83c-48c4-a43c-045367488a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663089952 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3663089952
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1755321157
Short name T13
Test name
Test status
Simulation time 1048535124 ps
CPU time 9.35 seconds
Started Aug 16 06:21:05 PM PDT 24
Finished Aug 16 06:21:14 PM PDT 24
Peak memory 242916 kb
Host smart-8d2660d1-eb2c-4559-b0e1-a45c9bb2b5ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755321157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1755321157
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2970694575
Short name T597
Test name
Test status
Simulation time 50072815 ps
CPU time 0.94 seconds
Started Aug 16 06:21:00 PM PDT 24
Finished Aug 16 06:21:01 PM PDT 24
Peak memory 215372 kb
Host smart-ed850433-c227-45aa-987b-0aea67aba69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970694575 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2970694575
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1470012345
Short name T692
Test name
Test status
Simulation time 123407348 ps
CPU time 2.22 seconds
Started Aug 16 06:20:59 PM PDT 24
Finished Aug 16 06:21:01 PM PDT 24
Peak memory 220336 kb
Host smart-3bc86330-e237-403a-bbe2-e59ed642f296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470012345 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1470012345
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.112002768
Short name T220
Test name
Test status
Simulation time 836768127 ps
CPU time 24.42 seconds
Started Aug 16 06:20:56 PM PDT 24
Finished Aug 16 06:21:21 PM PDT 24
Peak memory 215592 kb
Host smart-c2dee3e6-3fbd-40ef-85b4-952dc8dd4402
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112002768 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.112002768
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3250918456
Short name T704
Test name
Test status
Simulation time 49272205 ps
CPU time 1.31 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 218696 kb
Host smart-5f6f7016-f59d-42a5-b154-373502235f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250918456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3250918456
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.549180777
Short name T367
Test name
Test status
Simulation time 76908440 ps
CPU time 0.88 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 215084 kb
Host smart-a023aa76-c1b9-433f-be9e-824f21301b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549180777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.549180777
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.2819991352
Short name T353
Test name
Test status
Simulation time 23509819 ps
CPU time 0.95 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 215188 kb
Host smart-e6dc6d6a-6736-4c33-9e79-ee63fd58df0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819991352 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2819991352
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3691991626
Short name T907
Test name
Test status
Simulation time 111214587 ps
CPU time 1.05 seconds
Started Aug 16 06:21:36 PM PDT 24
Finished Aug 16 06:21:37 PM PDT 24
Peak memory 216764 kb
Host smart-45007e1c-4b5d-442c-a38a-0ac0788720e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691991626 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3691991626
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3981341324
Short name T383
Test name
Test status
Simulation time 25946388 ps
CPU time 1 seconds
Started Aug 16 06:21:30 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 219896 kb
Host smart-2b007880-71d9-484d-95d2-d6ea873a9637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981341324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3981341324
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3976019590
Short name T341
Test name
Test status
Simulation time 58527820 ps
CPU time 1.07 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:34 PM PDT 24
Peak memory 217420 kb
Host smart-89992e8d-a710-40ba-8e4d-999a252669f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976019590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3976019590
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.428301593
Short name T87
Test name
Test status
Simulation time 23541166 ps
CPU time 0.92 seconds
Started Aug 16 06:21:30 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 215920 kb
Host smart-3a30d421-1f18-431f-991d-33b7ab51220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428301593 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.428301593
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1241103803
Short name T839
Test name
Test status
Simulation time 38455488 ps
CPU time 0.87 seconds
Started Aug 16 06:21:34 PM PDT 24
Finished Aug 16 06:21:36 PM PDT 24
Peak memory 215352 kb
Host smart-b2cc171c-4953-40f1-b909-23e0d371150e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241103803 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1241103803
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3670377834
Short name T594
Test name
Test status
Simulation time 127646614 ps
CPU time 2.38 seconds
Started Aug 16 06:21:30 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 217252 kb
Host smart-2086d463-51c1-4809-a1e5-283c042583c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670377834 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3670377834
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2200805619
Short name T592
Test name
Test status
Simulation time 2257247239 ps
CPU time 12.75 seconds
Started Aug 16 06:21:42 PM PDT 24
Finished Aug 16 06:21:55 PM PDT 24
Peak memory 218960 kb
Host smart-50a0b056-bed0-4566-bc52-e2e5a29073fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200805619 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2200805619
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1691299723
Short name T325
Test name
Test status
Simulation time 51391767 ps
CPU time 1.28 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 217388 kb
Host smart-cee363c8-b2e8-47c5-b606-45d54b20464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691299723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1691299723
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.4245659076
Short name T744
Test name
Test status
Simulation time 82381074 ps
CPU time 1.3 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 217392 kb
Host smart-2cb892e7-f263-4c93-9526-d8c8fe4a550b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245659076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.4245659076
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1545595458
Short name T332
Test name
Test status
Simulation time 62863305 ps
CPU time 1.19 seconds
Started Aug 16 06:22:59 PM PDT 24
Finished Aug 16 06:23:01 PM PDT 24
Peak memory 218676 kb
Host smart-ed1aaeb7-1618-4029-9fd3-1d224e7a9ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545595458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1545595458
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4222428133
Short name T710
Test name
Test status
Simulation time 21362932 ps
CPU time 1.11 seconds
Started Aug 16 06:23:27 PM PDT 24
Finished Aug 16 06:23:28 PM PDT 24
Peak memory 217388 kb
Host smart-0de4423f-706a-4f33-90dd-01586cb70ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222428133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4222428133
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1377197897
Short name T15
Test name
Test status
Simulation time 85124822 ps
CPU time 2.6 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:04 PM PDT 24
Peak memory 220500 kb
Host smart-da9b17a9-20c3-4e39-a066-4cf3883be9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377197897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1377197897
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3678289378
Short name T809
Test name
Test status
Simulation time 42675983 ps
CPU time 1.76 seconds
Started Aug 16 06:23:24 PM PDT 24
Finished Aug 16 06:23:26 PM PDT 24
Peak memory 218544 kb
Host smart-8aed49f4-9e68-4081-ab16-edd95d0cdc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678289378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3678289378
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1418385895
Short name T318
Test name
Test status
Simulation time 54325616 ps
CPU time 1.17 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 220500 kb
Host smart-8a6b1eb9-bf4a-44c9-85f5-9b74e8237116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418385895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1418385895
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1461542259
Short name T885
Test name
Test status
Simulation time 101667174 ps
CPU time 1.44 seconds
Started Aug 16 06:23:01 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 218960 kb
Host smart-6552ffee-a978-4c14-9368-2aa905ab74de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461542259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1461542259
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3892919246
Short name T510
Test name
Test status
Simulation time 51056242 ps
CPU time 1.79 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 218708 kb
Host smart-4ea47786-9476-4bb8-9dfd-8c2032bd2a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892919246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3892919246
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.910184843
Short name T802
Test name
Test status
Simulation time 52329616 ps
CPU time 1.48 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 218660 kb
Host smart-51fc7b44-41ba-4344-bfc6-76568d9ba74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910184843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.910184843
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1196669840
Short name T797
Test name
Test status
Simulation time 97545754 ps
CPU time 1.24 seconds
Started Aug 16 06:21:45 PM PDT 24
Finished Aug 16 06:21:46 PM PDT 24
Peak memory 218668 kb
Host smart-767da518-c7a2-474a-9ba2-d654d81cffc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196669840 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1196669840
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1672749187
Short name T677
Test name
Test status
Simulation time 26654659 ps
CPU time 0.9 seconds
Started Aug 16 06:21:36 PM PDT 24
Finished Aug 16 06:21:37 PM PDT 24
Peak memory 215012 kb
Host smart-923ade33-f89e-4187-b397-768b1d4fa760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672749187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1672749187
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3677729338
Short name T181
Test name
Test status
Simulation time 62972768 ps
CPU time 0.88 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 215420 kb
Host smart-cfa96026-d3ea-4cd0-8888-647a0916519b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677729338 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3677729338
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3713513415
Short name T660
Test name
Test status
Simulation time 103581781 ps
CPU time 1.15 seconds
Started Aug 16 06:21:30 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 218760 kb
Host smart-be4622be-7439-4c82-8628-adece03bf8bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713513415 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3713513415
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1764475962
Short name T392
Test name
Test status
Simulation time 32631109 ps
CPU time 0.89 seconds
Started Aug 16 06:21:35 PM PDT 24
Finished Aug 16 06:21:36 PM PDT 24
Peak memory 218280 kb
Host smart-569c3dbf-b104-4186-b0a7-df1ddc13c495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764475962 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1764475962
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2592011154
Short name T468
Test name
Test status
Simulation time 66113892 ps
CPU time 1.25 seconds
Started Aug 16 06:21:30 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 217520 kb
Host smart-b7b3cc23-7b78-4730-9c4f-a827c1a2e97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592011154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2592011154
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1792151601
Short name T869
Test name
Test status
Simulation time 26997321 ps
CPU time 0.98 seconds
Started Aug 16 06:21:29 PM PDT 24
Finished Aug 16 06:21:30 PM PDT 24
Peak memory 215596 kb
Host smart-962bf9fb-1a93-4bc3-80fb-7f399f47f0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792151601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1792151601
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2084543535
Short name T967
Test name
Test status
Simulation time 20141474 ps
CPU time 1.03 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:33 PM PDT 24
Peak memory 215384 kb
Host smart-1a37a3bf-08eb-4216-854d-f48da0db431b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084543535 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2084543535
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3989851528
Short name T45
Test name
Test status
Simulation time 245451981 ps
CPU time 3.37 seconds
Started Aug 16 06:21:42 PM PDT 24
Finished Aug 16 06:21:45 PM PDT 24
Peak memory 215332 kb
Host smart-03c32d83-d98e-40a0-af31-2e21a178f3b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989851528 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3989851528
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/210.edn_genbits.2618294095
Short name T437
Test name
Test status
Simulation time 45635748 ps
CPU time 1.73 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:09 PM PDT 24
Peak memory 218688 kb
Host smart-82f1bb63-41a4-4398-b234-50eb552afe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618294095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2618294095
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3767371771
Short name T803
Test name
Test status
Simulation time 68364624 ps
CPU time 1.38 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 218788 kb
Host smart-6b9d87c9-acea-4f95-8f23-62a7f5b4cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767371771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3767371771
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.4252116334
Short name T821
Test name
Test status
Simulation time 66953796 ps
CPU time 1.25 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 217428 kb
Host smart-ca927c74-11a7-46d2-bf06-0ebbabfc7470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252116334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.4252116334
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3861500401
Short name T782
Test name
Test status
Simulation time 50357272 ps
CPU time 1.21 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 217344 kb
Host smart-0db246ed-ba0f-4ba5-a45f-b80ade1fbee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861500401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3861500401
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.43383311
Short name T955
Test name
Test status
Simulation time 52176617 ps
CPU time 1.23 seconds
Started Aug 16 06:23:15 PM PDT 24
Finished Aug 16 06:23:16 PM PDT 24
Peak memory 220552 kb
Host smart-18cb0405-218a-49e0-9486-4622a2bb567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43383311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.43383311
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3903874102
Short name T516
Test name
Test status
Simulation time 40534193 ps
CPU time 1.47 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:09 PM PDT 24
Peak memory 218780 kb
Host smart-cf32998e-3771-4225-b328-cb31288db2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903874102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3903874102
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.633387309
Short name T584
Test name
Test status
Simulation time 56061729 ps
CPU time 1.72 seconds
Started Aug 16 06:23:14 PM PDT 24
Finished Aug 16 06:23:16 PM PDT 24
Peak memory 218564 kb
Host smart-13fd9b22-428d-4034-a2f0-0fa709fcd144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633387309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.633387309
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3070383922
Short name T674
Test name
Test status
Simulation time 34032397 ps
CPU time 1.24 seconds
Started Aug 16 06:23:12 PM PDT 24
Finished Aug 16 06:23:13 PM PDT 24
Peak memory 218436 kb
Host smart-7a9c3820-d4e6-49d2-a6ad-5b4d2abb3779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070383922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3070383922
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1534703707
Short name T819
Test name
Test status
Simulation time 52473114 ps
CPU time 1.34 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:08 PM PDT 24
Peak memory 218700 kb
Host smart-f3094342-0bfc-4bd4-8727-bda32619404e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534703707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1534703707
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2361867776
Short name T511
Test name
Test status
Simulation time 24932563 ps
CPU time 1.24 seconds
Started Aug 16 06:21:34 PM PDT 24
Finished Aug 16 06:21:35 PM PDT 24
Peak memory 220956 kb
Host smart-fe06b7da-6027-4f56-b84b-f90ca3c8f409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361867776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2361867776
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2457639662
Short name T698
Test name
Test status
Simulation time 38334242 ps
CPU time 0.82 seconds
Started Aug 16 06:21:32 PM PDT 24
Finished Aug 16 06:21:33 PM PDT 24
Peak memory 206556 kb
Host smart-6ca23c6a-eaed-4cf3-8e52-d7094bb6ce86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457639662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2457639662
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1909703035
Short name T407
Test name
Test status
Simulation time 36513794 ps
CPU time 0.89 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 215216 kb
Host smart-e9b33b5c-6a5d-4df0-b50b-1cb751b241ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909703035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1909703035
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2194590649
Short name T716
Test name
Test status
Simulation time 70603306 ps
CPU time 1.09 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:34 PM PDT 24
Peak memory 216920 kb
Host smart-a96a2525-6e3f-40eb-bfbe-b7c2728c749b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194590649 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2194590649
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3937412232
Short name T391
Test name
Test status
Simulation time 68776703 ps
CPU time 1.06 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 217392 kb
Host smart-ab77fda6-d586-49ce-83d8-53a252f96c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937412232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3937412232
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2874901300
Short name T313
Test name
Test status
Simulation time 166615010 ps
CPU time 1.32 seconds
Started Aug 16 06:21:43 PM PDT 24
Finished Aug 16 06:21:45 PM PDT 24
Peak memory 218760 kb
Host smart-96169d11-c3d7-4c50-81a7-513bcbef8698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874901300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2874901300
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1687163040
Short name T88
Test name
Test status
Simulation time 36401189 ps
CPU time 0.83 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:35 PM PDT 24
Peak memory 215740 kb
Host smart-323bfe19-1bd6-410d-802d-c6f43ffed3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687163040 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1687163040
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3131463442
Short name T844
Test name
Test status
Simulation time 19410762 ps
CPU time 0.91 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:34 PM PDT 24
Peak memory 215428 kb
Host smart-12e366f0-82fc-49f4-af77-a4509357df43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131463442 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3131463442
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1294228892
Short name T430
Test name
Test status
Simulation time 148866556 ps
CPU time 1.48 seconds
Started Aug 16 06:21:32 PM PDT 24
Finished Aug 16 06:21:33 PM PDT 24
Peak memory 217424 kb
Host smart-247b3576-efc6-4cd4-95ef-7273602c97e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294228892 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1294228892
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3891800062
Short name T958
Test name
Test status
Simulation time 13371145778 ps
CPU time 183.82 seconds
Started Aug 16 06:21:35 PM PDT 24
Finished Aug 16 06:24:39 PM PDT 24
Peak memory 218568 kb
Host smart-66f904fd-b030-446e-9cee-3831c62f1dcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891800062 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3891800062
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3840545796
Short name T801
Test name
Test status
Simulation time 102324295 ps
CPU time 1.51 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 218952 kb
Host smart-082a9d2f-e66a-4710-8d38-98e2a40f6391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840545796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3840545796
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2740994322
Short name T587
Test name
Test status
Simulation time 37571263 ps
CPU time 1.23 seconds
Started Aug 16 06:23:52 PM PDT 24
Finished Aug 16 06:23:53 PM PDT 24
Peak memory 219944 kb
Host smart-6a6bf7dc-91fc-4fa3-8c7d-cbd7e0f8f9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740994322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2740994322
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3284422677
Short name T908
Test name
Test status
Simulation time 46656676 ps
CPU time 1.69 seconds
Started Aug 16 06:23:24 PM PDT 24
Finished Aug 16 06:23:26 PM PDT 24
Peak memory 218696 kb
Host smart-3c102330-8adc-427c-b5ce-940ae066a01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284422677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3284422677
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.4160007021
Short name T583
Test name
Test status
Simulation time 50329274 ps
CPU time 0.99 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 217336 kb
Host smart-cff8a6bf-b6bf-4a3a-b6da-054fea9259a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160007021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.4160007021
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3731584225
Short name T494
Test name
Test status
Simulation time 75365622 ps
CPU time 1.11 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 219272 kb
Host smart-3b184d8f-38ee-481a-983b-282bfb8437c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731584225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3731584225
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3464697462
Short name T632
Test name
Test status
Simulation time 97708277 ps
CPU time 1.56 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 218752 kb
Host smart-682c5ea5-a8cc-48e9-9f17-2257d064b7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464697462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3464697462
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.601742582
Short name T312
Test name
Test status
Simulation time 56094789 ps
CPU time 1.26 seconds
Started Aug 16 06:23:11 PM PDT 24
Finished Aug 16 06:23:13 PM PDT 24
Peak memory 218800 kb
Host smart-c6ba2288-02d0-4b78-8841-218b1dc31f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601742582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.601742582
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2583330781
Short name T683
Test name
Test status
Simulation time 118080731 ps
CPU time 1.15 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:09 PM PDT 24
Peak memory 217348 kb
Host smart-3b7e9439-a806-45df-b511-8bbe7e35e6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583330781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2583330781
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.27252662
Short name T962
Test name
Test status
Simulation time 94999684 ps
CPU time 1.62 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 219008 kb
Host smart-192c52f3-2459-48e0-a962-c372697e020f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27252662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.27252662
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1484997547
Short name T385
Test name
Test status
Simulation time 75969180 ps
CPU time 2.45 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:13 PM PDT 24
Peak memory 219604 kb
Host smart-64cc1a58-dd91-451a-a22e-2d2371a4b64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484997547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1484997547
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.4214027094
Short name T733
Test name
Test status
Simulation time 70431537 ps
CPU time 1.03 seconds
Started Aug 16 06:21:40 PM PDT 24
Finished Aug 16 06:21:42 PM PDT 24
Peak memory 219880 kb
Host smart-cc8bec08-7c64-4ebf-8b79-b4f67d7ba21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214027094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.4214027094
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2876464154
Short name T552
Test name
Test status
Simulation time 78521557 ps
CPU time 0.96 seconds
Started Aug 16 06:21:35 PM PDT 24
Finished Aug 16 06:21:37 PM PDT 24
Peak memory 206788 kb
Host smart-754d4661-813a-450b-9b07-15647a56a8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876464154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2876464154
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2531421406
Short name T366
Test name
Test status
Simulation time 41724082 ps
CPU time 0.9 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 207004 kb
Host smart-4a64a328-2b6f-4fb5-a5cc-82eff5efe109
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531421406 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2531421406
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2507244788
Short name T192
Test name
Test status
Simulation time 35530500 ps
CPU time 1.11 seconds
Started Aug 16 06:21:30 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 218268 kb
Host smart-f5c22160-3f9e-4c39-b024-3365cd611724
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507244788 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2507244788
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2714184110
Short name T159
Test name
Test status
Simulation time 30236436 ps
CPU time 1.28 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:35 PM PDT 24
Peak memory 219604 kb
Host smart-10529074-e410-45a7-a78c-4fd031cc21f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714184110 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2714184110
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2278661515
Short name T460
Test name
Test status
Simulation time 65028932 ps
CPU time 1.16 seconds
Started Aug 16 06:21:38 PM PDT 24
Finished Aug 16 06:21:40 PM PDT 24
Peak memory 219052 kb
Host smart-4affa609-2456-44b4-9408-e3ffc8eb0402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278661515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2278661515
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3828477799
Short name T558
Test name
Test status
Simulation time 99966822 ps
CPU time 0.87 seconds
Started Aug 16 06:21:52 PM PDT 24
Finished Aug 16 06:21:53 PM PDT 24
Peak memory 215436 kb
Host smart-b97eeb99-28db-4d81-90c9-10d0dda03e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828477799 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3828477799
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1969106908
Short name T337
Test name
Test status
Simulation time 23004189 ps
CPU time 0.95 seconds
Started Aug 16 06:21:34 PM PDT 24
Finished Aug 16 06:21:36 PM PDT 24
Peak memory 215368 kb
Host smart-55bb53ac-f6a0-4598-ad97-b46481ca9a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969106908 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1969106908
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.364689289
Short name T235
Test name
Test status
Simulation time 283512889 ps
CPU time 1.66 seconds
Started Aug 16 06:21:34 PM PDT 24
Finished Aug 16 06:21:36 PM PDT 24
Peak memory 215348 kb
Host smart-ba2406b5-096e-494c-b405-de3ce4c22e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364689289 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.364689289
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/230.edn_genbits.4237697966
Short name T328
Test name
Test status
Simulation time 54540034 ps
CPU time 1.43 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 218640 kb
Host smart-e3d086e4-61f2-49d3-9429-86c8a72f42bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237697966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.4237697966
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.837753707
Short name T279
Test name
Test status
Simulation time 69595948 ps
CPU time 1.3 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218900 kb
Host smart-d9f2fd20-a725-4b45-8f48-7478dd72b20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837753707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.837753707
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.70386211
Short name T838
Test name
Test status
Simulation time 60560973 ps
CPU time 1.56 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 218608 kb
Host smart-5c8c4e90-8089-43d0-8470-fe0479d6ff98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70386211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.70386211
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.553174840
Short name T355
Test name
Test status
Simulation time 180054537 ps
CPU time 1.02 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 217428 kb
Host smart-d95eaada-b981-4da8-b86e-b524f23b90a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553174840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.553174840
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2499388177
Short name T886
Test name
Test status
Simulation time 34583113 ps
CPU time 1.45 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 217248 kb
Host smart-3a4d46fe-3f9b-45af-ba36-2a9f897ca298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499388177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2499388177
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2880289550
Short name T951
Test name
Test status
Simulation time 59571438 ps
CPU time 1.01 seconds
Started Aug 16 06:23:05 PM PDT 24
Finished Aug 16 06:23:06 PM PDT 24
Peak memory 217440 kb
Host smart-dcc812ff-d433-431c-9f47-b89cdcca5179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880289550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2880289550
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.444363144
Short name T517
Test name
Test status
Simulation time 196485277 ps
CPU time 1.16 seconds
Started Aug 16 06:23:02 PM PDT 24
Finished Aug 16 06:23:03 PM PDT 24
Peak memory 217396 kb
Host smart-47da3c02-c2ce-4f8b-aeb2-f8a702cd550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444363144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.444363144
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3220816898
Short name T736
Test name
Test status
Simulation time 84287305 ps
CPU time 1.57 seconds
Started Aug 16 06:23:06 PM PDT 24
Finished Aug 16 06:23:13 PM PDT 24
Peak memory 217668 kb
Host smart-1ae93a97-4721-4bbb-95cf-d8802653f0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220816898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3220816898
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2937938426
Short name T525
Test name
Test status
Simulation time 41940079 ps
CPU time 1.43 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:09 PM PDT 24
Peak memory 217364 kb
Host smart-3315de44-a032-42d8-ac46-48476379a03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937938426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2937938426
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.802941819
Short name T652
Test name
Test status
Simulation time 100755042 ps
CPU time 1.13 seconds
Started Aug 16 06:21:34 PM PDT 24
Finished Aug 16 06:21:35 PM PDT 24
Peak memory 219940 kb
Host smart-e52a322b-9b08-4582-a14d-2713fa5ed202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802941819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.802941819
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4067605157
Short name T964
Test name
Test status
Simulation time 31209035 ps
CPU time 0.92 seconds
Started Aug 16 06:21:36 PM PDT 24
Finished Aug 16 06:21:37 PM PDT 24
Peak memory 206832 kb
Host smart-b66461aa-e477-4d44-8677-8280e735381a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067605157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4067605157
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2097402989
Short name T911
Test name
Test status
Simulation time 24377692 ps
CPU time 0.88 seconds
Started Aug 16 06:21:31 PM PDT 24
Finished Aug 16 06:21:32 PM PDT 24
Peak memory 215456 kb
Host smart-6e3b680e-7ec5-4042-bc3c-80f928ed2ac4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097402989 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2097402989
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.3661995166
Short name T206
Test name
Test status
Simulation time 34519144 ps
CPU time 0.94 seconds
Started Aug 16 06:21:32 PM PDT 24
Finished Aug 16 06:21:33 PM PDT 24
Peak memory 219836 kb
Host smart-7bb6fd3d-1381-406b-b607-222deb0f6cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661995166 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3661995166
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3214862729
Short name T784
Test name
Test status
Simulation time 223959243 ps
CPU time 1.47 seconds
Started Aug 16 06:21:29 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 219028 kb
Host smart-f7afe531-5f98-4e2b-9a5e-051754d21076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214862729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3214862729
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3853564266
Short name T826
Test name
Test status
Simulation time 21296283 ps
CPU time 1.08 seconds
Started Aug 16 06:21:35 PM PDT 24
Finished Aug 16 06:21:36 PM PDT 24
Peak memory 215600 kb
Host smart-be83f223-8794-48dd-ab84-c22f825a50b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853564266 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3853564266
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1646938317
Short name T737
Test name
Test status
Simulation time 17391197 ps
CPU time 1.02 seconds
Started Aug 16 06:21:35 PM PDT 24
Finished Aug 16 06:21:37 PM PDT 24
Peak memory 215292 kb
Host smart-f4181065-9ebd-4511-b316-fc00add9c65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646938317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1646938317
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.773020541
Short name T218
Test name
Test status
Simulation time 6198113230 ps
CPU time 44.68 seconds
Started Aug 16 06:21:39 PM PDT 24
Finished Aug 16 06:22:24 PM PDT 24
Peak memory 218484 kb
Host smart-7f289bcb-fae8-4ac0-9a9b-bde0627e6812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773020541 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.773020541
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3500871579
Short name T601
Test name
Test status
Simulation time 186559026 ps
CPU time 1.87 seconds
Started Aug 16 06:23:05 PM PDT 24
Finished Aug 16 06:23:07 PM PDT 24
Peak memory 219024 kb
Host smart-292d3260-d6c6-42ee-8f95-f18b5d51833e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500871579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3500871579
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2725157967
Short name T799
Test name
Test status
Simulation time 28223417 ps
CPU time 1.26 seconds
Started Aug 16 06:23:26 PM PDT 24
Finished Aug 16 06:23:28 PM PDT 24
Peak memory 217264 kb
Host smart-209607f3-0708-4c19-8c69-a7ff584943ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725157967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2725157967
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1705804352
Short name T783
Test name
Test status
Simulation time 52300888 ps
CPU time 1.19 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218548 kb
Host smart-cb0354aa-0d59-4b90-836c-79034bf07325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705804352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1705804352
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1136392558
Short name T521
Test name
Test status
Simulation time 182924002 ps
CPU time 1.57 seconds
Started Aug 16 06:23:34 PM PDT 24
Finished Aug 16 06:23:36 PM PDT 24
Peak memory 219160 kb
Host smart-6749afbf-1a5d-4979-bbd9-6821b29c5054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136392558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1136392558
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1533867675
Short name T905
Test name
Test status
Simulation time 47944685 ps
CPU time 1.57 seconds
Started Aug 16 06:23:11 PM PDT 24
Finished Aug 16 06:23:13 PM PDT 24
Peak memory 217268 kb
Host smart-bc2c1144-f079-4ca2-b214-0c139c76097f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533867675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1533867675
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.579273619
Short name T448
Test name
Test status
Simulation time 45549305 ps
CPU time 1.4 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:08 PM PDT 24
Peak memory 218620 kb
Host smart-8766da6b-289a-4b07-892e-74cae168c13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579273619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.579273619
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2785648622
Short name T741
Test name
Test status
Simulation time 100420819 ps
CPU time 1.35 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 218852 kb
Host smart-78e06565-4632-4e26-8b19-1098beac1144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785648622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2785648622
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1321942916
Short name T795
Test name
Test status
Simulation time 57796631 ps
CPU time 1.02 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 217568 kb
Host smart-4ab08cb9-9c43-4c3e-9578-5b589b364530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321942916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1321942916
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2791744935
Short name T77
Test name
Test status
Simulation time 96454920 ps
CPU time 1.21 seconds
Started Aug 16 06:21:43 PM PDT 24
Finished Aug 16 06:21:44 PM PDT 24
Peak memory 215700 kb
Host smart-8fb4e197-e137-42bd-a899-2a17e1ccf37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791744935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2791744935
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.191751306
Short name T655
Test name
Test status
Simulation time 21541298 ps
CPU time 1.04 seconds
Started Aug 16 06:21:55 PM PDT 24
Finished Aug 16 06:21:56 PM PDT 24
Peak memory 214988 kb
Host smart-ba72dafa-47a9-47bd-b796-60fe01817f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191751306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.191751306
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.981567573
Short name T411
Test name
Test status
Simulation time 41789404 ps
CPU time 0.86 seconds
Started Aug 16 06:21:37 PM PDT 24
Finished Aug 16 06:21:38 PM PDT 24
Peak memory 215472 kb
Host smart-31996c77-bb34-4b32-a872-a387f29ab154
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981567573 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.981567573
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.937716304
Short name T497
Test name
Test status
Simulation time 40942891 ps
CPU time 1.32 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:35 PM PDT 24
Peak memory 216772 kb
Host smart-9907b559-9306-4a4b-a63b-29441025e546
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937716304 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.937716304
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.562883649
Short name T143
Test name
Test status
Simulation time 35423016 ps
CPU time 0.95 seconds
Started Aug 16 06:21:37 PM PDT 24
Finished Aug 16 06:21:38 PM PDT 24
Peak memory 219944 kb
Host smart-4d43ff64-77e4-4a91-b6da-4652fbdd4192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562883649 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.562883649
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.642894342
Short name T912
Test name
Test status
Simulation time 282379814 ps
CPU time 3.05 seconds
Started Aug 16 06:21:34 PM PDT 24
Finished Aug 16 06:21:37 PM PDT 24
Peak memory 220564 kb
Host smart-86780f48-6b92-48d5-86ec-339e74d3a048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642894342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.642894342
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2997757594
Short name T842
Test name
Test status
Simulation time 27510399 ps
CPU time 1.1 seconds
Started Aug 16 06:21:47 PM PDT 24
Finished Aug 16 06:21:48 PM PDT 24
Peak memory 224176 kb
Host smart-a26fc330-1c67-4b4e-995c-1bdf7dee1a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997757594 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2997757594
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1161543226
Short name T348
Test name
Test status
Simulation time 25530120 ps
CPU time 0.95 seconds
Started Aug 16 06:21:34 PM PDT 24
Finished Aug 16 06:21:35 PM PDT 24
Peak memory 215312 kb
Host smart-40caf4f0-2a5b-49b5-9ec7-3d04f4c8b2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161543226 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1161543226
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3536901676
Short name T376
Test name
Test status
Simulation time 142328233 ps
CPU time 2.81 seconds
Started Aug 16 06:21:33 PM PDT 24
Finished Aug 16 06:21:36 PM PDT 24
Peak memory 217252 kb
Host smart-1b1bf02c-38c2-461f-b6b9-bfbd645cb6d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536901676 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3536901676
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/250.edn_genbits.3266463690
Short name T591
Test name
Test status
Simulation time 111010786 ps
CPU time 1.5 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 219076 kb
Host smart-83922940-f0d7-42bf-bf7e-c7dfcfe4a5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266463690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3266463690
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2925895967
Short name T436
Test name
Test status
Simulation time 155169111 ps
CPU time 1.22 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 217376 kb
Host smart-bda422d2-0dfa-49c0-9750-d35c28135006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925895967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2925895967
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2382102320
Short name T520
Test name
Test status
Simulation time 47365984 ps
CPU time 1.57 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218860 kb
Host smart-794fce03-131b-4ab8-8dca-2e9544cb42a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382102320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2382102320
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1643975335
Short name T877
Test name
Test status
Simulation time 33908321 ps
CPU time 1.46 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 218628 kb
Host smart-9eef46da-0ec2-472c-8e6a-e183864554f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643975335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1643975335
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3990215913
Short name T473
Test name
Test status
Simulation time 95153757 ps
CPU time 1.2 seconds
Started Aug 16 06:23:04 PM PDT 24
Finished Aug 16 06:23:06 PM PDT 24
Peak memory 217356 kb
Host smart-c72a52d3-d81d-41b0-85aa-c21a26849225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990215913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3990215913
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3510916129
Short name T707
Test name
Test status
Simulation time 75852455 ps
CPU time 1.49 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:09 PM PDT 24
Peak memory 218720 kb
Host smart-b20b3024-6fe4-4477-b2be-5f11dcddb53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510916129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3510916129
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.911418983
Short name T489
Test name
Test status
Simulation time 43596818 ps
CPU time 1.3 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218892 kb
Host smart-73a5bf4a-00f2-4618-834e-a2e771481d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911418983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.911418983
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.565723439
Short name T879
Test name
Test status
Simulation time 27330530 ps
CPU time 1.19 seconds
Started Aug 16 06:23:17 PM PDT 24
Finished Aug 16 06:23:18 PM PDT 24
Peak memory 217548 kb
Host smart-056f9dea-7746-4e96-815f-309db798514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565723439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.565723439
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3715161409
Short name T16
Test name
Test status
Simulation time 999641686 ps
CPU time 8.21 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:18 PM PDT 24
Peak memory 220624 kb
Host smart-5f6b2788-cb48-49bf-b247-f63dc4922ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715161409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3715161409
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1894744860
Short name T459
Test name
Test status
Simulation time 86019834 ps
CPU time 1.28 seconds
Started Aug 16 06:23:11 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 218556 kb
Host smart-20ff91ab-1e15-4812-bf7a-7b0a3b07cc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894744860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1894744860
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3039848995
Short name T188
Test name
Test status
Simulation time 25570300 ps
CPU time 1.18 seconds
Started Aug 16 06:21:41 PM PDT 24
Finished Aug 16 06:21:43 PM PDT 24
Peak memory 219888 kb
Host smart-2a0fbc1a-5c9c-420c-b45b-bf84127ab55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039848995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3039848995
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3605001555
Short name T609
Test name
Test status
Simulation time 43133369 ps
CPU time 1.39 seconds
Started Aug 16 06:21:40 PM PDT 24
Finished Aug 16 06:21:42 PM PDT 24
Peak memory 206936 kb
Host smart-c047eb3f-4873-4a8f-8761-c5ea90a71da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605001555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3605001555
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.987674242
Short name T536
Test name
Test status
Simulation time 12023932 ps
CPU time 0.94 seconds
Started Aug 16 06:21:41 PM PDT 24
Finished Aug 16 06:21:42 PM PDT 24
Peak memory 215160 kb
Host smart-8e1cb08b-4074-4ab3-b6fc-f596888c4544
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987674242 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.987674242
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.4250446240
Short name T377
Test name
Test status
Simulation time 76535173 ps
CPU time 1.12 seconds
Started Aug 16 06:22:02 PM PDT 24
Finished Aug 16 06:22:03 PM PDT 24
Peak memory 216972 kb
Host smart-2ee5530d-aa5b-40e5-805e-08760059b697
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250446240 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.4250446240
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2547109434
Short name T168
Test name
Test status
Simulation time 23497630 ps
CPU time 1.04 seconds
Started Aug 16 06:21:41 PM PDT 24
Finished Aug 16 06:21:42 PM PDT 24
Peak memory 224124 kb
Host smart-5b212a99-280b-41a1-91a2-ecfb7958b94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547109434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2547109434
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.795931246
Short name T501
Test name
Test status
Simulation time 108019909 ps
CPU time 1.13 seconds
Started Aug 16 06:21:43 PM PDT 24
Finished Aug 16 06:21:44 PM PDT 24
Peak memory 217256 kb
Host smart-2f179f9e-1d45-48de-88ee-70436cf90c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795931246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.795931246
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3637870101
Short name T51
Test name
Test status
Simulation time 22730436 ps
CPU time 1.22 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:21:50 PM PDT 24
Peak memory 224376 kb
Host smart-ecc4e99a-ae49-4956-aa17-ac8bbf6370fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637870101 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3637870101
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2885251342
Short name T456
Test name
Test status
Simulation time 32541221 ps
CPU time 0.89 seconds
Started Aug 16 06:21:32 PM PDT 24
Finished Aug 16 06:21:34 PM PDT 24
Peak memory 215372 kb
Host smart-7ee2ea40-c949-43f2-ba22-8e34717f4021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885251342 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2885251342
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1960641663
Short name T330
Test name
Test status
Simulation time 25373528 ps
CPU time 1.17 seconds
Started Aug 16 06:21:32 PM PDT 24
Finished Aug 16 06:21:33 PM PDT 24
Peak memory 207368 kb
Host smart-93baffe8-40b6-4cc0-b865-f6e1da2b1f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960641663 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1960641663
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1256039842
Short name T223
Test name
Test status
Simulation time 17793301119 ps
CPU time 111.07 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:23:39 PM PDT 24
Peak memory 219000 kb
Host smart-cfa7b525-fed1-4964-a4a0-d08a4b44c813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256039842 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1256039842
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1058750080
Short name T762
Test name
Test status
Simulation time 48115911 ps
CPU time 1.61 seconds
Started Aug 16 06:23:26 PM PDT 24
Finished Aug 16 06:23:27 PM PDT 24
Peak memory 218564 kb
Host smart-265d6d0f-f399-4db1-b701-057fde065746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058750080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1058750080
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.4225342532
Short name T793
Test name
Test status
Simulation time 54026154 ps
CPU time 1.38 seconds
Started Aug 16 06:23:20 PM PDT 24
Finished Aug 16 06:23:21 PM PDT 24
Peak memory 217488 kb
Host smart-73a13216-02ff-44b2-8e62-8e0ffedbeed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225342532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.4225342532
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2639414697
Short name T378
Test name
Test status
Simulation time 81549622 ps
CPU time 1.09 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 217364 kb
Host smart-e143e65b-1b4d-4c69-ad77-f37ebebc2e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639414697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2639414697
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3153541583
Short name T756
Test name
Test status
Simulation time 267708985 ps
CPU time 1.25 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 217536 kb
Host smart-cefb9cb5-ce3f-4376-b5fa-60e13c806d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153541583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3153541583
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1295954616
Short name T11
Test name
Test status
Simulation time 47444581 ps
CPU time 1.16 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 220172 kb
Host smart-9cd8552c-c52d-4876-a431-df5e3a622293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295954616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1295954616
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1457228923
Short name T368
Test name
Test status
Simulation time 37023456 ps
CPU time 1.26 seconds
Started Aug 16 06:23:11 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 220312 kb
Host smart-55fd46ed-6d62-4dbd-aeb6-e20735331fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457228923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1457228923
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2841480192
Short name T527
Test name
Test status
Simulation time 106242838 ps
CPU time 1.24 seconds
Started Aug 16 06:23:25 PM PDT 24
Finished Aug 16 06:23:27 PM PDT 24
Peak memory 219520 kb
Host smart-e8d13218-b4eb-4eeb-8aed-9e3568a05878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841480192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2841480192
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3439948713
Short name T871
Test name
Test status
Simulation time 51989636 ps
CPU time 2.15 seconds
Started Aug 16 06:23:11 PM PDT 24
Finished Aug 16 06:23:13 PM PDT 24
Peak memory 217528 kb
Host smart-affbd076-4cc4-4ad1-992f-c65ee44ec62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439948713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3439948713
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.335745122
Short name T893
Test name
Test status
Simulation time 66710777 ps
CPU time 1.81 seconds
Started Aug 16 06:23:26 PM PDT 24
Finished Aug 16 06:23:28 PM PDT 24
Peak memory 218900 kb
Host smart-821fefaf-c8cc-443a-861b-4fe20545f399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335745122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.335745122
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3461277515
Short name T532
Test name
Test status
Simulation time 44790451 ps
CPU time 1.44 seconds
Started Aug 16 06:23:35 PM PDT 24
Finished Aug 16 06:23:37 PM PDT 24
Peak memory 219288 kb
Host smart-a9f4bbdd-0a86-4bf8-b55a-be226b439175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461277515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3461277515
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3564611976
Short name T217
Test name
Test status
Simulation time 114960543 ps
CPU time 1.29 seconds
Started Aug 16 06:22:01 PM PDT 24
Finished Aug 16 06:22:02 PM PDT 24
Peak memory 219896 kb
Host smart-69346669-cd68-4a15-9d57-7faba0d12444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564611976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3564611976
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3608716935
Short name T848
Test name
Test status
Simulation time 69143159 ps
CPU time 0.97 seconds
Started Aug 16 06:21:39 PM PDT 24
Finished Aug 16 06:21:40 PM PDT 24
Peak memory 206756 kb
Host smart-dca690bf-1c42-4b78-ba8c-bc1e21226525
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608716935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3608716935
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1349566005
Short name T571
Test name
Test status
Simulation time 22716763 ps
CPU time 0.88 seconds
Started Aug 16 06:21:52 PM PDT 24
Finished Aug 16 06:21:53 PM PDT 24
Peak memory 215432 kb
Host smart-e21066cb-6690-4ba9-abe7-f4e05253644c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349566005 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1349566005
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1108482283
Short name T462
Test name
Test status
Simulation time 33691788 ps
CPU time 1.22 seconds
Started Aug 16 06:21:43 PM PDT 24
Finished Aug 16 06:21:49 PM PDT 24
Peak memory 218392 kb
Host smart-19be6987-cef4-4251-abee-45f4ddf70291
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108482283 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1108482283
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_genbits.2019967300
Short name T856
Test name
Test status
Simulation time 51180361 ps
CPU time 1.6 seconds
Started Aug 16 06:21:42 PM PDT 24
Finished Aug 16 06:21:44 PM PDT 24
Peak memory 215368 kb
Host smart-ffcbb852-08df-41f9-892b-64a65ae5f44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019967300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2019967300
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1242248393
Short name T915
Test name
Test status
Simulation time 27773861 ps
CPU time 1.02 seconds
Started Aug 16 06:21:59 PM PDT 24
Finished Aug 16 06:22:00 PM PDT 24
Peak memory 215964 kb
Host smart-be498758-6da7-45c1-b0ca-dcbdd19d49ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242248393 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1242248393
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3642711200
Short name T850
Test name
Test status
Simulation time 46207707 ps
CPU time 0.92 seconds
Started Aug 16 06:21:58 PM PDT 24
Finished Aug 16 06:21:59 PM PDT 24
Peak memory 215376 kb
Host smart-f1833a3a-bc5b-410b-911d-4ce80281ea5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642711200 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3642711200
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1230873185
Short name T310
Test name
Test status
Simulation time 199956187 ps
CPU time 4.39 seconds
Started Aug 16 06:21:40 PM PDT 24
Finished Aug 16 06:21:45 PM PDT 24
Peak memory 215444 kb
Host smart-b3e3e7b2-46fa-4b21-9d16-b888ed9e6c2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230873185 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1230873185
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2710229783
Short name T834
Test name
Test status
Simulation time 2845986044 ps
CPU time 77.18 seconds
Started Aug 16 06:21:39 PM PDT 24
Finished Aug 16 06:22:57 PM PDT 24
Peak memory 220912 kb
Host smart-0fa3b326-15ff-42c8-b981-9d21b2b2c415
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710229783 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2710229783
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2863175653
Short name T647
Test name
Test status
Simulation time 31899678 ps
CPU time 1.44 seconds
Started Aug 16 06:23:22 PM PDT 24
Finished Aug 16 06:23:24 PM PDT 24
Peak memory 218544 kb
Host smart-c89d9bce-5de8-47b6-8a55-91adf19cbcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863175653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2863175653
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.719876924
Short name T389
Test name
Test status
Simulation time 85212437 ps
CPU time 2.94 seconds
Started Aug 16 06:23:32 PM PDT 24
Finished Aug 16 06:23:35 PM PDT 24
Peak memory 219400 kb
Host smart-ed728cba-cb60-4fed-850f-b7c28b265e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719876924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.719876924
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2465108241
Short name T500
Test name
Test status
Simulation time 65718639 ps
CPU time 1.26 seconds
Started Aug 16 06:23:11 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 218472 kb
Host smart-c7e40ba7-a972-4bc6-a301-60fafd169cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465108241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2465108241
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2113954713
Short name T666
Test name
Test status
Simulation time 92621567 ps
CPU time 1.41 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:11 PM PDT 24
Peak memory 218344 kb
Host smart-88669033-446d-4e0f-afa0-ea06f22cb703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113954713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2113954713
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.500296265
Short name T918
Test name
Test status
Simulation time 63149043 ps
CPU time 1.37 seconds
Started Aug 16 06:23:11 PM PDT 24
Finished Aug 16 06:23:13 PM PDT 24
Peak memory 220208 kb
Host smart-6b4f4d0f-f72b-4c89-9e5e-0668f01777d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500296265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.500296265
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1340739939
Short name T331
Test name
Test status
Simulation time 53415209 ps
CPU time 1.17 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 220200 kb
Host smart-63937906-1a64-41a4-9fd7-07695e15e3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340739939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1340739939
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3462451019
Short name T635
Test name
Test status
Simulation time 139071252 ps
CPU time 3.14 seconds
Started Aug 16 06:23:13 PM PDT 24
Finished Aug 16 06:23:16 PM PDT 24
Peak memory 217576 kb
Host smart-29bb8b3d-49c5-4017-aaef-4627899dff32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462451019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3462451019
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1602394976
Short name T724
Test name
Test status
Simulation time 59047617 ps
CPU time 1.4 seconds
Started Aug 16 06:23:50 PM PDT 24
Finished Aug 16 06:23:51 PM PDT 24
Peak memory 218776 kb
Host smart-3fd42838-2a15-4eb8-bd51-8f86530ce5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602394976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1602394976
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3391857762
Short name T326
Test name
Test status
Simulation time 89125314 ps
CPU time 1.35 seconds
Started Aug 16 06:23:07 PM PDT 24
Finished Aug 16 06:23:14 PM PDT 24
Peak memory 218788 kb
Host smart-6af85c2f-404f-42c6-831a-2478eb9bdd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391857762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3391857762
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3549746730
Short name T852
Test name
Test status
Simulation time 53821165 ps
CPU time 1.51 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 220356 kb
Host smart-8db67f8c-f5ab-49ed-bf05-c9a6e10335db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549746730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3549746730
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2687274368
Short name T461
Test name
Test status
Simulation time 24069325 ps
CPU time 1.15 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:21:49 PM PDT 24
Peak memory 220860 kb
Host smart-3432794e-41cd-4dd5-9bb8-9f749e9df2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687274368 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2687274368
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.835267117
Short name T898
Test name
Test status
Simulation time 71671962 ps
CPU time 0.86 seconds
Started Aug 16 06:21:41 PM PDT 24
Finished Aug 16 06:21:42 PM PDT 24
Peak memory 214760 kb
Host smart-b90a1f44-93f8-413d-9f5e-cfd26c9a30e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835267117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.835267117
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1666501276
Short name T764
Test name
Test status
Simulation time 38647167 ps
CPU time 0.86 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:21:49 PM PDT 24
Peak memory 215148 kb
Host smart-81718d13-366d-47ba-9f91-3d45db60771a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666501276 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1666501276
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3138416864
Short name T513
Test name
Test status
Simulation time 40518449 ps
CPU time 1.09 seconds
Started Aug 16 06:21:54 PM PDT 24
Finished Aug 16 06:21:55 PM PDT 24
Peak memory 215360 kb
Host smart-e3834d91-60db-402e-b5cd-406a2847d51a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138416864 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3138416864
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3959026936
Short name T576
Test name
Test status
Simulation time 42055252 ps
CPU time 1.02 seconds
Started Aug 16 06:21:47 PM PDT 24
Finished Aug 16 06:21:48 PM PDT 24
Peak memory 219840 kb
Host smart-b94718bf-5934-416c-bcf6-ec11bc534569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959026936 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3959026936
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3497397022
Short name T240
Test name
Test status
Simulation time 46520530 ps
CPU time 1.28 seconds
Started Aug 16 06:21:41 PM PDT 24
Finished Aug 16 06:21:42 PM PDT 24
Peak memory 217368 kb
Host smart-1d57c70f-b80d-4128-8f20-42b8638ce483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497397022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3497397022
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.380624421
Short name T686
Test name
Test status
Simulation time 20850724 ps
CPU time 1.13 seconds
Started Aug 16 06:21:39 PM PDT 24
Finished Aug 16 06:21:41 PM PDT 24
Peak memory 215596 kb
Host smart-4e01464c-00d1-4ee3-b93e-8ff3ad3c3219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380624421 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.380624421
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.974210491
Short name T539
Test name
Test status
Simulation time 38295937 ps
CPU time 0.91 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:21:49 PM PDT 24
Peak memory 207172 kb
Host smart-2b5fd99f-d0d2-48f9-9208-cb9c1fae30eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974210491 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.974210491
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.185814525
Short name T239
Test name
Test status
Simulation time 726553412 ps
CPU time 6.14 seconds
Started Aug 16 06:22:02 PM PDT 24
Finished Aug 16 06:22:08 PM PDT 24
Peak memory 217176 kb
Host smart-74a2ca89-bef1-4a7b-9d4f-362643fd26b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185814525 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.185814525
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/280.edn_genbits.52805293
Short name T900
Test name
Test status
Simulation time 136230411 ps
CPU time 1.32 seconds
Started Aug 16 06:23:20 PM PDT 24
Finished Aug 16 06:23:21 PM PDT 24
Peak memory 217748 kb
Host smart-62353141-4b93-4fa9-a9cc-fe34c0c6b7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52805293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.52805293
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3013259330
Short name T859
Test name
Test status
Simulation time 66235801 ps
CPU time 1.1 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218712 kb
Host smart-ffd377fe-67ea-4bb6-b75c-f60bb3628ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013259330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3013259330
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3956357130
Short name T420
Test name
Test status
Simulation time 40652420 ps
CPU time 1.38 seconds
Started Aug 16 06:23:38 PM PDT 24
Finished Aug 16 06:23:40 PM PDT 24
Peak memory 218544 kb
Host smart-592c7b6e-2b50-4a12-9c05-bb611594c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956357130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3956357130
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3165740270
Short name T715
Test name
Test status
Simulation time 38924473 ps
CPU time 1.66 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 218700 kb
Host smart-9d64f583-658a-4104-bba2-8e0aee901423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165740270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3165740270
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1316307532
Short name T816
Test name
Test status
Simulation time 75456185 ps
CPU time 1.34 seconds
Started Aug 16 06:23:05 PM PDT 24
Finished Aug 16 06:23:07 PM PDT 24
Peak memory 218632 kb
Host smart-e0254bdf-4b84-4518-9667-e0e18a31136b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316307532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1316307532
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2268800469
Short name T901
Test name
Test status
Simulation time 49929988 ps
CPU time 1.86 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218724 kb
Host smart-75e70636-f991-4744-9b67-d4bfbab665d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268800469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2268800469
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.933950317
Short name T400
Test name
Test status
Simulation time 48901277 ps
CPU time 1.33 seconds
Started Aug 16 06:23:03 PM PDT 24
Finished Aug 16 06:23:05 PM PDT 24
Peak memory 218988 kb
Host smart-30f6df22-e2e7-49b7-86d4-b653decd7f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933950317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.933950317
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2889211628
Short name T705
Test name
Test status
Simulation time 64787956 ps
CPU time 1.87 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218760 kb
Host smart-2ac77e30-2f5e-433d-a181-399e37f80f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889211628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2889211628
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3724434377
Short name T929
Test name
Test status
Simulation time 46167777 ps
CPU time 1.59 seconds
Started Aug 16 06:23:06 PM PDT 24
Finished Aug 16 06:23:08 PM PDT 24
Peak memory 217348 kb
Host smart-6a670974-037d-4162-b440-142c0bb3aa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724434377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3724434377
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1356332151
Short name T585
Test name
Test status
Simulation time 109788792 ps
CPU time 1.13 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 217420 kb
Host smart-360ae2f8-835d-4fc0-8b99-b997ff98ae55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356332151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1356332151
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2100517735
Short name T442
Test name
Test status
Simulation time 97312210 ps
CPU time 1.15 seconds
Started Aug 16 06:21:51 PM PDT 24
Finished Aug 16 06:21:53 PM PDT 24
Peak memory 219832 kb
Host smart-58f6bfe2-d739-4e3d-a24c-6495be399d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100517735 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2100517735
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.2687081142
Short name T58
Test name
Test status
Simulation time 38584052 ps
CPU time 0.85 seconds
Started Aug 16 06:21:42 PM PDT 24
Finished Aug 16 06:21:43 PM PDT 24
Peak memory 206564 kb
Host smart-98387de1-4f9c-4590-86d6-4859cd7e5247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687081142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2687081142
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.376356771
Short name T158
Test name
Test status
Simulation time 19837611 ps
CPU time 0.89 seconds
Started Aug 16 06:21:57 PM PDT 24
Finished Aug 16 06:21:58 PM PDT 24
Peak memory 215488 kb
Host smart-253add19-d9bc-4f0f-a43b-b944b3160dcf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376356771 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.376356771
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2289489471
Short name T101
Test name
Test status
Simulation time 66098192 ps
CPU time 1.11 seconds
Started Aug 16 06:21:42 PM PDT 24
Finished Aug 16 06:21:44 PM PDT 24
Peak memory 217024 kb
Host smart-a6de97d4-753b-4cf4-bc2d-76bf275513b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289489471 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2289489471
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1094185945
Short name T208
Test name
Test status
Simulation time 35546979 ps
CPU time 1.22 seconds
Started Aug 16 06:21:56 PM PDT 24
Finished Aug 16 06:21:57 PM PDT 24
Peak memory 229972 kb
Host smart-c80efee9-2ef3-47cf-a21b-4048ff0566f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094185945 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1094185945
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1420927853
Short name T624
Test name
Test status
Simulation time 47319639 ps
CPU time 1.27 seconds
Started Aug 16 06:22:13 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 218676 kb
Host smart-2cf1e847-143a-487e-91f9-52e7540344e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420927853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1420927853
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3736349577
Short name T3
Test name
Test status
Simulation time 24325686 ps
CPU time 0.94 seconds
Started Aug 16 06:21:47 PM PDT 24
Finished Aug 16 06:21:48 PM PDT 24
Peak memory 215756 kb
Host smart-fea611c5-4e4e-4325-b17b-d9b64c280e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736349577 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3736349577
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3986348640
Short name T568
Test name
Test status
Simulation time 73783915 ps
CPU time 0.91 seconds
Started Aug 16 06:22:08 PM PDT 24
Finished Aug 16 06:22:09 PM PDT 24
Peak memory 215332 kb
Host smart-135249bf-0176-404e-930f-d88b41fa4256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986348640 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3986348640
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2121754930
Short name T921
Test name
Test status
Simulation time 227233908 ps
CPU time 2.86 seconds
Started Aug 16 06:21:51 PM PDT 24
Finished Aug 16 06:21:54 PM PDT 24
Peak memory 215408 kb
Host smart-d6c0df0c-7ed9-4705-ba8a-0fcc53b1a9d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121754930 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2121754930
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.2207425915
Short name T862
Test name
Test status
Simulation time 31539377 ps
CPU time 1.05 seconds
Started Aug 16 06:23:09 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218620 kb
Host smart-d8dc46f6-06dc-4a2c-a2f8-2721b63545a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207425915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2207425915
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3517231694
Short name T338
Test name
Test status
Simulation time 38178434 ps
CPU time 1.39 seconds
Started Aug 16 06:23:08 PM PDT 24
Finished Aug 16 06:23:10 PM PDT 24
Peak memory 218488 kb
Host smart-e300ee7e-ed15-4c5d-bac6-416970b19c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517231694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3517231694
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2031078693
Short name T375
Test name
Test status
Simulation time 90132866 ps
CPU time 1.32 seconds
Started Aug 16 06:23:10 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 218868 kb
Host smart-39be2f8a-0a8e-45d4-a322-2300b1ea94d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031078693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2031078693
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3544578259
Short name T880
Test name
Test status
Simulation time 36647044 ps
CPU time 1.37 seconds
Started Aug 16 06:23:12 PM PDT 24
Finished Aug 16 06:23:13 PM PDT 24
Peak memory 218584 kb
Host smart-bd2f26a4-2836-4a09-a367-237ec77220d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544578259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3544578259
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2869417802
Short name T559
Test name
Test status
Simulation time 345936213 ps
CPU time 1.78 seconds
Started Aug 16 06:23:39 PM PDT 24
Finished Aug 16 06:23:41 PM PDT 24
Peak memory 220592 kb
Host smart-3b29fe4c-7439-4033-b22a-5f4ed4b7d868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869417802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2869417802
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1440629113
Short name T314
Test name
Test status
Simulation time 59364424 ps
CPU time 1.31 seconds
Started Aug 16 06:23:16 PM PDT 24
Finished Aug 16 06:23:18 PM PDT 24
Peak memory 219564 kb
Host smart-7e550e69-f7af-4ab9-bd21-51c46468df99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440629113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1440629113
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3834292129
Short name T399
Test name
Test status
Simulation time 78628509 ps
CPU time 1.47 seconds
Started Aug 16 06:23:11 PM PDT 24
Finished Aug 16 06:23:13 PM PDT 24
Peak memory 217396 kb
Host smart-817ccfb1-f1a4-4a8e-94be-003a227a2f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834292129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3834292129
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1152364165
Short name T551
Test name
Test status
Simulation time 79416793 ps
CPU time 1.47 seconds
Started Aug 16 06:23:16 PM PDT 24
Finished Aug 16 06:23:17 PM PDT 24
Peak memory 219136 kb
Host smart-db8dee99-3442-4428-a653-e70bf2958520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152364165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1152364165
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3300865097
Short name T805
Test name
Test status
Simulation time 56104228 ps
CPU time 1.28 seconds
Started Aug 16 06:23:30 PM PDT 24
Finished Aug 16 06:23:32 PM PDT 24
Peak memory 217388 kb
Host smart-192e72b8-6f4b-4083-b691-b5bc536e401f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300865097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3300865097
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.813699779
Short name T327
Test name
Test status
Simulation time 26247854 ps
CPU time 1.37 seconds
Started Aug 16 06:23:31 PM PDT 24
Finished Aug 16 06:23:32 PM PDT 24
Peak memory 218696 kb
Host smart-8b0f2f9b-1168-49bc-a98c-6d964799ffd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813699779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.813699779
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert_test.2835011150
Short name T599
Test name
Test status
Simulation time 16848969 ps
CPU time 0.94 seconds
Started Aug 16 06:21:04 PM PDT 24
Finished Aug 16 06:21:05 PM PDT 24
Peak memory 206788 kb
Host smart-9fe07aa2-8b57-48b9-99f5-efbbdf46488d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835011150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2835011150
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3226250624
Short name T870
Test name
Test status
Simulation time 11339445 ps
CPU time 0.88 seconds
Started Aug 16 06:21:03 PM PDT 24
Finished Aug 16 06:21:04 PM PDT 24
Peak memory 215400 kb
Host smart-603fc935-a87f-4127-8743-b38fac73bb18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226250624 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3226250624
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2116558286
Short name T246
Test name
Test status
Simulation time 57609591 ps
CPU time 1.22 seconds
Started Aug 16 06:20:56 PM PDT 24
Finished Aug 16 06:20:58 PM PDT 24
Peak memory 216964 kb
Host smart-61d92b08-3b43-455b-a32d-ac30d252a4f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116558286 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2116558286
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1093266217
Short name T928
Test name
Test status
Simulation time 34676377 ps
CPU time 0.99 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:07 PM PDT 24
Peak memory 218560 kb
Host smart-3e0a4364-345d-4d38-9ea3-c7ad06c8c734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093266217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1093266217
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.300394522
Short name T365
Test name
Test status
Simulation time 62565202 ps
CPU time 1.31 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:21:00 PM PDT 24
Peak memory 217280 kb
Host smart-89a0bff9-3619-4275-a1b6-f492b46b956a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300394522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.300394522
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.891251527
Short name T681
Test name
Test status
Simulation time 22647870 ps
CPU time 1.06 seconds
Started Aug 16 06:20:59 PM PDT 24
Finished Aug 16 06:21:00 PM PDT 24
Peak memory 207124 kb
Host smart-1135dc92-ca4f-45bb-8824-a25ee5615773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891251527 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.891251527
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2120767693
Short name T626
Test name
Test status
Simulation time 17214008 ps
CPU time 1.01 seconds
Started Aug 16 06:20:59 PM PDT 24
Finished Aug 16 06:21:00 PM PDT 24
Peak memory 215400 kb
Host smart-e94ef489-744c-4fe6-a337-ed7a252e5de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120767693 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2120767693
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.567545634
Short name T903
Test name
Test status
Simulation time 371630899 ps
CPU time 3.91 seconds
Started Aug 16 06:21:00 PM PDT 24
Finished Aug 16 06:21:04 PM PDT 24
Peak memory 215412 kb
Host smart-ba1344bd-c4ff-490d-a8b0-b4f61128e578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567545634 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.567545634
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_alert.4023829407
Short name T693
Test name
Test status
Simulation time 41029653 ps
CPU time 1.2 seconds
Started Aug 16 06:21:39 PM PDT 24
Finished Aug 16 06:21:40 PM PDT 24
Peak memory 218996 kb
Host smart-668ccb03-55fd-4713-92d6-86a21f0eee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023829407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.4023829407
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1450074972
Short name T786
Test name
Test status
Simulation time 30349058 ps
CPU time 1.2 seconds
Started Aug 16 06:22:09 PM PDT 24
Finished Aug 16 06:22:11 PM PDT 24
Peak memory 215256 kb
Host smart-1a9ac2d1-b96c-428e-8b42-f6b443e97189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450074972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1450074972
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3674808609
Short name T119
Test name
Test status
Simulation time 35640040 ps
CPU time 1.24 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:21:49 PM PDT 24
Peak memory 216788 kb
Host smart-4f0c0a69-3b53-4cc9-b6c4-32b642af9474
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674808609 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3674808609
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1780652686
Short name T435
Test name
Test status
Simulation time 56991041 ps
CPU time 1.34 seconds
Started Aug 16 06:21:44 PM PDT 24
Finished Aug 16 06:21:45 PM PDT 24
Peak memory 219572 kb
Host smart-418cb72e-8ac5-4a94-b2ec-f4c92c930590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780652686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1780652686
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1438157088
Short name T350
Test name
Test status
Simulation time 56131399 ps
CPU time 1.36 seconds
Started Aug 16 06:22:12 PM PDT 24
Finished Aug 16 06:22:14 PM PDT 24
Peak memory 220544 kb
Host smart-2e5fb37a-bf0f-493a-bdc4-dcc52a0992eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438157088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1438157088
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.50277320
Short name T86
Test name
Test status
Simulation time 42341393 ps
CPU time 0.9 seconds
Started Aug 16 06:21:43 PM PDT 24
Finished Aug 16 06:21:44 PM PDT 24
Peak memory 215744 kb
Host smart-6dfbc1ac-a041-4fea-aa14-5e899b5e4a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50277320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.50277320
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2276543737
Short name T431
Test name
Test status
Simulation time 28885877 ps
CPU time 0.96 seconds
Started Aug 16 06:21:55 PM PDT 24
Finished Aug 16 06:21:56 PM PDT 24
Peak memory 215384 kb
Host smart-e37e513b-75ff-447c-9a4f-6ceb53d9fe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276543737 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2276543737
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3182311095
Short name T836
Test name
Test status
Simulation time 374523981 ps
CPU time 1.67 seconds
Started Aug 16 06:21:58 PM PDT 24
Finished Aug 16 06:22:00 PM PDT 24
Peak memory 217484 kb
Host smart-4e7c517e-c80c-4421-978e-789cd218f543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182311095 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3182311095
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1567772087
Short name T225
Test name
Test status
Simulation time 10959758694 ps
CPU time 71 seconds
Started Aug 16 06:21:40 PM PDT 24
Finished Aug 16 06:22:51 PM PDT 24
Peak memory 219148 kb
Host smart-bd7cfd64-c9eb-4045-b4ec-845b9bd4b04e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567772087 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1567772087
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.292984226
Short name T696
Test name
Test status
Simulation time 55202066 ps
CPU time 1.33 seconds
Started Aug 16 06:21:41 PM PDT 24
Finished Aug 16 06:21:42 PM PDT 24
Peak memory 215692 kb
Host smart-3fd0b6f7-8e93-40bb-94c5-17dbd0c525a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292984226 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.292984226
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.417996035
Short name T545
Test name
Test status
Simulation time 17235110 ps
CPU time 0.98 seconds
Started Aug 16 06:21:43 PM PDT 24
Finished Aug 16 06:21:44 PM PDT 24
Peak memory 206816 kb
Host smart-1af8ac11-b7ba-41ed-9f08-d4119d28ef26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417996035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.417996035
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.4260548023
Short name T806
Test name
Test status
Simulation time 81177766 ps
CPU time 1.06 seconds
Started Aug 16 06:21:42 PM PDT 24
Finished Aug 16 06:21:43 PM PDT 24
Peak memory 218324 kb
Host smart-7500da3b-6ef7-4fa6-890e-5783a046d27b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260548023 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.4260548023
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.150402309
Short name T18
Test name
Test status
Simulation time 31365600 ps
CPU time 1.14 seconds
Started Aug 16 06:22:03 PM PDT 24
Finished Aug 16 06:22:04 PM PDT 24
Peak memory 219696 kb
Host smart-7fede1c6-7592-4093-9a0d-354864a60a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150402309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.150402309
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.591104488
Short name T309
Test name
Test status
Simulation time 324840760 ps
CPU time 3.52 seconds
Started Aug 16 06:21:49 PM PDT 24
Finished Aug 16 06:21:52 PM PDT 24
Peak memory 219196 kb
Host smart-6ea50814-b519-4254-b3bb-893f05b54d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591104488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.591104488
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.276648786
Short name T89
Test name
Test status
Simulation time 31950974 ps
CPU time 0.89 seconds
Started Aug 16 06:21:51 PM PDT 24
Finished Aug 16 06:21:52 PM PDT 24
Peak memory 215616 kb
Host smart-dc9973d5-bcf6-448a-bbcd-87816b4e719f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276648786 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.276648786
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.927554456
Short name T499
Test name
Test status
Simulation time 22881236 ps
CPU time 0.93 seconds
Started Aug 16 06:22:00 PM PDT 24
Finished Aug 16 06:22:01 PM PDT 24
Peak memory 215384 kb
Host smart-25040f3c-0f34-49db-ac46-1305cee2fbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927554456 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.927554456
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3447545798
Short name T738
Test name
Test status
Simulation time 142486664 ps
CPU time 1.29 seconds
Started Aug 16 06:21:47 PM PDT 24
Finished Aug 16 06:21:48 PM PDT 24
Peak memory 215372 kb
Host smart-20745053-31a0-4b87-a330-6245bb82a384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447545798 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3447545798
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.300434147
Short name T682
Test name
Test status
Simulation time 9938893213 ps
CPU time 90.57 seconds
Started Aug 16 06:21:57 PM PDT 24
Finished Aug 16 06:23:28 PM PDT 24
Peak memory 218424 kb
Host smart-7116d96f-aba9-4fc5-8d51-7162dfa6b7c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300434147 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.300434147
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2678545270
Short name T857
Test name
Test status
Simulation time 28037645 ps
CPU time 1.27 seconds
Started Aug 16 06:21:41 PM PDT 24
Finished Aug 16 06:21:43 PM PDT 24
Peak memory 218568 kb
Host smart-f5aa12b0-9df6-48d4-85bf-d96fd1e0ec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678545270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2678545270
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3417365145
Short name T352
Test name
Test status
Simulation time 34119603 ps
CPU time 0.96 seconds
Started Aug 16 06:21:44 PM PDT 24
Finished Aug 16 06:21:45 PM PDT 24
Peak memory 206776 kb
Host smart-23ea4879-f87c-4f4c-8f94-2dd4225f8db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417365145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3417365145
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2197314864
Short name T547
Test name
Test status
Simulation time 53369229 ps
CPU time 0.94 seconds
Started Aug 16 06:21:46 PM PDT 24
Finished Aug 16 06:21:47 PM PDT 24
Peak memory 215200 kb
Host smart-98aae175-df6b-4609-8fd2-b7d88d589286
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197314864 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2197314864
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1920119645
Short name T193
Test name
Test status
Simulation time 31695487 ps
CPU time 1.45 seconds
Started Aug 16 06:21:49 PM PDT 24
Finished Aug 16 06:21:50 PM PDT 24
Peak memory 218520 kb
Host smart-4e4aee1e-4c01-4ca2-9e47-e90ff28192a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920119645 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1920119645
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1160428012
Short name T620
Test name
Test status
Simulation time 51946139 ps
CPU time 1.13 seconds
Started Aug 16 06:21:38 PM PDT 24
Finished Aug 16 06:21:40 PM PDT 24
Peak memory 229940 kb
Host smart-62b4d7bb-f297-41fb-891f-99951ecb04d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160428012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1160428012
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2543121270
Short name T550
Test name
Test status
Simulation time 51336929 ps
CPU time 1.38 seconds
Started Aug 16 06:21:39 PM PDT 24
Finished Aug 16 06:21:41 PM PDT 24
Peak memory 218892 kb
Host smart-a9a82f2e-603b-4ca2-9754-e37239e0a67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543121270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2543121270
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.647579187
Short name T25
Test name
Test status
Simulation time 27421248 ps
CPU time 0.85 seconds
Started Aug 16 06:21:47 PM PDT 24
Finished Aug 16 06:21:48 PM PDT 24
Peak memory 215676 kb
Host smart-44f8cb0b-3746-489d-94a7-4330e72e3825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647579187 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.647579187
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.544310526
Short name T464
Test name
Test status
Simulation time 42750331 ps
CPU time 0.89 seconds
Started Aug 16 06:21:41 PM PDT 24
Finished Aug 16 06:21:42 PM PDT 24
Peak memory 215308 kb
Host smart-14f7be84-e500-4efc-a580-1af7de650f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544310526 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.544310526
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3777138576
Short name T875
Test name
Test status
Simulation time 86850475 ps
CPU time 2.33 seconds
Started Aug 16 06:21:57 PM PDT 24
Finished Aug 16 06:21:59 PM PDT 24
Peak memory 217280 kb
Host smart-6c5bfd87-e3dc-45a3-8a96-6591d2c1a25c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777138576 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3777138576
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.965279775
Short name T227
Test name
Test status
Simulation time 31062413439 ps
CPU time 99.33 seconds
Started Aug 16 06:21:42 PM PDT 24
Finished Aug 16 06:23:21 PM PDT 24
Peak memory 218624 kb
Host smart-49579093-89cc-4862-9017-23aacbb7e3fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965279775 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.965279775
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.241005103
Short name T775
Test name
Test status
Simulation time 60578700 ps
CPU time 1.21 seconds
Started Aug 16 06:21:44 PM PDT 24
Finished Aug 16 06:21:46 PM PDT 24
Peak memory 219704 kb
Host smart-e1b59444-b368-4c2f-a54b-8bcc71ea53f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241005103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.241005103
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3045645118
Short name T479
Test name
Test status
Simulation time 63852490 ps
CPU time 0.94 seconds
Started Aug 16 06:21:45 PM PDT 24
Finished Aug 16 06:21:46 PM PDT 24
Peak memory 215024 kb
Host smart-ec73253d-fced-45a8-9759-fb16557ec6a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045645118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3045645118
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.4026755917
Short name T759
Test name
Test status
Simulation time 44639846 ps
CPU time 0.84 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:05 PM PDT 24
Peak memory 215440 kb
Host smart-5c3cecd5-cbe1-42c7-9eae-3c532fe718f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026755917 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.4026755917
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2887200207
Short name T96
Test name
Test status
Simulation time 32061278 ps
CPU time 0.98 seconds
Started Aug 16 06:21:55 PM PDT 24
Finished Aug 16 06:21:56 PM PDT 24
Peak memory 216920 kb
Host smart-2f1d2f92-19a0-4638-86f6-ea2dfb5e1723
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887200207 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2887200207
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2526441352
Short name T111
Test name
Test status
Simulation time 68570444 ps
CPU time 1.01 seconds
Started Aug 16 06:21:44 PM PDT 24
Finished Aug 16 06:21:45 PM PDT 24
Peak memory 220492 kb
Host smart-8a133b6a-c909-42b4-8b93-5eba68b5e872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526441352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2526441352
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3971851616
Short name T543
Test name
Test status
Simulation time 63486731 ps
CPU time 1.51 seconds
Started Aug 16 06:21:45 PM PDT 24
Finished Aug 16 06:21:47 PM PDT 24
Peak memory 217332 kb
Host smart-a3ea0f6f-c6d2-4756-8aa9-8999d174da5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971851616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3971851616
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1964567014
Short name T484
Test name
Test status
Simulation time 21598775 ps
CPU time 1.15 seconds
Started Aug 16 06:21:44 PM PDT 24
Finished Aug 16 06:21:45 PM PDT 24
Peak memory 215492 kb
Host smart-3c969f9e-c715-4507-aff3-ab26b5c73226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964567014 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1964567014
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1873528951
Short name T485
Test name
Test status
Simulation time 28958673 ps
CPU time 0.96 seconds
Started Aug 16 06:21:58 PM PDT 24
Finished Aug 16 06:21:59 PM PDT 24
Peak memory 215392 kb
Host smart-194ff4c9-ba99-4993-92cc-7727b37efd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873528951 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1873528951
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.4024417127
Short name T868
Test name
Test status
Simulation time 627697421 ps
CPU time 3.98 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:21:52 PM PDT 24
Peak memory 215372 kb
Host smart-24824482-c3a5-42ea-8a20-7a6c716fe3e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024417127 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.4024417127
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3714053158
Short name T228
Test name
Test status
Simulation time 16947797485 ps
CPU time 110.08 seconds
Started Aug 16 06:21:53 PM PDT 24
Finished Aug 16 06:23:43 PM PDT 24
Peak memory 222372 kb
Host smart-0ba0ce04-b575-4495-bd75-059104cd580c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714053158 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3714053158
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1179158177
Short name T243
Test name
Test status
Simulation time 52749723 ps
CPU time 1.34 seconds
Started Aug 16 06:21:58 PM PDT 24
Finished Aug 16 06:22:00 PM PDT 24
Peak memory 215752 kb
Host smart-a1f10553-2245-499b-bfea-db070ec30992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179158177 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1179158177
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.363865509
Short name T717
Test name
Test status
Simulation time 33492245 ps
CPU time 1.01 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:21:50 PM PDT 24
Peak memory 214988 kb
Host smart-6e53c345-ecb1-42c6-b460-25be2b97de39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363865509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.363865509
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2233772981
Short name T450
Test name
Test status
Simulation time 16285405 ps
CPU time 0.89 seconds
Started Aug 16 06:21:57 PM PDT 24
Finished Aug 16 06:21:58 PM PDT 24
Peak memory 215604 kb
Host smart-f4bfab2b-5204-4ec5-9cfd-d0f25266e810
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233772981 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2233772981
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.21478334
Short name T145
Test name
Test status
Simulation time 68745713 ps
CPU time 1.24 seconds
Started Aug 16 06:21:46 PM PDT 24
Finished Aug 16 06:21:48 PM PDT 24
Peak memory 216980 kb
Host smart-c7dd57d8-3996-407e-b88c-3cef2c35f577
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21478334 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_dis
able_auto_req_mode.21478334
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3588105453
Short name T124
Test name
Test status
Simulation time 137467108 ps
CPU time 1.05 seconds
Started Aug 16 06:22:08 PM PDT 24
Finished Aug 16 06:22:09 PM PDT 24
Peak memory 217460 kb
Host smart-456b4d1c-1ae0-439b-9da6-b552efa5a27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588105453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3588105453
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.875833874
Short name T702
Test name
Test status
Simulation time 27607636 ps
CPU time 1.29 seconds
Started Aug 16 06:21:57 PM PDT 24
Finished Aug 16 06:21:58 PM PDT 24
Peak memory 217476 kb
Host smart-4860e2b6-6a8e-4da9-a2ed-fa223b418459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875833874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.875833874
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1563398067
Short name T84
Test name
Test status
Simulation time 29730528 ps
CPU time 1.02 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:21:49 PM PDT 24
Peak memory 215896 kb
Host smart-dae2aa8f-4719-4044-9ee9-71ee38e7ceca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563398067 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1563398067
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3610570089
Short name T544
Test name
Test status
Simulation time 30267842 ps
CPU time 0.91 seconds
Started Aug 16 06:21:58 PM PDT 24
Finished Aug 16 06:21:59 PM PDT 24
Peak memory 215348 kb
Host smart-7c8fecee-7664-4de1-9368-1120ab7449d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610570089 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3610570089
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4289010925
Short name T658
Test name
Test status
Simulation time 278303769 ps
CPU time 3.43 seconds
Started Aug 16 06:21:47 PM PDT 24
Finished Aug 16 06:21:51 PM PDT 24
Peak memory 217320 kb
Host smart-165dcdbd-6f46-475a-a4bb-119727d23855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289010925 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4289010925
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.1445041807
Short name T685
Test name
Test status
Simulation time 89465779 ps
CPU time 1.26 seconds
Started Aug 16 06:22:12 PM PDT 24
Finished Aug 16 06:22:13 PM PDT 24
Peak memory 219532 kb
Host smart-113f5320-099a-4e5e-bcef-1dfdef90f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445041807 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1445041807
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1356529052
Short name T659
Test name
Test status
Simulation time 21011672 ps
CPU time 0.87 seconds
Started Aug 16 06:21:45 PM PDT 24
Finished Aug 16 06:21:46 PM PDT 24
Peak memory 214804 kb
Host smart-d7c51ee0-dd76-4d76-92fb-3161146197a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356529052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1356529052
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1199335961
Short name T290
Test name
Test status
Simulation time 23682949 ps
CPU time 0.89 seconds
Started Aug 16 06:22:07 PM PDT 24
Finished Aug 16 06:22:08 PM PDT 24
Peak memory 207112 kb
Host smart-e754d786-a4fe-4b2b-b556-1eda3eb8c523
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199335961 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1199335961
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.477581196
Short name T493
Test name
Test status
Simulation time 43317943 ps
CPU time 1.41 seconds
Started Aug 16 06:21:59 PM PDT 24
Finished Aug 16 06:22:00 PM PDT 24
Peak memory 217164 kb
Host smart-62ab5fea-240b-45c3-9b31-b8f5ab95f31d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477581196 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.477581196
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.141718642
Short name T186
Test name
Test status
Simulation time 39185414 ps
CPU time 1.04 seconds
Started Aug 16 06:21:46 PM PDT 24
Finished Aug 16 06:21:47 PM PDT 24
Peak memory 223960 kb
Host smart-2e7876ea-35c6-4aef-bcb3-9a52da0d70c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141718642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.141718642
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2439951889
Short name T276
Test name
Test status
Simulation time 58891821 ps
CPU time 1.21 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:06 PM PDT 24
Peak memory 218460 kb
Host smart-8d03a1fc-f4f7-4589-8d73-dd401ad0a0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439951889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2439951889
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.322722257
Short name T81
Test name
Test status
Simulation time 31441902 ps
CPU time 1.19 seconds
Started Aug 16 06:22:10 PM PDT 24
Finished Aug 16 06:22:11 PM PDT 24
Peak memory 216984 kb
Host smart-52fe3cc4-c1c9-4a6a-9574-828a3818f9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322722257 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.322722257
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3427552281
Short name T711
Test name
Test status
Simulation time 49275764 ps
CPU time 0.97 seconds
Started Aug 16 06:21:45 PM PDT 24
Finished Aug 16 06:21:47 PM PDT 24
Peak memory 215460 kb
Host smart-07ba088f-fa39-4c6b-9b20-aecf357b62a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427552281 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3427552281
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.130697056
Short name T940
Test name
Test status
Simulation time 1186915867 ps
CPU time 3.45 seconds
Started Aug 16 06:21:56 PM PDT 24
Finished Aug 16 06:22:00 PM PDT 24
Peak memory 217436 kb
Host smart-9282a2c5-72e1-46bf-b737-151726bdc1fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130697056 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.130697056
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1581477429
Short name T835
Test name
Test status
Simulation time 3369473242 ps
CPU time 44.17 seconds
Started Aug 16 06:21:51 PM PDT 24
Finished Aug 16 06:22:35 PM PDT 24
Peak memory 217656 kb
Host smart-4157d121-4a73-42a8-8dd4-33571752bb61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581477429 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1581477429
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2826063720
Short name T639
Test name
Test status
Simulation time 83365652 ps
CPU time 1.1 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:21:49 PM PDT 24
Peak memory 219372 kb
Host smart-83e8aa87-877e-4705-942b-80d0b0e91502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826063720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2826063720
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3293435610
Short name T387
Test name
Test status
Simulation time 28466438 ps
CPU time 0.91 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:05 PM PDT 24
Peak memory 206780 kb
Host smart-79bdb018-78d3-4b98-8392-7904e474ea3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293435610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3293435610
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.908965938
Short name T152
Test name
Test status
Simulation time 19171415 ps
CPU time 0.85 seconds
Started Aug 16 06:22:10 PM PDT 24
Finished Aug 16 06:22:11 PM PDT 24
Peak memory 215420 kb
Host smart-c3cc96ea-4de6-45e4-983b-bcc9773a6c48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908965938 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.908965938
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.929652268
Short name T140
Test name
Test status
Simulation time 93018928 ps
CPU time 1.29 seconds
Started Aug 16 06:21:46 PM PDT 24
Finished Aug 16 06:21:47 PM PDT 24
Peak memory 216932 kb
Host smart-69646e54-0799-4701-9414-1533967ce83f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929652268 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.929652268
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_genbits.3980348272
Short name T306
Test name
Test status
Simulation time 69398240 ps
CPU time 1.33 seconds
Started Aug 16 06:21:46 PM PDT 24
Finished Aug 16 06:21:47 PM PDT 24
Peak memory 219096 kb
Host smart-42defb80-4596-4134-b553-4a1499bb86e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980348272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3980348272
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.578661534
Short name T881
Test name
Test status
Simulation time 38894673 ps
CPU time 1 seconds
Started Aug 16 06:21:45 PM PDT 24
Finished Aug 16 06:21:46 PM PDT 24
Peak memory 224020 kb
Host smart-a2f69788-901e-45c1-a380-712bb31dd0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578661534 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.578661534
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1389437768
Short name T586
Test name
Test status
Simulation time 57469517 ps
CPU time 0.89 seconds
Started Aug 16 06:21:44 PM PDT 24
Finished Aug 16 06:21:45 PM PDT 24
Peak memory 215164 kb
Host smart-2164b515-346d-4a75-9bdb-e2e3e8571399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389437768 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1389437768
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2343720464
Short name T488
Test name
Test status
Simulation time 352654138 ps
CPU time 6.89 seconds
Started Aug 16 06:21:45 PM PDT 24
Finished Aug 16 06:21:52 PM PDT 24
Peak memory 220556 kb
Host smart-6077211f-f320-418c-a346-1b62daa1c58f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343720464 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2343720464
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.27607623
Short name T374
Test name
Test status
Simulation time 106778712 ps
CPU time 1.21 seconds
Started Aug 16 06:21:55 PM PDT 24
Finished Aug 16 06:21:56 PM PDT 24
Peak memory 215776 kb
Host smart-d71d76a3-1067-4edb-819c-02626c109a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27607623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.27607623
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.965278268
Short name T467
Test name
Test status
Simulation time 45432997 ps
CPU time 0.89 seconds
Started Aug 16 06:21:45 PM PDT 24
Finished Aug 16 06:21:46 PM PDT 24
Peak memory 206796 kb
Host smart-038c9c6a-78ea-4a29-b541-493347bd0c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965278268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.965278268
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.484801758
Short name T854
Test name
Test status
Simulation time 39638763 ps
CPU time 0.89 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:21:49 PM PDT 24
Peak memory 215420 kb
Host smart-4cf1ecd5-cec2-4278-8b47-b2546a35d9c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484801758 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.484801758
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.994218368
Short name T130
Test name
Test status
Simulation time 68158840 ps
CPU time 1.08 seconds
Started Aug 16 06:21:56 PM PDT 24
Finished Aug 16 06:21:57 PM PDT 24
Peak memory 216980 kb
Host smart-778c267e-b450-43e0-8d48-d3287f21f5e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994218368 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.994218368
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_genbits.1857683485
Short name T427
Test name
Test status
Simulation time 63347408 ps
CPU time 1.13 seconds
Started Aug 16 06:21:46 PM PDT 24
Finished Aug 16 06:21:47 PM PDT 24
Peak memory 219276 kb
Host smart-f0399b25-ef77-43cf-8880-de3478bfc57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857683485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1857683485
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3036039093
Short name T24
Test name
Test status
Simulation time 42135244 ps
CPU time 0.87 seconds
Started Aug 16 06:21:47 PM PDT 24
Finished Aug 16 06:21:48 PM PDT 24
Peak memory 215728 kb
Host smart-9e3bfb0a-67cd-4e38-aed5-23b5f37ad91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036039093 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3036039093
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.4090075345
Short name T766
Test name
Test status
Simulation time 52622456 ps
CPU time 0.9 seconds
Started Aug 16 06:22:14 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 215276 kb
Host smart-366b14c8-ccdf-4db4-90a8-95410c05262e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090075345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.4090075345
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1197239589
Short name T644
Test name
Test status
Simulation time 176646795 ps
CPU time 1.58 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:06 PM PDT 24
Peak memory 219676 kb
Host smart-00f303d4-8f6d-4674-9923-9c6ac9d48b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197239589 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1197239589
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_alert.3264377418
Short name T665
Test name
Test status
Simulation time 30191101 ps
CPU time 1.3 seconds
Started Aug 16 06:21:57 PM PDT 24
Finished Aug 16 06:21:58 PM PDT 24
Peak memory 218832 kb
Host smart-57bfe617-4a84-42bd-a54c-c2dbaec27161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264377418 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3264377418
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1799523622
Short name T487
Test name
Test status
Simulation time 81853945 ps
CPU time 0.9 seconds
Started Aug 16 06:21:46 PM PDT 24
Finished Aug 16 06:21:47 PM PDT 24
Peak memory 214980 kb
Host smart-11ea0cbf-87ac-42a5-be0f-da5c6ace3131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799523622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1799523622
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3459191896
Short name T196
Test name
Test status
Simulation time 13872113 ps
CPU time 0.93 seconds
Started Aug 16 06:21:47 PM PDT 24
Finished Aug 16 06:21:48 PM PDT 24
Peak memory 215560 kb
Host smart-735f5041-f678-4a1e-a2d6-119e18244d8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459191896 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3459191896
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1381406794
Short name T943
Test name
Test status
Simulation time 48620850 ps
CPU time 1.07 seconds
Started Aug 16 06:21:45 PM PDT 24
Finished Aug 16 06:21:47 PM PDT 24
Peak memory 218616 kb
Host smart-c9805131-493b-4885-a17d-1ffc6a208776
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381406794 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1381406794
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.882514931
Short name T122
Test name
Test status
Simulation time 34395602 ps
CPU time 1.07 seconds
Started Aug 16 06:22:07 PM PDT 24
Finished Aug 16 06:22:08 PM PDT 24
Peak memory 220656 kb
Host smart-0c5b88d1-4d25-4d5b-82a3-ea95aa006a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882514931 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.882514931
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3445017623
Short name T526
Test name
Test status
Simulation time 34625678 ps
CPU time 1.37 seconds
Started Aug 16 06:22:05 PM PDT 24
Finished Aug 16 06:22:06 PM PDT 24
Peak memory 218668 kb
Host smart-fe6b3545-165f-48e6-a8be-0be2d1129f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445017623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3445017623
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1753146507
Short name T927
Test name
Test status
Simulation time 33429757 ps
CPU time 0.92 seconds
Started Aug 16 06:22:13 PM PDT 24
Finished Aug 16 06:22:14 PM PDT 24
Peak memory 215796 kb
Host smart-22954665-3a37-457d-b29e-8de5ef700659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753146507 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1753146507
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1583925327
Short name T336
Test name
Test status
Simulation time 30792485 ps
CPU time 0.98 seconds
Started Aug 16 06:21:47 PM PDT 24
Finished Aug 16 06:21:48 PM PDT 24
Peak memory 215348 kb
Host smart-10673781-01e1-428f-a077-98d5add24eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583925327 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1583925327
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.647251863
Short name T948
Test name
Test status
Simulation time 938331667 ps
CPU time 5.22 seconds
Started Aug 16 06:22:09 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 217336 kb
Host smart-1d4e53d3-65f8-4a78-ac5b-d229b6548a42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647251863 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.647251863
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2170600334
Short name T232
Test name
Test status
Simulation time 1132717855 ps
CPU time 27.95 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:32 PM PDT 24
Peak memory 220140 kb
Host smart-45c905cf-0092-4bb6-b4c5-d793e0208568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170600334 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2170600334
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3470253626
Short name T78
Test name
Test status
Simulation time 29927428 ps
CPU time 1.32 seconds
Started Aug 16 06:21:57 PM PDT 24
Finished Aug 16 06:21:58 PM PDT 24
Peak memory 218860 kb
Host smart-daabe775-28cb-413b-9cac-b2ecbf07c546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470253626 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3470253626
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3457015360
Short name T418
Test name
Test status
Simulation time 67297714 ps
CPU time 0.88 seconds
Started Aug 16 06:22:12 PM PDT 24
Finished Aug 16 06:22:13 PM PDT 24
Peak memory 214916 kb
Host smart-f34e8575-ef16-452d-9abd-9eed158f147e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457015360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3457015360
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1356928154
Short name T754
Test name
Test status
Simulation time 58190689 ps
CPU time 0.81 seconds
Started Aug 16 06:21:57 PM PDT 24
Finished Aug 16 06:21:58 PM PDT 24
Peak memory 215396 kb
Host smart-5592052d-1c25-4bdb-9e39-21135854f4ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356928154 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1356928154
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.886111624
Short name T612
Test name
Test status
Simulation time 294663936 ps
CPU time 1.21 seconds
Started Aug 16 06:22:09 PM PDT 24
Finished Aug 16 06:22:11 PM PDT 24
Peak memory 219480 kb
Host smart-c73120c6-c63e-410b-a29c-6adcd5c9bddc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886111624 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.886111624
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1536433583
Short name T137
Test name
Test status
Simulation time 36574213 ps
CPU time 1.07 seconds
Started Aug 16 06:21:57 PM PDT 24
Finished Aug 16 06:21:58 PM PDT 24
Peak memory 220744 kb
Host smart-c14a98d8-ba8e-49fa-a7b9-d703caa6f926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536433583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1536433583
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2704153750
Short name T605
Test name
Test status
Simulation time 69739933 ps
CPU time 1.05 seconds
Started Aug 16 06:22:10 PM PDT 24
Finished Aug 16 06:22:11 PM PDT 24
Peak memory 217472 kb
Host smart-262d1343-8296-47ee-857b-c29e6d8744f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704153750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2704153750
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4198256024
Short name T822
Test name
Test status
Simulation time 25051531 ps
CPU time 1.16 seconds
Started Aug 16 06:21:48 PM PDT 24
Finished Aug 16 06:21:49 PM PDT 24
Peak memory 215604 kb
Host smart-dbbb4b02-0925-4b25-945b-9adb89b412e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198256024 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4198256024
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2326508537
Short name T546
Test name
Test status
Simulation time 16199722 ps
CPU time 1 seconds
Started Aug 16 06:22:10 PM PDT 24
Finished Aug 16 06:22:11 PM PDT 24
Peak memory 215352 kb
Host smart-12eb48e8-cafd-467a-8367-13e574ef46ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326508537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2326508537
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3858061383
Short name T615
Test name
Test status
Simulation time 309297397 ps
CPU time 6.69 seconds
Started Aug 16 06:21:44 PM PDT 24
Finished Aug 16 06:21:50 PM PDT 24
Peak memory 217396 kb
Host smart-951fefdf-6ed4-4d27-9874-dde77377d67c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858061383 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3858061383
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_alert.4027643733
Short name T648
Test name
Test status
Simulation time 42438918 ps
CPU time 1.22 seconds
Started Aug 16 06:21:23 PM PDT 24
Finished Aug 16 06:21:25 PM PDT 24
Peak memory 219264 kb
Host smart-c4f405f5-b5ab-4cad-96c3-5e9024ca07bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027643733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.4027643733
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.4050405842
Short name T730
Test name
Test status
Simulation time 126850936 ps
CPU time 0.88 seconds
Started Aug 16 06:21:19 PM PDT 24
Finished Aug 16 06:21:20 PM PDT 24
Peak memory 206776 kb
Host smart-bf4a927a-cf93-4310-b4e9-9c7242edec6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050405842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.4050405842
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1853354814
Short name T397
Test name
Test status
Simulation time 33953206 ps
CPU time 0.88 seconds
Started Aug 16 06:21:08 PM PDT 24
Finished Aug 16 06:21:09 PM PDT 24
Peak memory 215136 kb
Host smart-d3573f15-86db-40b0-a590-733ba5d5c237
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853354814 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1853354814
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2053704335
Short name T138
Test name
Test status
Simulation time 43716260 ps
CPU time 1.42 seconds
Started Aug 16 06:21:10 PM PDT 24
Finished Aug 16 06:21:11 PM PDT 24
Peak memory 216968 kb
Host smart-952c2813-9abc-44d0-b638-b895b0fb5d44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053704335 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2053704335
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2566237561
Short name T426
Test name
Test status
Simulation time 36804748 ps
CPU time 1.13 seconds
Started Aug 16 06:21:07 PM PDT 24
Finished Aug 16 06:21:09 PM PDT 24
Peak memory 218728 kb
Host smart-60481287-3f83-42fc-bb90-c99f57112e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566237561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2566237561
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.604807766
Short name T372
Test name
Test status
Simulation time 340403256 ps
CPU time 3.69 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:10 PM PDT 24
Peak memory 220240 kb
Host smart-131f28a9-00da-41e6-b2e4-54351a097521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604807766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.604807766
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3374818907
Short name T107
Test name
Test status
Simulation time 28791170 ps
CPU time 0.98 seconds
Started Aug 16 06:21:05 PM PDT 24
Finished Aug 16 06:21:06 PM PDT 24
Peak memory 215900 kb
Host smart-6d30d29a-ce32-4516-9e8c-158277cfb1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374818907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3374818907
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2350286038
Short name T970
Test name
Test status
Simulation time 17515335 ps
CPU time 1 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:07 PM PDT 24
Peak memory 207164 kb
Host smart-1e66fb9e-5e45-40ea-85e9-4814b670ae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350286038 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2350286038
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2938300386
Short name T55
Test name
Test status
Simulation time 254940214 ps
CPU time 4.92 seconds
Started Aug 16 06:21:07 PM PDT 24
Finished Aug 16 06:21:12 PM PDT 24
Peak memory 235248 kb
Host smart-5ac775a0-9231-4bc0-bfe2-205093300db9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938300386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2938300386
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1341398266
Short name T344
Test name
Test status
Simulation time 54894483 ps
CPU time 0.97 seconds
Started Aug 16 06:20:58 PM PDT 24
Finished Aug 16 06:20:59 PM PDT 24
Peak memory 215372 kb
Host smart-09d17131-8d42-45f5-85fe-1163f6cb2405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341398266 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1341398266
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1688653408
Short name T866
Test name
Test status
Simulation time 280591407 ps
CPU time 5.7 seconds
Started Aug 16 06:21:04 PM PDT 24
Finished Aug 16 06:21:10 PM PDT 24
Peak memory 217148 kb
Host smart-e4b2f60f-ae90-492f-8cca-02cf9d9d77ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688653408 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1688653408
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_alert.432277783
Short name T968
Test name
Test status
Simulation time 175688751 ps
CPU time 1.29 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:06 PM PDT 24
Peak memory 220584 kb
Host smart-c624f781-9878-4e2d-b330-e77824c43ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432277783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.432277783
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3145903086
Short name T874
Test name
Test status
Simulation time 44219921 ps
CPU time 0.86 seconds
Started Aug 16 06:22:09 PM PDT 24
Finished Aug 16 06:22:10 PM PDT 24
Peak memory 206584 kb
Host smart-4ddc111e-16a8-487d-984a-fecf9703f2e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145903086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3145903086
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.169138625
Short name T878
Test name
Test status
Simulation time 114596130 ps
CPU time 1.07 seconds
Started Aug 16 06:21:56 PM PDT 24
Finished Aug 16 06:21:58 PM PDT 24
Peak memory 215312 kb
Host smart-3dca14cc-3cfc-4732-b03b-c0138f24107a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169138625 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.169138625
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.159525230
Short name T794
Test name
Test status
Simulation time 19485547 ps
CPU time 1.03 seconds
Started Aug 16 06:21:54 PM PDT 24
Finished Aug 16 06:21:55 PM PDT 24
Peak memory 218328 kb
Host smart-2104f966-5c69-4c0f-a391-8262c40b8ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159525230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.159525230
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3840153563
Short name T708
Test name
Test status
Simulation time 54078819 ps
CPU time 1.61 seconds
Started Aug 16 06:21:56 PM PDT 24
Finished Aug 16 06:21:58 PM PDT 24
Peak memory 218576 kb
Host smart-971fa155-61c8-4845-8ee4-93e39e06dfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840153563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3840153563
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2962008493
Short name T495
Test name
Test status
Simulation time 29027384 ps
CPU time 0.95 seconds
Started Aug 16 06:22:03 PM PDT 24
Finished Aug 16 06:22:04 PM PDT 24
Peak memory 215600 kb
Host smart-bdd99b2e-8d9e-4049-adfd-22351c720890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962008493 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2962008493
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2816545542
Short name T335
Test name
Test status
Simulation time 66524390 ps
CPU time 0.88 seconds
Started Aug 16 06:21:55 PM PDT 24
Finished Aug 16 06:21:56 PM PDT 24
Peak memory 215380 kb
Host smart-053a6c99-f6f2-4885-a150-6804be882fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816545542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2816545542
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2876705339
Short name T709
Test name
Test status
Simulation time 164805902 ps
CPU time 2.18 seconds
Started Aug 16 06:22:14 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 217228 kb
Host smart-28e32ca4-f874-4841-83b0-83998d7cc7ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876705339 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2876705339
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3868351989
Short name T229
Test name
Test status
Simulation time 3387889013 ps
CPU time 78.16 seconds
Started Aug 16 06:21:54 PM PDT 24
Finished Aug 16 06:23:12 PM PDT 24
Peak memory 217528 kb
Host smart-ac5bef0d-3cfa-4447-a01d-265f9150e1d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868351989 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3868351989
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.280930868
Short name T452
Test name
Test status
Simulation time 24875693 ps
CPU time 1.25 seconds
Started Aug 16 06:21:56 PM PDT 24
Finished Aug 16 06:21:57 PM PDT 24
Peak memory 219820 kb
Host smart-877a78c7-78e9-4546-a474-edde47ca6132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280930868 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.280930868
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2191344740
Short name T876
Test name
Test status
Simulation time 46529662 ps
CPU time 0.87 seconds
Started Aug 16 06:22:14 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 206776 kb
Host smart-37b16887-b0cb-4746-925e-b9df5ca4ec4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191344740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2191344740
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1009810784
Short name T938
Test name
Test status
Simulation time 12631980 ps
CPU time 0.95 seconds
Started Aug 16 06:22:13 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 215376 kb
Host smart-6bde4919-fb85-435f-b30d-f061c4cb3dcf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009810784 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1009810784
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.227150666
Short name T614
Test name
Test status
Simulation time 28887418 ps
CPU time 1.13 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:20 PM PDT 24
Peak memory 218536 kb
Host smart-da0dc1dc-d5c4-4feb-9516-f17ed6c1dd54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227150666 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.227150666
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3311319908
Short name T727
Test name
Test status
Simulation time 20048699 ps
CPU time 1.12 seconds
Started Aug 16 06:22:09 PM PDT 24
Finished Aug 16 06:22:10 PM PDT 24
Peak memory 218692 kb
Host smart-9483b896-3c0d-44e2-aa8c-3dbf338b08f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311319908 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3311319908
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3997337305
Short name T303
Test name
Test status
Simulation time 127645905 ps
CPU time 1.68 seconds
Started Aug 16 06:22:10 PM PDT 24
Finished Aug 16 06:22:12 PM PDT 24
Peak memory 215508 kb
Host smart-c7596e74-04ed-4aa5-8b43-d2d29cfdf922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997337305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3997337305
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1723598559
Short name T26
Test name
Test status
Simulation time 29743474 ps
CPU time 0.86 seconds
Started Aug 16 06:21:56 PM PDT 24
Finished Aug 16 06:21:57 PM PDT 24
Peak memory 215888 kb
Host smart-ea07ac50-9263-401f-a457-41db7fd75325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723598559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1723598559
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1772735380
Short name T811
Test name
Test status
Simulation time 22294590 ps
CPU time 0.91 seconds
Started Aug 16 06:22:07 PM PDT 24
Finished Aug 16 06:22:08 PM PDT 24
Peak memory 215356 kb
Host smart-0e072e62-1319-4e08-b989-3bc2a4b47fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772735380 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1772735380
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.439240500
Short name T44
Test name
Test status
Simulation time 1277005664 ps
CPU time 5.05 seconds
Started Aug 16 06:22:01 PM PDT 24
Finished Aug 16 06:22:06 PM PDT 24
Peak memory 215304 kb
Host smart-566f57b9-21f7-43b9-b286-d57e1593b576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439240500 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.439240500
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert.4235641666
Short name T694
Test name
Test status
Simulation time 65204827 ps
CPU time 1.19 seconds
Started Aug 16 06:21:57 PM PDT 24
Finished Aug 16 06:21:58 PM PDT 24
Peak memory 218668 kb
Host smart-0c942158-27bb-417f-835b-3359f8d0796f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235641666 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.4235641666
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3662628365
Short name T894
Test name
Test status
Simulation time 58071822 ps
CPU time 0.9 seconds
Started Aug 16 06:21:58 PM PDT 24
Finished Aug 16 06:21:59 PM PDT 24
Peak memory 206772 kb
Host smart-ecbb6a93-86c9-4c4f-9a87-5f27695d9639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662628365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3662628365
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3419886261
Short name T616
Test name
Test status
Simulation time 35123292 ps
CPU time 0.84 seconds
Started Aug 16 06:22:16 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 215444 kb
Host smart-ca8108be-5209-4e7a-8d89-4e12f8ab13c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419886261 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3419886261
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.4142147696
Short name T596
Test name
Test status
Simulation time 71203758 ps
CPU time 1 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:05 PM PDT 24
Peak memory 216896 kb
Host smart-e3dd5826-9d41-4e50-b9ab-8e6768231a05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142147696 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.4142147696
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1847371253
Short name T651
Test name
Test status
Simulation time 133520015 ps
CPU time 1.05 seconds
Started Aug 16 06:22:12 PM PDT 24
Finished Aug 16 06:22:13 PM PDT 24
Peak memory 219676 kb
Host smart-7c53b79b-9bac-4fbf-b002-56a42adb4fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847371253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1847371253
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2854008916
Short name T757
Test name
Test status
Simulation time 57919370 ps
CPU time 1.32 seconds
Started Aug 16 06:21:56 PM PDT 24
Finished Aug 16 06:21:57 PM PDT 24
Peak memory 217424 kb
Host smart-11015e03-3004-4731-ad3c-21727d53b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854008916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2854008916
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3467718784
Short name T750
Test name
Test status
Simulation time 39391499 ps
CPU time 0.89 seconds
Started Aug 16 06:21:55 PM PDT 24
Finished Aug 16 06:21:56 PM PDT 24
Peak memory 215596 kb
Host smart-f76f8548-5ae6-4439-8d53-44803199cd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467718784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3467718784
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3281597020
Short name T556
Test name
Test status
Simulation time 26613919 ps
CPU time 0.91 seconds
Started Aug 16 06:22:12 PM PDT 24
Finished Aug 16 06:22:14 PM PDT 24
Peak memory 215356 kb
Host smart-0164bd83-b210-4631-a22a-ce56eae55114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281597020 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3281597020
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.712203681
Short name T890
Test name
Test status
Simulation time 678473340 ps
CPU time 7.06 seconds
Started Aug 16 06:22:05 PM PDT 24
Finished Aug 16 06:22:12 PM PDT 24
Peak memory 220104 kb
Host smart-2916cf54-dba4-4925-9c80-b850846563c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712203681 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.712203681
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1572969927
Short name T729
Test name
Test status
Simulation time 1469319712 ps
CPU time 41.6 seconds
Started Aug 16 06:22:13 PM PDT 24
Finished Aug 16 06:22:55 PM PDT 24
Peak memory 215528 kb
Host smart-c972fc32-9c03-4167-8051-5eb9fd5b050e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572969927 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1572969927
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3462873351
Short name T132
Test name
Test status
Simulation time 35528660 ps
CPU time 1.08 seconds
Started Aug 16 06:22:11 PM PDT 24
Finished Aug 16 06:22:12 PM PDT 24
Peak memory 220776 kb
Host smart-a51e67fd-ca5a-4d1e-849a-7f2afda23436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462873351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3462873351
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2904802315
Short name T540
Test name
Test status
Simulation time 24555877 ps
CPU time 0.95 seconds
Started Aug 16 06:22:05 PM PDT 24
Finished Aug 16 06:22:06 PM PDT 24
Peak memory 214972 kb
Host smart-0f836af1-9b52-4086-afd9-40ee8b89383f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904802315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2904802315
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2147380261
Short name T804
Test name
Test status
Simulation time 121611225 ps
CPU time 0.82 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:05 PM PDT 24
Peak memory 215380 kb
Host smart-1c9eb305-bafe-4814-b0aa-84a1d6bd9236
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147380261 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2147380261
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2810515354
Short name T763
Test name
Test status
Simulation time 138981328 ps
CPU time 1.14 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 219560 kb
Host smart-9f4de72e-6b8d-4378-bf92-4083ffde8db1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810515354 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2810515354
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3887183733
Short name T205
Test name
Test status
Simulation time 21587445 ps
CPU time 1.04 seconds
Started Aug 16 06:22:16 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 219536 kb
Host smart-64bfb589-7ce5-4630-b5c1-a0ca34d5edad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887183733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3887183733
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2641766596
Short name T369
Test name
Test status
Simulation time 32156926 ps
CPU time 1.3 seconds
Started Aug 16 06:21:55 PM PDT 24
Finished Aug 16 06:21:57 PM PDT 24
Peak memory 218524 kb
Host smart-51c5ec30-15c6-4f3d-9ac2-792d0f0ac84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641766596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2641766596
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2223678874
Short name T953
Test name
Test status
Simulation time 32555871 ps
CPU time 0.91 seconds
Started Aug 16 06:22:05 PM PDT 24
Finished Aug 16 06:22:06 PM PDT 24
Peak memory 215572 kb
Host smart-a466aa1d-4825-4469-a8e7-360a52cbbcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223678874 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2223678874
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1541025443
Short name T419
Test name
Test status
Simulation time 42054839 ps
CPU time 0.87 seconds
Started Aug 16 06:21:55 PM PDT 24
Finished Aug 16 06:21:56 PM PDT 24
Peak memory 215184 kb
Host smart-84898f39-2dfc-425c-aec9-09643cd761ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541025443 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1541025443
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3809212600
Short name T961
Test name
Test status
Simulation time 314758026 ps
CPU time 6.53 seconds
Started Aug 16 06:22:09 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 215376 kb
Host smart-ed0d0b63-90c0-4aa1-83a9-5d712ed40aa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809212600 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3809212600
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.473957603
Short name T221
Test name
Test status
Simulation time 3673359162 ps
CPU time 99.28 seconds
Started Aug 16 06:21:58 PM PDT 24
Finished Aug 16 06:23:38 PM PDT 24
Peak memory 217752 kb
Host smart-0454de2d-be01-4b2f-84d0-ad4c022a3182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473957603 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.473957603
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2450450850
Short name T214
Test name
Test status
Simulation time 44344424 ps
CPU time 1.2 seconds
Started Aug 16 06:22:03 PM PDT 24
Finished Aug 16 06:22:04 PM PDT 24
Peak memory 219800 kb
Host smart-e25641ea-a46e-45cd-acbf-830c4ebbe45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450450850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2450450850
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2798313760
Short name T569
Test name
Test status
Simulation time 27790951 ps
CPU time 0.82 seconds
Started Aug 16 06:22:03 PM PDT 24
Finished Aug 16 06:22:04 PM PDT 24
Peak memory 206836 kb
Host smart-24298d7e-244b-4346-b74b-852d62a02c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798313760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2798313760
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2614934377
Short name T199
Test name
Test status
Simulation time 37419508 ps
CPU time 0.84 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 215456 kb
Host smart-03c4afa3-193c-4a14-836f-891492b170d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614934377 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2614934377
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2608541106
Short name T944
Test name
Test status
Simulation time 117616472 ps
CPU time 1.17 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:16 PM PDT 24
Peak memory 215616 kb
Host smart-4d29f2a1-a5fc-4f77-a8be-2ecb5a234fa5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608541106 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2608541106
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.4122730302
Short name T629
Test name
Test status
Simulation time 24965392 ps
CPU time 0.94 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:20 PM PDT 24
Peak memory 215520 kb
Host smart-6528469f-7be9-4745-ad11-787b321e6ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122730302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4122730302
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.226267228
Short name T342
Test name
Test status
Simulation time 57954403 ps
CPU time 1.52 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 217456 kb
Host smart-91fe0a4a-1a8f-4101-bd8c-c5eab36d6290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226267228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.226267228
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3938198646
Short name T46
Test name
Test status
Simulation time 22231602 ps
CPU time 1.05 seconds
Started Aug 16 06:22:11 PM PDT 24
Finished Aug 16 06:22:12 PM PDT 24
Peak memory 215552 kb
Host smart-e36900e7-c47b-4b0f-81c4-e6865c6c911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938198646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3938198646
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.453356745
Short name T808
Test name
Test status
Simulation time 14658336 ps
CPU time 1.01 seconds
Started Aug 16 06:22:03 PM PDT 24
Finished Aug 16 06:22:04 PM PDT 24
Peak memory 215356 kb
Host smart-832149d6-e2fd-479a-84c7-b2e2355799db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453356745 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.453356745
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3041122029
Short name T765
Test name
Test status
Simulation time 205353989 ps
CPU time 1.75 seconds
Started Aug 16 06:22:14 PM PDT 24
Finished Aug 16 06:22:16 PM PDT 24
Peak memory 217164 kb
Host smart-d13e7bbc-8132-42f5-8a3e-44c85bda184a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041122029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3041122029
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_alert.2878390564
Short name T1
Test name
Test status
Simulation time 28917781 ps
CPU time 1.25 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:06 PM PDT 24
Peak memory 220776 kb
Host smart-db77b769-6345-4bfb-a140-cdf0ab09f681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878390564 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2878390564
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.4168719780
Short name T483
Test name
Test status
Simulation time 252982916 ps
CPU time 0.93 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:06 PM PDT 24
Peak memory 215012 kb
Host smart-6737ec03-8e46-46c9-a57f-5e16ccc77fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168719780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.4168719780
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3941470644
Short name T195
Test name
Test status
Simulation time 23304226 ps
CPU time 0.9 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:20 PM PDT 24
Peak memory 215436 kb
Host smart-f16e863a-51c5-4768-bfff-2ef6c98b1e6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941470644 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3941470644
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2038829828
Short name T610
Test name
Test status
Simulation time 37231920 ps
CPU time 1.32 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 219340 kb
Host smart-71619c77-e39f-43e6-852d-71aaaa659f0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038829828 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2038829828
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3445054822
Short name T428
Test name
Test status
Simulation time 28494864 ps
CPU time 0.94 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:16 PM PDT 24
Peak memory 223920 kb
Host smart-0a7762a0-835a-45dc-8437-1ab1f937fafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445054822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3445054822
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1901473310
Short name T65
Test name
Test status
Simulation time 38787288 ps
CPU time 1.39 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:05 PM PDT 24
Peak memory 218560 kb
Host smart-f5cc4999-be0c-4b63-b954-10ed4216dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901473310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1901473310
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.874809834
Short name T23
Test name
Test status
Simulation time 27722539 ps
CPU time 0.93 seconds
Started Aug 16 06:22:06 PM PDT 24
Finished Aug 16 06:22:07 PM PDT 24
Peak memory 215868 kb
Host smart-b6cac7cd-81a5-41a4-a69f-b780d3d28250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874809834 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.874809834
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2551390589
Short name T455
Test name
Test status
Simulation time 43341145 ps
CPU time 0.91 seconds
Started Aug 16 06:22:06 PM PDT 24
Finished Aug 16 06:22:07 PM PDT 24
Peak memory 207152 kb
Host smart-1ff5075a-710a-43a8-90c4-5dd41671e6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551390589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2551390589
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1448098591
Short name T94
Test name
Test status
Simulation time 524600399 ps
CPU time 5.25 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:25 PM PDT 24
Peak memory 217296 kb
Host smart-8c859e6b-ac4b-4b90-9e61-c580384e15ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448098591 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1448098591
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.252855839
Short name T230
Test name
Test status
Simulation time 315339944 ps
CPU time 8.55 seconds
Started Aug 16 06:22:06 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 218592 kb
Host smart-5bda199b-9869-4a87-bafc-01db6ca84cfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252855839 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.252855839
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2579029106
Short name T578
Test name
Test status
Simulation time 77447116 ps
CPU time 1.24 seconds
Started Aug 16 06:22:03 PM PDT 24
Finished Aug 16 06:22:05 PM PDT 24
Peak memory 219976 kb
Host smart-298090f6-25b8-4cf0-a463-c9f67f521f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579029106 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2579029106
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4265490134
Short name T823
Test name
Test status
Simulation time 54999641 ps
CPU time 0.98 seconds
Started Aug 16 06:22:08 PM PDT 24
Finished Aug 16 06:22:09 PM PDT 24
Peak memory 206832 kb
Host smart-48028b9a-195e-468e-b46c-89e989e51ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265490134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4265490134
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1297875678
Short name T194
Test name
Test status
Simulation time 36550942 ps
CPU time 0.85 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:05 PM PDT 24
Peak memory 215460 kb
Host smart-30ad0a14-463c-48fc-8db5-2ca616900cbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297875678 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1297875678
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1679455938
Short name T491
Test name
Test status
Simulation time 21691228 ps
CPU time 1.01 seconds
Started Aug 16 06:22:06 PM PDT 24
Finished Aug 16 06:22:07 PM PDT 24
Peak memory 215380 kb
Host smart-e9d30cb9-2e02-4593-a302-8d6bbbd8b32a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679455938 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1679455938
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.404631365
Short name T638
Test name
Test status
Simulation time 20686177 ps
CPU time 1.03 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:20 PM PDT 24
Peak memory 218624 kb
Host smart-929f70cd-006e-49c2-a1b6-8dd06c2e80d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404631365 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.404631365
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.190690590
Short name T346
Test name
Test status
Simulation time 82042216 ps
CPU time 1.01 seconds
Started Aug 16 06:22:06 PM PDT 24
Finished Aug 16 06:22:07 PM PDT 24
Peak memory 217400 kb
Host smart-3ec7a160-c5e3-47ac-93c7-920abbf72fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190690590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.190690590
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1333537000
Short name T909
Test name
Test status
Simulation time 27442032 ps
CPU time 1.01 seconds
Started Aug 16 06:22:08 PM PDT 24
Finished Aug 16 06:22:09 PM PDT 24
Peak memory 215864 kb
Host smart-b3059244-6830-4eba-9955-4d4816ee8e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333537000 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1333537000
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2488479376
Short name T53
Test name
Test status
Simulation time 23417804 ps
CPU time 0.92 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 215364 kb
Host smart-16bb34c3-b844-4d93-954c-3e343820406c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488479376 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2488479376
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1772575771
Short name T873
Test name
Test status
Simulation time 689717380 ps
CPU time 5.13 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:09 PM PDT 24
Peak memory 217484 kb
Host smart-102ba178-de66-46b0-b49b-3e1837490502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772575771 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1772575771
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_alert.2325266934
Short name T92
Test name
Test status
Simulation time 24294512 ps
CPU time 1.19 seconds
Started Aug 16 06:22:07 PM PDT 24
Finished Aug 16 06:22:09 PM PDT 24
Peak memory 220068 kb
Host smart-ea75cc76-415b-4d51-8416-5b1e8ab2d880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325266934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2325266934
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2633052535
Short name T654
Test name
Test status
Simulation time 24644917 ps
CPU time 1.14 seconds
Started Aug 16 06:22:16 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 207040 kb
Host smart-47d0218c-78d9-4ea4-8479-8cb42e6243d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633052535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2633052535
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.804907228
Short name T650
Test name
Test status
Simulation time 31741970 ps
CPU time 0.83 seconds
Started Aug 16 06:22:17 PM PDT 24
Finished Aug 16 06:22:18 PM PDT 24
Peak memory 206988 kb
Host smart-ba962415-566a-4cb2-9264-db14075fa47e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804907228 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.804907228
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2531483094
Short name T129
Test name
Test status
Simulation time 31527196 ps
CPU time 1.2 seconds
Started Aug 16 06:22:06 PM PDT 24
Finished Aug 16 06:22:07 PM PDT 24
Peak memory 218836 kb
Host smart-4d8ce7b3-8371-4ad9-baec-84c06416adb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531483094 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2531483094
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3420341777
Short name T200
Test name
Test status
Simulation time 45916303 ps
CPU time 1.02 seconds
Started Aug 16 06:22:03 PM PDT 24
Finished Aug 16 06:22:04 PM PDT 24
Peak memory 219768 kb
Host smart-6b53b730-d0f5-4639-9e36-d7ad139592c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420341777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3420341777
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2594169376
Short name T478
Test name
Test status
Simulation time 58983943 ps
CPU time 2.29 seconds
Started Aug 16 06:22:01 PM PDT 24
Finished Aug 16 06:22:04 PM PDT 24
Peak memory 219800 kb
Host smart-3060707b-9a56-4589-93b3-dda9975cd52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594169376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2594169376
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.946054719
Short name T695
Test name
Test status
Simulation time 21741896 ps
CPU time 1.13 seconds
Started Aug 16 06:22:03 PM PDT 24
Finished Aug 16 06:22:04 PM PDT 24
Peak memory 215600 kb
Host smart-7f10df16-39d7-45db-9163-e5c5a4300c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946054719 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.946054719
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2702801643
Short name T62
Test name
Test status
Simulation time 33583028 ps
CPU time 0.98 seconds
Started Aug 16 06:22:14 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 207152 kb
Host smart-5a1b881e-ebb0-4a33-aedd-9cf08946c28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702801643 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2702801643
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.4144483867
Short name T234
Test name
Test status
Simulation time 238155640 ps
CPU time 4.8 seconds
Started Aug 16 06:22:17 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 217368 kb
Host smart-24b9001a-572a-4209-a3da-51564a87399f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144483867 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.4144483867
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_alert_test.2518832011
Short name T56
Test name
Test status
Simulation time 84890729 ps
CPU time 0.92 seconds
Started Aug 16 06:22:08 PM PDT 24
Finished Aug 16 06:22:09 PM PDT 24
Peak memory 206812 kb
Host smart-5e338b62-53e9-4d60-a711-68354eec74e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518832011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2518832011
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1147925653
Short name T669
Test name
Test status
Simulation time 13013115 ps
CPU time 0.93 seconds
Started Aug 16 06:22:16 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 215580 kb
Host smart-52a78c8b-65c0-4887-8418-7bd9fdcac720
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147925653 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1147925653
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3166762541
Short name T934
Test name
Test status
Simulation time 41894107 ps
CPU time 1.39 seconds
Started Aug 16 06:22:08 PM PDT 24
Finished Aug 16 06:22:09 PM PDT 24
Peak memory 217164 kb
Host smart-0c640e29-ebc2-4db2-b653-fb904b832d57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166762541 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3166762541
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1423761371
Short name T116
Test name
Test status
Simulation time 48764917 ps
CPU time 1.07 seconds
Started Aug 16 06:22:04 PM PDT 24
Finished Aug 16 06:22:05 PM PDT 24
Peak memory 220848 kb
Host smart-5f177849-1ee8-4a64-8b04-00dcc30dbcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423761371 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1423761371
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.814193037
Short name T349
Test name
Test status
Simulation time 75288086 ps
CPU time 1.8 seconds
Started Aug 16 06:22:14 PM PDT 24
Finished Aug 16 06:22:16 PM PDT 24
Peak memory 220612 kb
Host smart-fea427eb-1d35-4783-99cb-09ba7038babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814193037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.814193037
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1492098048
Short name T688
Test name
Test status
Simulation time 44346075 ps
CPU time 0.87 seconds
Started Aug 16 06:22:08 PM PDT 24
Finished Aug 16 06:22:09 PM PDT 24
Peak memory 215660 kb
Host smart-fecd6cf3-c92b-4af4-9aa1-8305a75cb6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492098048 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1492098048
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.4107927401
Short name T830
Test name
Test status
Simulation time 16420079 ps
CPU time 0.99 seconds
Started Aug 16 06:22:16 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 215352 kb
Host smart-d396aec9-dec7-4ad9-b36a-1587847a2ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107927401 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.4107927401
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3044486533
Short name T829
Test name
Test status
Simulation time 241553923 ps
CPU time 5.18 seconds
Started Aug 16 06:22:07 PM PDT 24
Finished Aug 16 06:22:12 PM PDT 24
Peak memory 215404 kb
Host smart-67684ff2-67e5-4dfd-8d84-ce5417a46d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044486533 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3044486533
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.2348398520
Short name T813
Test name
Test status
Simulation time 31522486 ps
CPU time 1.18 seconds
Started Aug 16 06:22:11 PM PDT 24
Finished Aug 16 06:22:13 PM PDT 24
Peak memory 219420 kb
Host smart-291a470f-cbc9-45b1-87b0-b40f3cbac778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348398520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2348398520
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.684446370
Short name T807
Test name
Test status
Simulation time 15359061 ps
CPU time 0.92 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 206752 kb
Host smart-504fdfa7-9e26-4646-8c74-75e4366988f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684446370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.684446370
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1844282215
Short name T19
Test name
Test status
Simulation time 18869839 ps
CPU time 0.9 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 215412 kb
Host smart-5e417233-767b-4331-9d62-e915143b3427
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844282215 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1844282215
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.4221060369
Short name T535
Test name
Test status
Simulation time 290863829 ps
CPU time 1.19 seconds
Started Aug 16 06:22:13 PM PDT 24
Finished Aug 16 06:22:14 PM PDT 24
Peak memory 216872 kb
Host smart-cfc2f167-14ea-40a3-92c3-11f80ab85ae5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221060369 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.4221060369
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.719507709
Short name T189
Test name
Test status
Simulation time 55389402 ps
CPU time 0.97 seconds
Started Aug 16 06:22:14 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 229380 kb
Host smart-5878bb5a-83e4-48ac-93d7-e559d65a988b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719507709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.719507709
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1048992668
Short name T913
Test name
Test status
Simulation time 34938714 ps
CPU time 1.46 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:23 PM PDT 24
Peak memory 218584 kb
Host smart-c50def8a-4344-4893-a15e-fd8642cca472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048992668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1048992668
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.384029335
Short name T882
Test name
Test status
Simulation time 32734620 ps
CPU time 0.86 seconds
Started Aug 16 06:22:10 PM PDT 24
Finished Aug 16 06:22:10 PM PDT 24
Peak memory 215356 kb
Host smart-9e8719fa-d4a5-411f-998a-60baff72fd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384029335 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.384029335
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.250616970
Short name T580
Test name
Test status
Simulation time 17326097 ps
CPU time 0.98 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 215376 kb
Host smart-471b82d3-b099-4d0f-8aaf-3854e14a7b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250616970 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.250616970
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.4286088133
Short name T902
Test name
Test status
Simulation time 686938237 ps
CPU time 3.71 seconds
Started Aug 16 06:22:17 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 217580 kb
Host smart-cc99c927-6183-4b30-835e-22562800b52e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286088133 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.4286088133
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_alert.3134755479
Short name T740
Test name
Test status
Simulation time 22323934 ps
CPU time 1.17 seconds
Started Aug 16 06:21:09 PM PDT 24
Finished Aug 16 06:21:10 PM PDT 24
Peak memory 221020 kb
Host smart-8432d4d4-9337-49ca-a824-c4846fc8ae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134755479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3134755479
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3801440483
Short name T853
Test name
Test status
Simulation time 86291831 ps
CPU time 1.01 seconds
Started Aug 16 06:21:13 PM PDT 24
Finished Aug 16 06:21:14 PM PDT 24
Peak memory 206808 kb
Host smart-7afd2e5f-d745-4245-83b5-bec528f09f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801440483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3801440483
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1807106104
Short name T79
Test name
Test status
Simulation time 45365297 ps
CPU time 1.16 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 216952 kb
Host smart-d690b038-d739-4ec4-9b1f-6dbc2e477551
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807106104 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1807106104
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2823001581
Short name T207
Test name
Test status
Simulation time 27575544 ps
CPU time 1.28 seconds
Started Aug 16 06:21:07 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 217412 kb
Host smart-0b631a2e-7df6-4837-8a6b-9c521d20bf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823001581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2823001581
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.542196768
Short name T529
Test name
Test status
Simulation time 48455349 ps
CPU time 1.15 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:07 PM PDT 24
Peak memory 217396 kb
Host smart-c298c3d0-12ef-4b14-9cd7-9b8454ac38fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542196768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.542196768
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1229595986
Short name T931
Test name
Test status
Simulation time 32955318 ps
CPU time 0.94 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 215748 kb
Host smart-c01b873b-0c05-4fca-9c55-48befee5f41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229595986 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1229595986
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.329300155
Short name T923
Test name
Test status
Simulation time 24778572 ps
CPU time 0.94 seconds
Started Aug 16 06:21:15 PM PDT 24
Finished Aug 16 06:21:16 PM PDT 24
Peak memory 207168 kb
Host smart-45450770-251e-4ad0-9231-879d2af630f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329300155 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.329300155
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2393393297
Short name T475
Test name
Test status
Simulation time 114096489 ps
CPU time 1.04 seconds
Started Aug 16 06:21:13 PM PDT 24
Finished Aug 16 06:21:14 PM PDT 24
Peak memory 215356 kb
Host smart-f4de8993-0968-4273-9e0d-191eeb4322cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393393297 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2393393297
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1576576743
Short name T672
Test name
Test status
Simulation time 314048018 ps
CPU time 2.27 seconds
Started Aug 16 06:21:09 PM PDT 24
Finished Aug 16 06:21:12 PM PDT 24
Peak memory 215324 kb
Host smart-6f25e5c1-c715-46b2-a8a8-c994e0ff949f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576576743 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1576576743
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2768841949
Short name T680
Test name
Test status
Simulation time 4767926724 ps
CPU time 135.56 seconds
Started Aug 16 06:21:16 PM PDT 24
Finished Aug 16 06:23:31 PM PDT 24
Peak memory 218232 kb
Host smart-f7f0385d-3cda-427c-bff3-06c50ab81cfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768841949 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2768841949
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.2899275029
Short name T351
Test name
Test status
Simulation time 241069190 ps
CPU time 1.28 seconds
Started Aug 16 06:22:13 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 219576 kb
Host smart-91eca63f-9109-493e-826c-d40d1ee1cc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899275029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.2899275029
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.2691288645
Short name T760
Test name
Test status
Simulation time 22710147 ps
CPU time 0.89 seconds
Started Aug 16 06:22:12 PM PDT 24
Finished Aug 16 06:22:13 PM PDT 24
Peak memory 218232 kb
Host smart-094f3020-04d8-4c3a-aa0e-b96a20996740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691288645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2691288645
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3294770968
Short name T307
Test name
Test status
Simulation time 45550259 ps
CPU time 1.31 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 219012 kb
Host smart-1eb9411f-95db-4e18-81cd-74a78ab63291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294770968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3294770968
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3620648875
Short name T476
Test name
Test status
Simulation time 55759742 ps
CPU time 1.07 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:16 PM PDT 24
Peak memory 219732 kb
Host smart-8c905d45-83f4-468d-8e11-a9ef05eb58bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620648875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3620648875
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4182011632
Short name T363
Test name
Test status
Simulation time 31248016 ps
CPU time 1.46 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 217564 kb
Host smart-279d2643-2068-490f-8960-8b36245471df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182011632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4182011632
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.2572816429
Short name T607
Test name
Test status
Simulation time 53272497 ps
CPU time 1.27 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 220172 kb
Host smart-b832efdf-3ebf-4e0c-b07e-c4a4d887c01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572816429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.2572816429
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1265036373
Short name T49
Test name
Test status
Simulation time 20211042 ps
CPU time 1.2 seconds
Started Aug 16 06:22:13 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 229688 kb
Host smart-3498c4a9-ccfc-418c-be03-15c7863b8844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265036373 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1265036373
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2735005235
Short name T598
Test name
Test status
Simulation time 361371762 ps
CPU time 2.73 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:18 PM PDT 24
Peak memory 220520 kb
Host smart-9e62736f-32eb-46ff-8794-5361a5e80701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735005235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2735005235
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1750180212
Short name T796
Test name
Test status
Simulation time 166745988 ps
CPU time 1.14 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 219868 kb
Host smart-be443eac-d1d1-4485-b9be-36e2b048a98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750180212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1750180212
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.2130987401
Short name T930
Test name
Test status
Simulation time 49217283 ps
CPU time 1.01 seconds
Started Aug 16 06:22:16 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 219552 kb
Host smart-8a54d68b-1c2b-4fa5-9ed1-6d6f95389b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130987401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2130987401
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1622899028
Short name T732
Test name
Test status
Simulation time 76145178 ps
CPU time 1.26 seconds
Started Aug 16 06:22:12 PM PDT 24
Finished Aug 16 06:22:13 PM PDT 24
Peak memory 217512 kb
Host smart-e367a52a-6a04-4f9a-9f34-c9aa15a463af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622899028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1622899028
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.2752170945
Short name T292
Test name
Test status
Simulation time 118597198 ps
CPU time 1.18 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 215748 kb
Host smart-fa5ae2a7-9244-42e7-a580-000be481d9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752170945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.2752170945
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2051690918
Short name T136
Test name
Test status
Simulation time 24757049 ps
CPU time 1.26 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:20 PM PDT 24
Peak memory 229724 kb
Host smart-2879b930-9816-40b4-8e7b-e09c49539c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051690918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2051690918
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.506515532
Short name T752
Test name
Test status
Simulation time 63742335 ps
CPU time 2.16 seconds
Started Aug 16 06:22:17 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 217708 kb
Host smart-832eda7d-11fd-4c43-96fd-7467592c5947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506515532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.506515532
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.3997379995
Short name T438
Test name
Test status
Simulation time 53146841 ps
CPU time 1.15 seconds
Started Aug 16 06:22:12 PM PDT 24
Finished Aug 16 06:22:13 PM PDT 24
Peak memory 220936 kb
Host smart-e65b9f21-3207-49ae-893d-fd1212b12be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997379995 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.3997379995
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.2124933695
Short name T66
Test name
Test status
Simulation time 18452399 ps
CPU time 1.12 seconds
Started Aug 16 06:22:12 PM PDT 24
Finished Aug 16 06:22:14 PM PDT 24
Peak memory 218400 kb
Host smart-9d130d43-793e-49b8-a567-daeb67a743f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124933695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2124933695
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.545694973
Short name T941
Test name
Test status
Simulation time 37867943 ps
CPU time 1.2 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 217260 kb
Host smart-6f7c479b-efaa-47e2-98c6-5c2de7f12a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545694973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.545694973
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.469951184
Short name T637
Test name
Test status
Simulation time 45705547 ps
CPU time 1.19 seconds
Started Aug 16 06:22:17 PM PDT 24
Finished Aug 16 06:22:18 PM PDT 24
Peak memory 215692 kb
Host smart-78013af1-28a4-4098-9d92-d7800088b902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469951184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.469951184
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.1008248526
Short name T831
Test name
Test status
Simulation time 46551298 ps
CPU time 1.17 seconds
Started Aug 16 06:22:11 PM PDT 24
Finished Aug 16 06:22:12 PM PDT 24
Peak memory 219784 kb
Host smart-5a31f9ab-eb78-437b-b1f2-b7699449359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008248526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1008248526
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1049463507
Short name T661
Test name
Test status
Simulation time 41389618 ps
CPU time 1.13 seconds
Started Aug 16 06:22:16 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 218456 kb
Host smart-2860ad93-9f59-4ae5-a8a1-08fe27e9318d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049463507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1049463507
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.454297233
Short name T149
Test name
Test status
Simulation time 103947590 ps
CPU time 1.34 seconds
Started Aug 16 06:22:14 PM PDT 24
Finished Aug 16 06:22:16 PM PDT 24
Peak memory 219800 kb
Host smart-62d42fb5-2f24-4bc8-9f1d-a3ad21f3ac8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454297233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.454297233
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.4080404679
Short name T800
Test name
Test status
Simulation time 48086395 ps
CPU time 1.04 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:20 PM PDT 24
Peak memory 219760 kb
Host smart-202d51ef-44a6-46e9-9248-a90d718bbd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080404679 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4080404679
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3739664257
Short name T403
Test name
Test status
Simulation time 42694639 ps
CPU time 1.21 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:16 PM PDT 24
Peak memory 217456 kb
Host smart-a1738bda-aced-45dd-8f94-f5e4205e0ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739664257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3739664257
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.1035334613
Short name T619
Test name
Test status
Simulation time 76513868 ps
CPU time 1.13 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 220632 kb
Host smart-a7b6e329-3ea7-4274-b560-6ef53d249fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035334613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.1035334613
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.2246419399
Short name T828
Test name
Test status
Simulation time 21542763 ps
CPU time 1.13 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:20 PM PDT 24
Peak memory 220568 kb
Host smart-a4c9699a-f721-4724-87f8-30dbb2536f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246419399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2246419399
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3114482312
Short name T371
Test name
Test status
Simulation time 37603731 ps
CPU time 1.41 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:16 PM PDT 24
Peak memory 217408 kb
Host smart-c46c8667-76cb-44ba-8f62-437418948e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114482312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3114482312
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2606294423
Short name T247
Test name
Test status
Simulation time 116478825 ps
CPU time 1.25 seconds
Started Aug 16 06:22:17 PM PDT 24
Finished Aug 16 06:22:18 PM PDT 24
Peak memory 218632 kb
Host smart-432b563e-2a50-4926-8f0e-f97cd1407724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606294423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2606294423
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.1940181431
Short name T812
Test name
Test status
Simulation time 28131515 ps
CPU time 0.87 seconds
Started Aug 16 06:22:17 PM PDT 24
Finished Aug 16 06:22:18 PM PDT 24
Peak memory 218372 kb
Host smart-5b0b8fe4-3066-4077-95c0-c83e3705716e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940181431 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1940181431
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2183108696
Short name T34
Test name
Test status
Simulation time 32352195 ps
CPU time 1.26 seconds
Started Aug 16 06:22:13 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 218868 kb
Host smart-26fcaff1-66a7-48aa-a7c8-0a1d0da08f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183108696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2183108696
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2580238764
Short name T410
Test name
Test status
Simulation time 92478722 ps
CPU time 1.21 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 215764 kb
Host smart-78db4141-2500-4b2d-88bc-fef9f8d9d10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580238764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2580238764
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3459307457
Short name T429
Test name
Test status
Simulation time 34086380 ps
CPU time 0.93 seconds
Started Aug 16 06:21:09 PM PDT 24
Finished Aug 16 06:21:10 PM PDT 24
Peak memory 214768 kb
Host smart-dc526b0d-3d00-4167-8543-68f5992de240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459307457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3459307457
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2706074244
Short name T157
Test name
Test status
Simulation time 11307639 ps
CPU time 0.91 seconds
Started Aug 16 06:21:07 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 215404 kb
Host smart-90da140c-f505-4b8d-b08a-77d2f2a31d6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706074244 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2706074244
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.994550429
Short name T114
Test name
Test status
Simulation time 71336950 ps
CPU time 1.05 seconds
Started Aug 16 06:21:13 PM PDT 24
Finished Aug 16 06:21:14 PM PDT 24
Peak memory 218076 kb
Host smart-13efa33d-2126-4b06-8db3-a5442b3684e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994550429 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.994550429
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2797137639
Short name T169
Test name
Test status
Simulation time 21220325 ps
CPU time 1.05 seconds
Started Aug 16 06:21:09 PM PDT 24
Finished Aug 16 06:21:10 PM PDT 24
Peak memory 224088 kb
Host smart-2b6b8236-5f86-4952-bd81-3b09c709024f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797137639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2797137639
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.255339346
Short name T952
Test name
Test status
Simulation time 97519999 ps
CPU time 1.28 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 218760 kb
Host smart-06cda305-283d-404c-bc6d-855cb1af30aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255339346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.255339346
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1365127989
Short name T798
Test name
Test status
Simulation time 23695216 ps
CPU time 1.14 seconds
Started Aug 16 06:21:08 PM PDT 24
Finished Aug 16 06:21:09 PM PDT 24
Peak memory 224304 kb
Host smart-d426719b-b0c8-4e38-abcb-b91e3dbe5c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365127989 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1365127989
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.940814568
Short name T749
Test name
Test status
Simulation time 19009526 ps
CPU time 1.03 seconds
Started Aug 16 06:21:10 PM PDT 24
Finished Aug 16 06:21:11 PM PDT 24
Peak memory 207172 kb
Host smart-93d9e911-7577-4f9b-90a4-47c17dd4d4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940814568 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.940814568
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.570842262
Short name T675
Test name
Test status
Simulation time 18821633 ps
CPU time 1.08 seconds
Started Aug 16 06:21:05 PM PDT 24
Finished Aug 16 06:21:07 PM PDT 24
Peak memory 215356 kb
Host smart-21fd2cd8-a0d7-4c65-8ac3-d3d54c62280f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570842262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.570842262
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3127693955
Short name T238
Test name
Test status
Simulation time 190327359 ps
CPU time 2.39 seconds
Started Aug 16 06:21:05 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 215360 kb
Host smart-8e3c819d-0a2f-4711-a3e1-ca82ff04c9d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127693955 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3127693955
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.4084496142
Short name T579
Test name
Test status
Simulation time 2462162939 ps
CPU time 34.52 seconds
Started Aug 16 06:21:05 PM PDT 24
Finished Aug 16 06:21:40 PM PDT 24
Peak memory 220528 kb
Host smart-0a492677-9335-42fc-89fc-d9c532274599
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084496142 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.4084496142
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3403470473
Short name T408
Test name
Test status
Simulation time 36779516 ps
CPU time 1.07 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 220672 kb
Host smart-be22cffd-5607-4dad-ab22-b0797b3de73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403470473 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3403470473
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1600656419
Short name T357
Test name
Test status
Simulation time 32716621 ps
CPU time 1.37 seconds
Started Aug 16 06:22:14 PM PDT 24
Finished Aug 16 06:22:16 PM PDT 24
Peak memory 217588 kb
Host smart-d60fbb84-88a2-4fea-8ca5-3a81c4084183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600656419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1600656419
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_alert.1997375532
Short name T241
Test name
Test status
Simulation time 37002318 ps
CPU time 1.39 seconds
Started Aug 16 06:22:14 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 215788 kb
Host smart-60546da8-9a7e-4182-b5c9-173955025d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997375532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.1997375532
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/default/61.edn_err.3410631236
Short name T203
Test name
Test status
Simulation time 31258171 ps
CPU time 1.29 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 219604 kb
Host smart-ca5d1c60-a6ff-46fb-a24b-4680c601b3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410631236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3410631236
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3247954880
Short name T887
Test name
Test status
Simulation time 51738314 ps
CPU time 1.26 seconds
Started Aug 16 06:22:14 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 217500 kb
Host smart-df6a8f67-d884-4425-af97-ee546f1725c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247954880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3247954880
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.4014362768
Short name T723
Test name
Test status
Simulation time 178433954 ps
CPU time 1.28 seconds
Started Aug 16 06:22:17 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 218916 kb
Host smart-c0840250-5db4-4bd8-b886-40f1d855d431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014362768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.4014362768
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2297158880
Short name T131
Test name
Test status
Simulation time 71197074 ps
CPU time 1.19 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 225748 kb
Host smart-2f4fd835-4514-4727-8bc6-08f38c744759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297158880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2297158880
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/63.edn_alert.3722399230
Short name T780
Test name
Test status
Simulation time 47526004 ps
CPU time 1.13 seconds
Started Aug 16 06:22:12 PM PDT 24
Finished Aug 16 06:22:14 PM PDT 24
Peak memory 219564 kb
Host smart-6838e1aa-ce3f-41fa-94cf-0d9d6ade337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722399230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.3722399230
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.4136985997
Short name T109
Test name
Test status
Simulation time 40219230 ps
CPU time 1.17 seconds
Started Aug 16 06:22:22 PM PDT 24
Finished Aug 16 06:22:24 PM PDT 24
Peak memory 229744 kb
Host smart-ffa53b1c-cb19-412f-8aef-001c4b9095ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136985997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4136985997
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1719160935
Short name T364
Test name
Test status
Simulation time 64223628 ps
CPU time 1.7 seconds
Started Aug 16 06:22:13 PM PDT 24
Finished Aug 16 06:22:15 PM PDT 24
Peak memory 218816 kb
Host smart-6f1243e9-f78e-4016-87de-b00e7a027c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719160935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1719160935
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.2992242543
Short name T858
Test name
Test status
Simulation time 22644637 ps
CPU time 1.13 seconds
Started Aug 16 06:22:17 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 218528 kb
Host smart-1f2bacf4-ef85-45ee-9225-7792612dd2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992242543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.2992242543
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.2167003280
Short name T67
Test name
Test status
Simulation time 30204749 ps
CPU time 0.89 seconds
Started Aug 16 06:22:25 PM PDT 24
Finished Aug 16 06:22:26 PM PDT 24
Peak memory 218284 kb
Host smart-5d3ec3ec-cc35-46c6-927c-3cd50034c507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167003280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2167003280
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1592065042
Short name T421
Test name
Test status
Simulation time 93937530 ps
CPU time 1.4 seconds
Started Aug 16 06:22:17 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 217408 kb
Host smart-4da4c3fd-4ae6-46ac-9845-f2f04a650e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592065042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1592065042
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.2644250690
Short name T120
Test name
Test status
Simulation time 119914931 ps
CPU time 1.26 seconds
Started Aug 16 06:22:17 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 218568 kb
Host smart-a34e6a44-6c9a-4e97-b7d1-a8b1a27c1ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644250690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.2644250690
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.795843884
Short name T642
Test name
Test status
Simulation time 34330766 ps
CPU time 1.47 seconds
Started Aug 16 06:22:16 PM PDT 24
Finished Aug 16 06:22:18 PM PDT 24
Peak memory 225840 kb
Host smart-500817df-bb5e-4e63-ac1c-d6c618aa9835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795843884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.795843884
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2479549900
Short name T466
Test name
Test status
Simulation time 160054701 ps
CPU time 1.41 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:16 PM PDT 24
Peak memory 218800 kb
Host smart-e90481fb-0d75-4a24-827b-94d74af0c0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479549900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2479549900
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.273281766
Short name T777
Test name
Test status
Simulation time 75322793 ps
CPU time 1.14 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:20 PM PDT 24
Peak memory 219956 kb
Host smart-5e9219f4-bbb1-464b-a195-682d99e19936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273281766 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.273281766
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.3238142121
Short name T884
Test name
Test status
Simulation time 168951351 ps
CPU time 1.15 seconds
Started Aug 16 06:22:15 PM PDT 24
Finished Aug 16 06:22:16 PM PDT 24
Peak memory 219784 kb
Host smart-c9309612-f0c2-470a-b975-baa311d17e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238142121 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3238142121
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.409366279
Short name T945
Test name
Test status
Simulation time 48652860 ps
CPU time 1.31 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 218872 kb
Host smart-a4538983-9add-4fcf-89e7-eb2982d94256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409366279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.409366279
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1379107485
Short name T954
Test name
Test status
Simulation time 40068991 ps
CPU time 1.23 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:23 PM PDT 24
Peak memory 219180 kb
Host smart-ddb539e8-7280-4e2b-accf-f4f8e99e0974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379107485 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1379107485
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.337755434
Short name T523
Test name
Test status
Simulation time 84354836 ps
CPU time 1.05 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 215516 kb
Host smart-e33513d4-af1f-4a73-8079-7335b44c15e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337755434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.337755434
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.195588544
Short name T611
Test name
Test status
Simulation time 61456951 ps
CPU time 1.55 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 218708 kb
Host smart-fbd84b6e-9976-4ee4-a228-3da4fb7236a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195588544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.195588544
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.3274208281
Short name T689
Test name
Test status
Simulation time 27002081 ps
CPU time 1.31 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:19 PM PDT 24
Peak memory 219208 kb
Host smart-e5aa8931-dfb5-4679-92f3-6c1da3816d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274208281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.3274208281
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.347669031
Short name T778
Test name
Test status
Simulation time 31963188 ps
CPU time 0.87 seconds
Started Aug 16 06:22:24 PM PDT 24
Finished Aug 16 06:22:24 PM PDT 24
Peak memory 218572 kb
Host smart-d5ac708b-6981-4afe-a490-1f94fdb039a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347669031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.347669031
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1387796832
Short name T524
Test name
Test status
Simulation time 65648977 ps
CPU time 1.01 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 217340 kb
Host smart-a6288bc8-2088-49de-b21b-25ef20ca5de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387796832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1387796832
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_alert.4005538677
Short name T595
Test name
Test status
Simulation time 22098968 ps
CPU time 1.16 seconds
Started Aug 16 06:22:16 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 220076 kb
Host smart-2da8910e-5156-420e-87eb-ebc8cec100ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005538677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.4005538677
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/69.edn_err.3686482384
Short name T646
Test name
Test status
Simulation time 62246319 ps
CPU time 1.03 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 218844 kb
Host smart-72575278-22d6-4811-a903-3af230f375bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686482384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3686482384
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1162874277
Short name T277
Test name
Test status
Simulation time 32125589 ps
CPU time 1.37 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 218636 kb
Host smart-3bfb20d0-a870-4db6-8729-e2214246ed73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162874277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1162874277
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2247974912
Short name T503
Test name
Test status
Simulation time 356415551 ps
CPU time 1.29 seconds
Started Aug 16 06:21:05 PM PDT 24
Finished Aug 16 06:21:06 PM PDT 24
Peak memory 219916 kb
Host smart-458bcca8-eff9-4464-be1f-aa54fe54cd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247974912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2247974912
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3761990123
Short name T458
Test name
Test status
Simulation time 28150289 ps
CPU time 0.99 seconds
Started Aug 16 06:21:21 PM PDT 24
Finished Aug 16 06:21:22 PM PDT 24
Peak memory 206792 kb
Host smart-8d2b59a8-2b31-49d9-9a87-605ca2cc66eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761990123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3761990123
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_err.2649208924
Short name T123
Test name
Test status
Simulation time 20979618 ps
CPU time 1.15 seconds
Started Aug 16 06:21:10 PM PDT 24
Finished Aug 16 06:21:11 PM PDT 24
Peak memory 219624 kb
Host smart-8174c942-0194-4002-b3b4-885c0e1ae26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649208924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2649208924
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1952165574
Short name T676
Test name
Test status
Simulation time 61494110 ps
CPU time 1.34 seconds
Started Aug 16 06:21:26 PM PDT 24
Finished Aug 16 06:21:28 PM PDT 24
Peak memory 220044 kb
Host smart-6a3fec0f-2503-4948-993c-31e64a020d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952165574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1952165574
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1241403771
Short name T706
Test name
Test status
Simulation time 43616690 ps
CPU time 0.91 seconds
Started Aug 16 06:21:08 PM PDT 24
Finished Aug 16 06:21:09 PM PDT 24
Peak memory 215332 kb
Host smart-a7d34ca8-b42b-4192-a685-6c7973e25c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241403771 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1241403771
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3936803380
Short name T810
Test name
Test status
Simulation time 16515320 ps
CPU time 1.08 seconds
Started Aug 16 06:21:08 PM PDT 24
Finished Aug 16 06:21:09 PM PDT 24
Peak memory 207212 kb
Host smart-cf7657e2-5a6e-466d-9b87-bca2904aae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936803380 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3936803380
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2038584395
Short name T289
Test name
Test status
Simulation time 15995444 ps
CPU time 0.97 seconds
Started Aug 16 06:21:12 PM PDT 24
Finished Aug 16 06:21:13 PM PDT 24
Peak memory 207184 kb
Host smart-827206b6-1e79-4260-9b0f-a66cc011adcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038584395 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2038584395
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.831638109
Short name T922
Test name
Test status
Simulation time 2495569969 ps
CPU time 5.63 seconds
Started Aug 16 06:21:08 PM PDT 24
Finished Aug 16 06:21:14 PM PDT 24
Peak memory 217280 kb
Host smart-9dfd0704-f828-413b-b504-9c4fa961c5d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831638109 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.831638109
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/70.edn_alert.3823622146
Short name T482
Test name
Test status
Simulation time 110124634 ps
CPU time 1.32 seconds
Started Aug 16 06:22:16 PM PDT 24
Finished Aug 16 06:22:18 PM PDT 24
Peak memory 215752 kb
Host smart-1216f762-b6ec-4deb-a1ed-ec2cc7f64f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823622146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.3823622146
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.101298067
Short name T105
Test name
Test status
Simulation time 34222273 ps
CPU time 0.96 seconds
Started Aug 16 06:22:23 PM PDT 24
Finished Aug 16 06:22:24 PM PDT 24
Peak memory 219944 kb
Host smart-30c39c0d-5011-423e-b2c4-606130e65a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101298067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.101298067
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3651147218
Short name T508
Test name
Test status
Simulation time 170270285 ps
CPU time 2.03 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 219840 kb
Host smart-4c7e0d0d-bcf5-4852-9e45-4cf7c00d2189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651147218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3651147218
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.829224132
Short name T779
Test name
Test status
Simulation time 44010113 ps
CPU time 1.27 seconds
Started Aug 16 06:22:29 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 220224 kb
Host smart-55e7973f-69d9-43d3-ae1d-8ec7a7bf02e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829224132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.829224132
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2304092429
Short name T380
Test name
Test status
Simulation time 18551602 ps
CPU time 1.04 seconds
Started Aug 16 06:22:30 PM PDT 24
Finished Aug 16 06:22:31 PM PDT 24
Peak memory 218816 kb
Host smart-09f421f6-b9e4-4c2d-8af1-764798749225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304092429 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2304092429
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.405913650
Short name T956
Test name
Test status
Simulation time 48895519 ps
CPU time 1.33 seconds
Started Aug 16 06:22:43 PM PDT 24
Finished Aug 16 06:22:44 PM PDT 24
Peak memory 220404 kb
Host smart-f7321563-d0b7-462c-9826-d574e070d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405913650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.405913650
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.1930066336
Short name T509
Test name
Test status
Simulation time 27209824 ps
CPU time 1.17 seconds
Started Aug 16 06:22:24 PM PDT 24
Finished Aug 16 06:22:25 PM PDT 24
Peak memory 215764 kb
Host smart-7ecc765a-272b-4b73-bfa4-154b2149f317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930066336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.1930066336
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_genbits.1807186893
Short name T300
Test name
Test status
Simulation time 49244108 ps
CPU time 1.93 seconds
Started Aug 16 06:22:23 PM PDT 24
Finished Aug 16 06:22:25 PM PDT 24
Peak memory 218648 kb
Host smart-58564e8f-a854-43dd-9d1e-b4f23984e7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807186893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1807186893
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.942310690
Short name T687
Test name
Test status
Simulation time 22017818 ps
CPU time 1.11 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 218784 kb
Host smart-214a067d-ac9b-4736-b6c9-b1bb3252b539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942310690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.942310690
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.3401782533
Short name T110
Test name
Test status
Simulation time 27292523 ps
CPU time 1.18 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 219724 kb
Host smart-0dce6131-82bb-4eba-a7f6-23b8c62bac0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401782533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3401782533
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1449845990
Short name T966
Test name
Test status
Simulation time 76357619 ps
CPU time 1.32 seconds
Started Aug 16 06:22:43 PM PDT 24
Finished Aug 16 06:22:45 PM PDT 24
Peak memory 217352 kb
Host smart-5c108c76-3365-449c-ae1c-2adc9d028be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449845990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1449845990
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_alert.3562642747
Short name T288
Test name
Test status
Simulation time 24446331 ps
CPU time 1.17 seconds
Started Aug 16 06:22:41 PM PDT 24
Finished Aug 16 06:22:42 PM PDT 24
Peak memory 218812 kb
Host smart-90323981-b788-47ee-85c1-5a2c608ce406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562642747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.3562642747
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.2606464859
Short name T161
Test name
Test status
Simulation time 167297330 ps
CPU time 1.16 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 215368 kb
Host smart-81d70425-8691-4fd2-b206-e49ca7cbfcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606464859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2606464859
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3916876273
Short name T477
Test name
Test status
Simulation time 64601732 ps
CPU time 1.34 seconds
Started Aug 16 06:22:23 PM PDT 24
Finished Aug 16 06:22:25 PM PDT 24
Peak memory 218704 kb
Host smart-bbec3484-ffb7-4651-8a08-e0e72faec8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916876273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3916876273
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.2113339867
Short name T855
Test name
Test status
Simulation time 73711872 ps
CPU time 1.26 seconds
Started Aug 16 06:22:29 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 218812 kb
Host smart-e1d125e3-a298-45c2-9f55-99b1fd4b4c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113339867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.2113339867
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3594399294
Short name T197
Test name
Test status
Simulation time 38953461 ps
CPU time 0.9 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 218340 kb
Host smart-823cfd86-d89a-4b7b-9837-265cdb990ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594399294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3594399294
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3263792619
Short name T845
Test name
Test status
Simulation time 110527992 ps
CPU time 1.62 seconds
Started Aug 16 06:22:18 PM PDT 24
Finished Aug 16 06:22:20 PM PDT 24
Peak memory 219116 kb
Host smart-7043d98e-faa1-4930-8feb-1a8bda4da8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263792619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3263792619
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_alert.2327125121
Short name T747
Test name
Test status
Simulation time 26906029 ps
CPU time 1.21 seconds
Started Aug 16 06:22:28 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 218772 kb
Host smart-2e158054-3613-4b2c-b330-71d31a25292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327125121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2327125121
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/default/76.edn_err.3052534
Short name T4
Test name
Test status
Simulation time 23274612 ps
CPU time 1.21 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:23 PM PDT 24
Peak memory 224284 kb
Host smart-21612b08-a04f-498e-a434-fe70a29dfb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052534 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3052534
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1005250599
Short name T867
Test name
Test status
Simulation time 32518844 ps
CPU time 1.31 seconds
Started Aug 16 06:22:30 PM PDT 24
Finished Aug 16 06:22:31 PM PDT 24
Peak memory 217504 kb
Host smart-6968d484-c73e-4579-903c-77b4dc9d165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005250599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1005250599
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.707051861
Short name T788
Test name
Test status
Simulation time 30053084 ps
CPU time 1.2 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 218460 kb
Host smart-81fec6ec-db00-49a5-8000-d58b3b414705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707051861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.707051861
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.2093166903
Short name T721
Test name
Test status
Simulation time 24951615 ps
CPU time 1.03 seconds
Started Aug 16 06:22:34 PM PDT 24
Finished Aug 16 06:22:35 PM PDT 24
Peak memory 219700 kb
Host smart-5d37e3a7-7f88-4037-8366-b8dd26e171bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093166903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2093166903
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1226957725
Short name T93
Test name
Test status
Simulation time 40400798 ps
CPU time 1.22 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 220280 kb
Host smart-a4d645a7-60db-4218-88b8-dfdadfb88544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226957725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1226957725
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.2198976486
Short name T393
Test name
Test status
Simulation time 27166016 ps
CPU time 1.2 seconds
Started Aug 16 06:22:56 PM PDT 24
Finished Aug 16 06:22:57 PM PDT 24
Peak memory 219588 kb
Host smart-4e3f3c9c-65b9-4cf1-aa5e-25a59f34d607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198976486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.2198976486
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_genbits.379713217
Short name T768
Test name
Test status
Simulation time 59444765 ps
CPU time 1.5 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:23 PM PDT 24
Peak memory 218608 kb
Host smart-8e0c5d33-aab9-44d3-968f-066ce117a114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379713217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.379713217
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.3627638972
Short name T538
Test name
Test status
Simulation time 22636864 ps
CPU time 1.16 seconds
Started Aug 16 06:22:44 PM PDT 24
Finished Aug 16 06:22:45 PM PDT 24
Peak memory 218720 kb
Host smart-1d79a0b2-aeae-4456-968c-53d85ce29aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627638972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.3627638972
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.12956965
Short name T154
Test name
Test status
Simulation time 66047883 ps
CPU time 0.86 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 218524 kb
Host smart-d7118ceb-4820-4610-a982-f0b911d9935f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12956965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.12956965
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.881799431
Short name T742
Test name
Test status
Simulation time 73763425 ps
CPU time 1.24 seconds
Started Aug 16 06:22:20 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 217444 kb
Host smart-09c5d8e0-ddb4-444f-9e8e-6d73e624d3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881799431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.881799431
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.548183142
Short name T792
Test name
Test status
Simulation time 48678759 ps
CPU time 1.23 seconds
Started Aug 16 06:21:07 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 218964 kb
Host smart-38144c50-430c-49de-9b71-c0e92ea53864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548183142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.548183142
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3090621766
Short name T360
Test name
Test status
Simulation time 75376440 ps
CPU time 0.93 seconds
Started Aug 16 06:21:17 PM PDT 24
Finished Aug 16 06:21:18 PM PDT 24
Peak memory 206808 kb
Host smart-08e6b7c2-d9ee-4a98-bf7f-de4e1a432765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090621766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3090621766
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2262612412
Short name T725
Test name
Test status
Simulation time 15389939 ps
CPU time 0.8 seconds
Started Aug 16 06:21:07 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 215428 kb
Host smart-eb91b707-46ee-4c82-ba12-119a817b0eef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262612412 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2262612412
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2327675342
Short name T118
Test name
Test status
Simulation time 40664731 ps
CPU time 1.32 seconds
Started Aug 16 06:21:06 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 216996 kb
Host smart-4788f331-0975-40df-9e48-8275a70e2621
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327675342 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2327675342
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3693433144
Short name T555
Test name
Test status
Simulation time 47775952 ps
CPU time 1.12 seconds
Started Aug 16 06:21:08 PM PDT 24
Finished Aug 16 06:21:09 PM PDT 24
Peak memory 224128 kb
Host smart-13dbb2ae-9594-4b35-b688-fbc6eb7aeab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693433144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3693433144
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2249728155
Short name T433
Test name
Test status
Simulation time 69553796 ps
CPU time 1.19 seconds
Started Aug 16 06:21:08 PM PDT 24
Finished Aug 16 06:21:09 PM PDT 24
Peak memory 218792 kb
Host smart-4f45d01e-aca7-460c-9c17-a06ec40a7d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249728155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2249728155
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1172382389
Short name T864
Test name
Test status
Simulation time 24847848 ps
CPU time 1.02 seconds
Started Aug 16 06:21:07 PM PDT 24
Finished Aug 16 06:21:08 PM PDT 24
Peak memory 215560 kb
Host smart-8e7a2f1c-7339-461f-94ac-f1772f1ffb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172382389 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1172382389
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.435707426
Short name T291
Test name
Test status
Simulation time 25657033 ps
CPU time 0.93 seconds
Started Aug 16 06:21:09 PM PDT 24
Finished Aug 16 06:21:10 PM PDT 24
Peak memory 207176 kb
Host smart-3bfd43ad-5144-4f7a-b724-9459aea80d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435707426 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.435707426
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.979545429
Short name T90
Test name
Test status
Simulation time 41658206 ps
CPU time 0.92 seconds
Started Aug 16 06:21:09 PM PDT 24
Finished Aug 16 06:21:10 PM PDT 24
Peak memory 215560 kb
Host smart-a9340061-73f0-4b74-971c-47c3d86b30f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979545429 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.979545429
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2578461611
Short name T577
Test name
Test status
Simulation time 255000007 ps
CPU time 5.39 seconds
Started Aug 16 06:21:12 PM PDT 24
Finished Aug 16 06:21:17 PM PDT 24
Peak memory 215380 kb
Host smart-79959789-34e8-4df9-8e70-f270bc8bc793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578461611 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2578461611
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1410537763
Short name T219
Test name
Test status
Simulation time 2584846005 ps
CPU time 69.01 seconds
Started Aug 16 06:21:08 PM PDT 24
Finished Aug 16 06:22:17 PM PDT 24
Peak memory 218352 kb
Host smart-a3cdd013-db30-4abd-97ce-7b5f00fbc22c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410537763 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1410537763
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_alert.3626441270
Short name T621
Test name
Test status
Simulation time 52739401 ps
CPU time 1.13 seconds
Started Aug 16 06:22:22 PM PDT 24
Finished Aug 16 06:22:23 PM PDT 24
Peak memory 218740 kb
Host smart-da180b13-38e9-4438-aa67-2056e21a38c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626441270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.3626441270
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/80.edn_err.2429749951
Short name T643
Test name
Test status
Simulation time 24702205 ps
CPU time 0.88 seconds
Started Aug 16 06:22:23 PM PDT 24
Finished Aug 16 06:22:24 PM PDT 24
Peak memory 218336 kb
Host smart-532ed83b-887e-45eb-96e5-dec2f077778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429749951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2429749951
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2941984723
Short name T413
Test name
Test status
Simulation time 28193989 ps
CPU time 1.29 seconds
Started Aug 16 06:22:22 PM PDT 24
Finished Aug 16 06:22:23 PM PDT 24
Peak memory 218484 kb
Host smart-82b59429-6eef-4141-8005-31df1fc64b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941984723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2941984723
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.2965966421
Short name T211
Test name
Test status
Simulation time 98965682 ps
CPU time 1.33 seconds
Started Aug 16 06:22:23 PM PDT 24
Finished Aug 16 06:22:24 PM PDT 24
Peak memory 219472 kb
Host smart-be433def-74a1-4dd7-aabf-07f98251adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965966421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.2965966421
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.1026030461
Short name T396
Test name
Test status
Simulation time 19202806 ps
CPU time 1.08 seconds
Started Aug 16 06:22:28 PM PDT 24
Finished Aug 16 06:22:29 PM PDT 24
Peak memory 219732 kb
Host smart-d9bac5a4-08da-44eb-82be-7bb2897cfa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026030461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1026030461
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_alert.3210447454
Short name T785
Test name
Test status
Simulation time 221875398 ps
CPU time 1.29 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:23 PM PDT 24
Peak memory 215764 kb
Host smart-24380b5e-1b25-48ad-b673-0a4a925a94e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210447454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.3210447454
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.745665744
Short name T936
Test name
Test status
Simulation time 34907136 ps
CPU time 0.93 seconds
Started Aug 16 06:22:23 PM PDT 24
Finished Aug 16 06:22:24 PM PDT 24
Peak memory 223900 kb
Host smart-ce4e33bd-82c3-47f5-b991-a2b5c9be0673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745665744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.745665744
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_alert.2991191787
Short name T423
Test name
Test status
Simulation time 91278813 ps
CPU time 1.2 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:23 PM PDT 24
Peak memory 215692 kb
Host smart-2d798aa3-6861-4581-934f-fa5d909f6efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991191787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.2991191787
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.4025120966
Short name T916
Test name
Test status
Simulation time 20617370 ps
CPU time 1.13 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 219796 kb
Host smart-8daebf92-cd25-439b-9dff-b6d3b2cac970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025120966 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4025120966
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.4028303812
Short name T753
Test name
Test status
Simulation time 34061940 ps
CPU time 1.28 seconds
Started Aug 16 06:22:34 PM PDT 24
Finished Aug 16 06:22:36 PM PDT 24
Peak memory 220540 kb
Host smart-50bd7bf3-bb58-4b26-800e-3390c6529173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028303812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4028303812
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.1639161024
Short name T166
Test name
Test status
Simulation time 52406451 ps
CPU time 1.23 seconds
Started Aug 16 06:22:22 PM PDT 24
Finished Aug 16 06:22:24 PM PDT 24
Peak memory 220840 kb
Host smart-8b2b3071-c744-4617-b331-ddc813d4591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639161024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.1639161024
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.773606354
Short name T151
Test name
Test status
Simulation time 51245863 ps
CPU time 0.84 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 218292 kb
Host smart-cb529bc3-49a3-48f3-9533-ced1093e865c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773606354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.773606354
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3475151620
Short name T758
Test name
Test status
Simulation time 167965197 ps
CPU time 1.13 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:23 PM PDT 24
Peak memory 217544 kb
Host smart-821d5523-9c57-4fb0-a364-ced864862920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475151620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3475151620
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.2367069027
Short name T618
Test name
Test status
Simulation time 45976067 ps
CPU time 1.25 seconds
Started Aug 16 06:22:58 PM PDT 24
Finished Aug 16 06:22:59 PM PDT 24
Peak memory 219572 kb
Host smart-6a3e6ac6-9a5a-4efb-9c1d-f16c7076354b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367069027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.2367069027
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.4227810562
Short name T180
Test name
Test status
Simulation time 24938367 ps
CPU time 1.07 seconds
Started Aug 16 06:22:19 PM PDT 24
Finished Aug 16 06:22:21 PM PDT 24
Peak memory 224196 kb
Host smart-79f2dec5-6990-4e87-84f6-a20f7b5b07b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227810562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.4227810562
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2308593005
Short name T301
Test name
Test status
Simulation time 54606532 ps
CPU time 1.79 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:23 PM PDT 24
Peak memory 218640 kb
Host smart-35f05761-2ee5-43e3-b96e-274871eb1899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308593005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2308593005
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.2790984406
Short name T602
Test name
Test status
Simulation time 70808811 ps
CPU time 1.25 seconds
Started Aug 16 06:22:29 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 220820 kb
Host smart-a920bb3c-dd0b-40dc-b1e9-e3cde4dfc203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790984406 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.2790984406
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2589104130
Short name T861
Test name
Test status
Simulation time 25982579 ps
CPU time 1.09 seconds
Started Aug 16 06:22:45 PM PDT 24
Finished Aug 16 06:22:46 PM PDT 24
Peak memory 229776 kb
Host smart-b430b3e1-9bb7-48ec-b2c4-0a029196f1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589104130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2589104130
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.672782463
Short name T691
Test name
Test status
Simulation time 45443666 ps
CPU time 0.98 seconds
Started Aug 16 06:22:36 PM PDT 24
Finished Aug 16 06:22:37 PM PDT 24
Peak memory 217248 kb
Host smart-2f7143f4-12ee-49e3-baf7-727bd136b6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672782463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.672782463
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.845606701
Short name T121
Test name
Test status
Simulation time 110627963 ps
CPU time 1.4 seconds
Started Aug 16 06:22:22 PM PDT 24
Finished Aug 16 06:22:24 PM PDT 24
Peak memory 218484 kb
Host smart-73a31a71-4973-49c4-be96-88c6bc49e944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845606701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.845606701
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.3931220397
Short name T820
Test name
Test status
Simulation time 32558465 ps
CPU time 1.17 seconds
Started Aug 16 06:22:44 PM PDT 24
Finished Aug 16 06:22:46 PM PDT 24
Peak memory 224200 kb
Host smart-d0951db4-aa38-4c02-b544-d7dd1d996ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931220397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3931220397
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1713467794
Short name T974
Test name
Test status
Simulation time 37917267 ps
CPU time 1.46 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:23 PM PDT 24
Peak memory 219796 kb
Host smart-cd770200-fe5e-4dad-851f-bf2cca597f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713467794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1713467794
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.519929761
Short name T972
Test name
Test status
Simulation time 80787014 ps
CPU time 1.19 seconds
Started Aug 16 06:22:31 PM PDT 24
Finished Aug 16 06:22:33 PM PDT 24
Peak memory 215736 kb
Host smart-c7e432c4-0ab9-4b79-a25c-63291eaea656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519929761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.519929761
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.3097175630
Short name T761
Test name
Test status
Simulation time 182666072 ps
CPU time 1 seconds
Started Aug 16 06:22:47 PM PDT 24
Finished Aug 16 06:22:48 PM PDT 24
Peak memory 218652 kb
Host smart-2dc76406-3974-4298-ae5b-27cc5b1b8f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097175630 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3097175630
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.945253586
Short name T771
Test name
Test status
Simulation time 40899738 ps
CPU time 1.24 seconds
Started Aug 16 06:22:30 PM PDT 24
Finished Aug 16 06:22:32 PM PDT 24
Peak memory 219556 kb
Host smart-34247d54-d55f-4434-8cc0-657a6a97179c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945253586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.945253586
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.2576048453
Short name T115
Test name
Test status
Simulation time 47280620 ps
CPU time 1.18 seconds
Started Aug 16 06:22:21 PM PDT 24
Finished Aug 16 06:22:22 PM PDT 24
Peak memory 218672 kb
Host smart-5e7c4baf-0795-4b67-a686-cca8ab198a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576048453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.2576048453
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.775226364
Short name T174
Test name
Test status
Simulation time 19311006 ps
CPU time 1.18 seconds
Started Aug 16 06:22:24 PM PDT 24
Finished Aug 16 06:22:25 PM PDT 24
Peak memory 224132 kb
Host smart-9f62bdcf-2d76-4e26-be82-fb8cba09bc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775226364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.775226364
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.931871721
Short name T697
Test name
Test status
Simulation time 52189092 ps
CPU time 1.57 seconds
Started Aug 16 06:22:23 PM PDT 24
Finished Aug 16 06:22:24 PM PDT 24
Peak memory 218708 kb
Host smart-d504a1b3-3b9c-49bc-9c17-7b78c12b42c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931871721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.931871721
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2420126246
Short name T106
Test name
Test status
Simulation time 66523825 ps
CPU time 1.05 seconds
Started Aug 16 06:21:30 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 219796 kb
Host smart-dfee54ac-1b2d-4510-8505-ca0649349cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420126246 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2420126246
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.887365705
Short name T59
Test name
Test status
Simulation time 23060529 ps
CPU time 0.91 seconds
Started Aug 16 06:21:17 PM PDT 24
Finished Aug 16 06:21:18 PM PDT 24
Peak memory 206628 kb
Host smart-73121922-e6f0-4f95-9b25-d49daf468b67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887365705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.887365705
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3588236729
Short name T202
Test name
Test status
Simulation time 46247868 ps
CPU time 0.89 seconds
Started Aug 16 06:21:30 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 215424 kb
Host smart-0acc4464-e855-4756-a5cb-4cb81350c17e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588236729 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3588236729
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1993755669
Short name T623
Test name
Test status
Simulation time 26536191 ps
CPU time 1.03 seconds
Started Aug 16 06:21:30 PM PDT 24
Finished Aug 16 06:21:31 PM PDT 24
Peak memory 218460 kb
Host smart-d3002390-76ef-42de-a10f-b71afa800bde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993755669 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1993755669
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3746175855
Short name T52
Test name
Test status
Simulation time 62952690 ps
CPU time 1.25 seconds
Started Aug 16 06:21:16 PM PDT 24
Finished Aug 16 06:21:17 PM PDT 24
Peak memory 225748 kb
Host smart-ed3f2d14-a9ca-4dbd-9c59-491eb6fb7eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746175855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3746175855
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2515614993
Short name T324
Test name
Test status
Simulation time 95307394 ps
CPU time 1.25 seconds
Started Aug 16 06:21:08 PM PDT 24
Finished Aug 16 06:21:09 PM PDT 24
Peak memory 219640 kb
Host smart-e55b75f9-b9fd-42cd-8dd4-0c472fca54e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515614993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2515614993
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.3153441074
Short name T22
Test name
Test status
Simulation time 14554085 ps
CPU time 1 seconds
Started Aug 16 06:21:21 PM PDT 24
Finished Aug 16 06:21:22 PM PDT 24
Peak memory 207216 kb
Host smart-cdc0e3f9-e44d-42c2-ab89-6857427b98b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153441074 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3153441074
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.987040238
Short name T896
Test name
Test status
Simulation time 19671475 ps
CPU time 0.94 seconds
Started Aug 16 06:21:20 PM PDT 24
Finished Aug 16 06:21:21 PM PDT 24
Peak memory 207216 kb
Host smart-14cd3c74-18ad-41ba-80fd-1f6782bb2c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987040238 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.987040238
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.4134232148
Short name T925
Test name
Test status
Simulation time 266301567 ps
CPU time 2.26 seconds
Started Aug 16 06:21:14 PM PDT 24
Finished Aug 16 06:21:17 PM PDT 24
Peak memory 217472 kb
Host smart-2a36f890-2661-4e7f-b47a-96cf96473c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134232148 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.4134232148
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/90.edn_alert.3304716812
Short name T40
Test name
Test status
Simulation time 162276003 ps
CPU time 1.27 seconds
Started Aug 16 06:22:29 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 219340 kb
Host smart-82826e5f-3d27-4192-b9fe-9faef930edaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304716812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.3304716812
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/90.edn_err.3224933754
Short name T144
Test name
Test status
Simulation time 33900828 ps
CPU time 1.11 seconds
Started Aug 16 06:22:29 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 220876 kb
Host smart-c86c0a07-6184-48ad-a0c0-6e524d29b334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224933754 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3224933754
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3869338985
Short name T422
Test name
Test status
Simulation time 196827150 ps
CPU time 1.58 seconds
Started Aug 16 06:22:26 PM PDT 24
Finished Aug 16 06:22:28 PM PDT 24
Peak memory 218808 kb
Host smart-2d61a1c6-78bc-4442-90c7-968ed3f4cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869338985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3869338985
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.407411528
Short name T814
Test name
Test status
Simulation time 26871399 ps
CPU time 1.22 seconds
Started Aug 16 06:22:28 PM PDT 24
Finished Aug 16 06:22:29 PM PDT 24
Peak memory 220708 kb
Host smart-1150a2ac-67bb-4e34-90ed-0594de5134ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407411528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.407411528
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.211082062
Short name T135
Test name
Test status
Simulation time 28202879 ps
CPU time 1.42 seconds
Started Aug 16 06:22:29 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 230040 kb
Host smart-d6c36071-dc29-463e-9eb3-ae872ada0226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211082062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.211082062
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3702796706
Short name T531
Test name
Test status
Simulation time 75722827 ps
CPU time 1.16 seconds
Started Aug 16 06:22:28 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 220376 kb
Host smart-d6a2ef97-be24-4a3d-8e2a-9921180197b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702796706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3702796706
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.1546786175
Short name T486
Test name
Test status
Simulation time 168010885 ps
CPU time 1.14 seconds
Started Aug 16 06:22:25 PM PDT 24
Finished Aug 16 06:22:26 PM PDT 24
Peak memory 218660 kb
Host smart-86e7151f-b8bb-4dce-854f-8320fded5aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546786175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.1546786175
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.2483071126
Short name T160
Test name
Test status
Simulation time 18580543 ps
CPU time 1.04 seconds
Started Aug 16 06:22:46 PM PDT 24
Finished Aug 16 06:22:47 PM PDT 24
Peak memory 218392 kb
Host smart-82a5b060-9bc2-4ba3-8227-c938b71ff897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483071126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2483071126
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.292260273
Short name T323
Test name
Test status
Simulation time 26841008 ps
CPU time 1.22 seconds
Started Aug 16 06:22:52 PM PDT 24
Finished Aug 16 06:22:54 PM PDT 24
Peak memory 219584 kb
Host smart-e4fdc1dc-556a-40eb-a775-0db035cb584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292260273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.292260273
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.1946391210
Short name T267
Test name
Test status
Simulation time 320633943 ps
CPU time 1.44 seconds
Started Aug 16 06:22:30 PM PDT 24
Finished Aug 16 06:22:31 PM PDT 24
Peak memory 218376 kb
Host smart-1d6ccbab-b585-4569-b469-f8c0c859eb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946391210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1946391210
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.3592308529
Short name T947
Test name
Test status
Simulation time 38407097 ps
CPU time 0.94 seconds
Started Aug 16 06:22:31 PM PDT 24
Finished Aug 16 06:22:32 PM PDT 24
Peak memory 218328 kb
Host smart-fcabbb36-3e07-4407-9466-1534bbfc2be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592308529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3592308529
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3799439083
Short name T316
Test name
Test status
Simulation time 79856973 ps
CPU time 1.52 seconds
Started Aug 16 06:22:47 PM PDT 24
Finished Aug 16 06:22:49 PM PDT 24
Peak memory 218556 kb
Host smart-8a28b21a-8ed0-4fd6-be3d-a77f19712b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799439083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3799439083
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.521108095
Short name T424
Test name
Test status
Simulation time 42029701 ps
CPU time 1.24 seconds
Started Aug 16 06:22:44 PM PDT 24
Finished Aug 16 06:22:45 PM PDT 24
Peak memory 217548 kb
Host smart-95e68220-f900-4ccb-a200-d4579af69a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521108095 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.521108095
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.2222995776
Short name T565
Test name
Test status
Simulation time 32636555 ps
CPU time 0.99 seconds
Started Aug 16 06:22:43 PM PDT 24
Finished Aug 16 06:22:44 PM PDT 24
Peak memory 223880 kb
Host smart-841f55a3-1412-45d8-b8d2-fd245a2b4147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222995776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2222995776
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.386145900
Short name T959
Test name
Test status
Simulation time 303612464 ps
CPU time 1.47 seconds
Started Aug 16 06:22:26 PM PDT 24
Finished Aug 16 06:22:28 PM PDT 24
Peak memory 217488 kb
Host smart-41f10abd-114b-4b8f-9bf4-01dad88d6a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386145900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.386145900
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.570996717
Short name T888
Test name
Test status
Simulation time 61142159 ps
CPU time 1.21 seconds
Started Aug 16 06:22:49 PM PDT 24
Finished Aug 16 06:22:51 PM PDT 24
Peak memory 219904 kb
Host smart-0e2c299e-60d5-42bb-8ba9-2ac1a7b6decd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570996717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.570996717
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.3190369534
Short name T204
Test name
Test status
Simulation time 26805679 ps
CPU time 1.2 seconds
Started Aug 16 06:22:30 PM PDT 24
Finished Aug 16 06:22:31 PM PDT 24
Peak memory 217372 kb
Host smart-ac2db5d5-5748-4f55-b2d9-dc830b3bbb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190369534 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3190369534
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2886011469
Short name T969
Test name
Test status
Simulation time 43867263 ps
CPU time 1.5 seconds
Started Aug 16 06:22:26 PM PDT 24
Finished Aug 16 06:22:28 PM PDT 24
Peak memory 217416 kb
Host smart-46a202db-1708-4cf5-8942-ebdf55dcec23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886011469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2886011469
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.2413550077
Short name T662
Test name
Test status
Simulation time 32024018 ps
CPU time 1.32 seconds
Started Aug 16 06:22:28 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 215772 kb
Host smart-f9843c90-f8d0-416a-8061-80c7faf0080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413550077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.2413550077
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.3560145119
Short name T170
Test name
Test status
Simulation time 24434323 ps
CPU time 0.96 seconds
Started Aug 16 06:22:36 PM PDT 24
Finished Aug 16 06:22:37 PM PDT 24
Peak memory 223888 kb
Host smart-20876061-c379-47fb-8342-fc413feac486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560145119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3560145119
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1941000085
Short name T668
Test name
Test status
Simulation time 127124597 ps
CPU time 1.55 seconds
Started Aug 16 06:22:28 PM PDT 24
Finished Aug 16 06:22:29 PM PDT 24
Peak memory 220280 kb
Host smart-dbf044b9-3fce-43de-a596-76cc9cb2ee4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941000085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1941000085
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.975959808
Short name T179
Test name
Test status
Simulation time 74072772 ps
CPU time 1.17 seconds
Started Aug 16 06:22:44 PM PDT 24
Finished Aug 16 06:22:45 PM PDT 24
Peak memory 220540 kb
Host smart-895162c9-959d-4482-98a2-3f9a898475a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975959808 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.975959808
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.94383064
Short name T417
Test name
Test status
Simulation time 71157161 ps
CPU time 1.05 seconds
Started Aug 16 06:22:31 PM PDT 24
Finished Aug 16 06:22:32 PM PDT 24
Peak memory 219728 kb
Host smart-0601f165-6b99-4f69-95f7-affd8287664e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94383064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.94383064
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_alert.239293920
Short name T604
Test name
Test status
Simulation time 89327224 ps
CPU time 1.25 seconds
Started Aug 16 06:22:53 PM PDT 24
Finished Aug 16 06:22:54 PM PDT 24
Peak memory 221864 kb
Host smart-2f21afab-06e1-4aba-a3d4-7b8d73e1961d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239293920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.239293920
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.112320861
Short name T356
Test name
Test status
Simulation time 20386837 ps
CPU time 1.09 seconds
Started Aug 16 06:22:29 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 219652 kb
Host smart-af85add9-4954-41ea-a1ae-3402461f4cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112320861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.112320861
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3022530554
Short name T321
Test name
Test status
Simulation time 77429598 ps
CPU time 1.42 seconds
Started Aug 16 06:22:28 PM PDT 24
Finished Aug 16 06:22:29 PM PDT 24
Peak memory 219084 kb
Host smart-ec0de77b-f8bb-4779-9eec-f1135b70bb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022530554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3022530554
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.3111452038
Short name T398
Test name
Test status
Simulation time 88161092 ps
CPU time 1.22 seconds
Started Aug 16 06:22:30 PM PDT 24
Finished Aug 16 06:22:31 PM PDT 24
Peak memory 219516 kb
Host smart-2863cb92-8ecf-4f25-aff2-230006d9be6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111452038 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.3111452038
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_err.3056468007
Short name T515
Test name
Test status
Simulation time 21687447 ps
CPU time 0.94 seconds
Started Aug 16 06:22:29 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 218668 kb
Host smart-70a9754b-bb57-4d65-9996-4359a86fa778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056468007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3056468007
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1877529137
Short name T827
Test name
Test status
Simulation time 95469508 ps
CPU time 1.26 seconds
Started Aug 16 06:22:29 PM PDT 24
Finished Aug 16 06:22:30 PM PDT 24
Peak memory 217280 kb
Host smart-5ca5db91-f5a2-4e18-800a-dfa96ec559db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877529137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1877529137
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%