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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.69 98.25 93.97 97.02 91.28 96.37 99.77 93.18


Total test records in report: 1111
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T1012 /workspace/coverage/cover_reg_top/42.edn_intr_test.3448887299 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:53 PM PDT 24 55329249 ps
T1013 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1888043849 Aug 17 06:26:47 PM PDT 24 Aug 17 06:26:48 PM PDT 24 62985013 ps
T1014 /workspace/coverage/cover_reg_top/3.edn_intr_test.1228062987 Aug 17 06:26:49 PM PDT 24 Aug 17 06:26:50 PM PDT 24 16048130 ps
T1015 /workspace/coverage/cover_reg_top/11.edn_intr_test.516096898 Aug 17 06:26:53 PM PDT 24 Aug 17 06:26:54 PM PDT 24 30414848 ps
T253 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1393438979 Aug 17 06:26:40 PM PDT 24 Aug 17 06:26:42 PM PDT 24 37703226 ps
T1016 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3164344352 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:53 PM PDT 24 137156653 ps
T1017 /workspace/coverage/cover_reg_top/46.edn_intr_test.766019409 Aug 17 06:26:56 PM PDT 24 Aug 17 06:26:57 PM PDT 24 36868855 ps
T1018 /workspace/coverage/cover_reg_top/25.edn_intr_test.3409840484 Aug 17 06:27:01 PM PDT 24 Aug 17 06:27:02 PM PDT 24 60417155 ps
T1019 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1853931516 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:53 PM PDT 24 38345329 ps
T1020 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1046178433 Aug 17 06:26:43 PM PDT 24 Aug 17 06:26:44 PM PDT 24 37963112 ps
T284 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2668916586 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:53 PM PDT 24 94095778 ps
T1021 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.59261521 Aug 17 06:26:55 PM PDT 24 Aug 17 06:26:56 PM PDT 24 21453841 ps
T1022 /workspace/coverage/cover_reg_top/14.edn_tl_errors.968457805 Aug 17 06:26:57 PM PDT 24 Aug 17 06:26:59 PM PDT 24 36878926 ps
T1023 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2846966093 Aug 17 06:26:55 PM PDT 24 Aug 17 06:26:57 PM PDT 24 173858823 ps
T1024 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3218280639 Aug 17 06:26:40 PM PDT 24 Aug 17 06:26:41 PM PDT 24 16263532 ps
T1025 /workspace/coverage/cover_reg_top/1.edn_tl_errors.226537661 Aug 17 06:26:30 PM PDT 24 Aug 17 06:26:33 PM PDT 24 71114187 ps
T1026 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2064415385 Aug 17 06:26:38 PM PDT 24 Aug 17 06:26:39 PM PDT 24 64093469 ps
T1027 /workspace/coverage/cover_reg_top/24.edn_intr_test.4125628044 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:52 PM PDT 24 15184677 ps
T254 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2848885933 Aug 17 06:26:44 PM PDT 24 Aug 17 06:26:45 PM PDT 24 17531010 ps
T1028 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3259469655 Aug 17 06:26:54 PM PDT 24 Aug 17 06:26:57 PM PDT 24 87772043 ps
T1029 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3370504199 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:53 PM PDT 24 176011921 ps
T1030 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1936720790 Aug 17 06:26:47 PM PDT 24 Aug 17 06:26:48 PM PDT 24 19812780 ps
T255 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3397105211 Aug 17 06:26:45 PM PDT 24 Aug 17 06:26:46 PM PDT 24 24673356 ps
T1031 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1143228348 Aug 17 06:27:00 PM PDT 24 Aug 17 06:27:01 PM PDT 24 112805602 ps
T1032 /workspace/coverage/cover_reg_top/48.edn_intr_test.4104079944 Aug 17 06:26:55 PM PDT 24 Aug 17 06:26:56 PM PDT 24 34660117 ps
T1033 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3194814242 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:53 PM PDT 24 87547090 ps
T1034 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2650399235 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:54 PM PDT 24 183704696 ps
T256 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2763110226 Aug 17 06:26:30 PM PDT 24 Aug 17 06:26:31 PM PDT 24 201431087 ps
T257 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3544755670 Aug 17 06:26:29 PM PDT 24 Aug 17 06:26:30 PM PDT 24 24356422 ps
T1035 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3178259781 Aug 17 06:26:40 PM PDT 24 Aug 17 06:26:42 PM PDT 24 76206696 ps
T1036 /workspace/coverage/cover_reg_top/39.edn_intr_test.3656079612 Aug 17 06:27:01 PM PDT 24 Aug 17 06:27:07 PM PDT 24 21448561 ps
T1037 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1284726092 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:53 PM PDT 24 38781643 ps
T1038 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2929062948 Aug 17 06:26:35 PM PDT 24 Aug 17 06:26:37 PM PDT 24 97380300 ps
T1039 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4268998619 Aug 17 06:26:45 PM PDT 24 Aug 17 06:26:46 PM PDT 24 18475239 ps
T1040 /workspace/coverage/cover_reg_top/4.edn_intr_test.130815888 Aug 17 06:26:33 PM PDT 24 Aug 17 06:26:34 PM PDT 24 37886032 ps
T1041 /workspace/coverage/cover_reg_top/28.edn_intr_test.3876359352 Aug 17 06:26:53 PM PDT 24 Aug 17 06:26:54 PM PDT 24 14091905 ps
T1042 /workspace/coverage/cover_reg_top/10.edn_intr_test.2900367237 Aug 17 06:26:53 PM PDT 24 Aug 17 06:26:54 PM PDT 24 38029274 ps
T1043 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1542441745 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:54 PM PDT 24 386816887 ps
T1044 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1299740473 Aug 17 06:26:12 PM PDT 24 Aug 17 06:26:13 PM PDT 24 131790967 ps
T1045 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.535445765 Aug 17 06:26:34 PM PDT 24 Aug 17 06:26:38 PM PDT 24 66352709 ps
T1046 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1214762962 Aug 17 06:26:54 PM PDT 24 Aug 17 06:26:56 PM PDT 24 128086171 ps
T1047 /workspace/coverage/cover_reg_top/18.edn_intr_test.2836661034 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:53 PM PDT 24 36344757 ps
T258 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2149688519 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:58 PM PDT 24 14005884 ps
T1048 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.690800895 Aug 17 06:26:43 PM PDT 24 Aug 17 06:26:45 PM PDT 24 69362417 ps
T1049 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3589169410 Aug 17 06:26:43 PM PDT 24 Aug 17 06:26:45 PM PDT 24 19980243 ps
T1050 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2499287365 Aug 17 06:26:43 PM PDT 24 Aug 17 06:26:47 PM PDT 24 108293584 ps
T1051 /workspace/coverage/cover_reg_top/32.edn_intr_test.1271248219 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:53 PM PDT 24 14664730 ps
T1052 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3204592586 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:53 PM PDT 24 176212058 ps
T1053 /workspace/coverage/cover_reg_top/13.edn_intr_test.1059782870 Aug 17 06:26:53 PM PDT 24 Aug 17 06:26:54 PM PDT 24 12086718 ps
T1054 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3579219685 Aug 17 06:26:33 PM PDT 24 Aug 17 06:26:36 PM PDT 24 135375479 ps
T1055 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3808648731 Aug 17 06:26:53 PM PDT 24 Aug 17 06:26:54 PM PDT 24 14454697 ps
T1056 /workspace/coverage/cover_reg_top/29.edn_intr_test.640202017 Aug 17 06:26:50 PM PDT 24 Aug 17 06:26:51 PM PDT 24 28913289 ps
T1057 /workspace/coverage/cover_reg_top/44.edn_intr_test.2256384565 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:53 PM PDT 24 35897156 ps
T1058 /workspace/coverage/cover_reg_top/23.edn_intr_test.1225576355 Aug 17 06:26:59 PM PDT 24 Aug 17 06:27:05 PM PDT 24 24881867 ps
T1059 /workspace/coverage/cover_reg_top/15.edn_intr_test.2350069796 Aug 17 06:26:50 PM PDT 24 Aug 17 06:26:51 PM PDT 24 27392683 ps
T1060 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1900543046 Aug 17 06:26:56 PM PDT 24 Aug 17 06:27:01 PM PDT 24 127185898 ps
T1061 /workspace/coverage/cover_reg_top/43.edn_intr_test.1420374932 Aug 17 06:26:54 PM PDT 24 Aug 17 06:26:54 PM PDT 24 48171013 ps
T1062 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2015678628 Aug 17 06:26:33 PM PDT 24 Aug 17 06:26:35 PM PDT 24 40496249 ps
T1063 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1207466271 Aug 17 06:26:28 PM PDT 24 Aug 17 06:26:36 PM PDT 24 291690334 ps
T1064 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3087432280 Aug 17 06:26:54 PM PDT 24 Aug 17 06:26:57 PM PDT 24 355529143 ps
T1065 /workspace/coverage/cover_reg_top/12.edn_intr_test.1653466277 Aug 17 06:26:50 PM PDT 24 Aug 17 06:26:51 PM PDT 24 63571709 ps
T1066 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.716757784 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:53 PM PDT 24 56328882 ps
T1067 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1886685994 Aug 17 06:26:47 PM PDT 24 Aug 17 06:26:48 PM PDT 24 26321634 ps
T1068 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2261995477 Aug 17 06:26:43 PM PDT 24 Aug 17 06:26:45 PM PDT 24 54364940 ps
T1069 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.944772530 Aug 17 06:26:29 PM PDT 24 Aug 17 06:26:32 PM PDT 24 96883857 ps
T1070 /workspace/coverage/cover_reg_top/40.edn_intr_test.4023348173 Aug 17 06:26:55 PM PDT 24 Aug 17 06:26:56 PM PDT 24 12223634 ps
T1071 /workspace/coverage/cover_reg_top/15.edn_tl_errors.813013758 Aug 17 06:26:45 PM PDT 24 Aug 17 06:26:47 PM PDT 24 61717875 ps
T1072 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3565586554 Aug 17 06:26:35 PM PDT 24 Aug 17 06:26:38 PM PDT 24 361655904 ps
T1073 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1689339554 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:54 PM PDT 24 50398019 ps
T1074 /workspace/coverage/cover_reg_top/35.edn_intr_test.3224767514 Aug 17 06:26:56 PM PDT 24 Aug 17 06:26:57 PM PDT 24 23386813 ps
T1075 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2828815151 Aug 17 06:26:49 PM PDT 24 Aug 17 06:26:50 PM PDT 24 21798791 ps
T259 /workspace/coverage/cover_reg_top/9.edn_csr_rw.824123891 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:52 PM PDT 24 46853809 ps
T1076 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3871682017 Aug 17 06:26:49 PM PDT 24 Aug 17 06:26:51 PM PDT 24 19127123 ps
T1077 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1290716941 Aug 17 06:26:46 PM PDT 24 Aug 17 06:26:47 PM PDT 24 115304277 ps
T1078 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1410563901 Aug 17 06:26:13 PM PDT 24 Aug 17 06:26:15 PM PDT 24 76452651 ps
T260 /workspace/coverage/cover_reg_top/7.edn_csr_rw.407004079 Aug 17 06:26:40 PM PDT 24 Aug 17 06:26:41 PM PDT 24 11943157 ps
T1079 /workspace/coverage/cover_reg_top/6.edn_intr_test.3953879605 Aug 17 06:26:44 PM PDT 24 Aug 17 06:26:45 PM PDT 24 24148196 ps
T1080 /workspace/coverage/cover_reg_top/26.edn_intr_test.1863011966 Aug 17 06:27:03 PM PDT 24 Aug 17 06:27:04 PM PDT 24 17334557 ps
T1081 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1977435731 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:54 PM PDT 24 74815648 ps
T1082 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1844419589 Aug 17 06:27:05 PM PDT 24 Aug 17 06:27:07 PM PDT 24 88810543 ps
T1083 /workspace/coverage/cover_reg_top/49.edn_intr_test.2674073849 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:54 PM PDT 24 50497559 ps
T1084 /workspace/coverage/cover_reg_top/41.edn_intr_test.399259689 Aug 17 06:26:53 PM PDT 24 Aug 17 06:26:54 PM PDT 24 11683612 ps
T1085 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3248725501 Aug 17 06:26:36 PM PDT 24 Aug 17 06:26:37 PM PDT 24 54841279 ps
T1086 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.496714270 Aug 17 06:26:47 PM PDT 24 Aug 17 06:26:48 PM PDT 24 14681285 ps
T1087 /workspace/coverage/cover_reg_top/30.edn_intr_test.3815375721 Aug 17 06:26:57 PM PDT 24 Aug 17 06:26:58 PM PDT 24 14432694 ps
T261 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1065983533 Aug 17 06:26:37 PM PDT 24 Aug 17 06:26:38 PM PDT 24 14572917 ps
T1088 /workspace/coverage/cover_reg_top/16.edn_intr_test.1005714445 Aug 17 06:26:53 PM PDT 24 Aug 17 06:26:54 PM PDT 24 15472863 ps
T1089 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1148134911 Aug 17 06:26:54 PM PDT 24 Aug 17 06:26:55 PM PDT 24 34796002 ps
T1090 /workspace/coverage/cover_reg_top/27.edn_intr_test.2982947876 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:53 PM PDT 24 14507941 ps
T1091 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2692455919 Aug 17 06:26:54 PM PDT 24 Aug 17 06:27:00 PM PDT 24 30478877 ps
T1092 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1553827324 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:55 PM PDT 24 39327055 ps
T1093 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2246187681 Aug 17 06:26:37 PM PDT 24 Aug 17 06:26:38 PM PDT 24 13424518 ps
T1094 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4065852006 Aug 17 06:26:42 PM PDT 24 Aug 17 06:26:44 PM PDT 24 62231226 ps
T1095 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3646843526 Aug 17 06:26:50 PM PDT 24 Aug 17 06:26:51 PM PDT 24 41246735 ps
T1096 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3010235357 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:53 PM PDT 24 69985825 ps
T1097 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3699315465 Aug 17 06:26:31 PM PDT 24 Aug 17 06:26:33 PM PDT 24 340819336 ps
T1098 /workspace/coverage/cover_reg_top/1.edn_intr_test.3218046600 Aug 17 06:26:38 PM PDT 24 Aug 17 06:26:39 PM PDT 24 75644644 ps
T1099 /workspace/coverage/cover_reg_top/7.edn_intr_test.1449270771 Aug 17 06:26:43 PM PDT 24 Aug 17 06:26:43 PM PDT 24 44797768 ps
T1100 /workspace/coverage/cover_reg_top/22.edn_intr_test.1282109183 Aug 17 06:26:48 PM PDT 24 Aug 17 06:26:49 PM PDT 24 14561941 ps
T1101 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1809553185 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:53 PM PDT 24 41143350 ps
T1102 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3114008909 Aug 17 06:26:47 PM PDT 24 Aug 17 06:26:49 PM PDT 24 92400057 ps
T1103 /workspace/coverage/cover_reg_top/14.edn_intr_test.3508564839 Aug 17 06:26:54 PM PDT 24 Aug 17 06:26:55 PM PDT 24 29934988 ps
T262 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1156884414 Aug 17 06:26:46 PM PDT 24 Aug 17 06:26:48 PM PDT 24 71688699 ps
T1104 /workspace/coverage/cover_reg_top/0.edn_tl_errors.397633732 Aug 17 06:26:21 PM PDT 24 Aug 17 06:26:22 PM PDT 24 35058594 ps
T1105 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3736316985 Aug 17 06:26:50 PM PDT 24 Aug 17 06:26:52 PM PDT 24 102905854 ps
T1106 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2767195342 Aug 17 06:26:52 PM PDT 24 Aug 17 06:26:53 PM PDT 24 103251678 ps
T1107 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.274847141 Aug 17 06:26:47 PM PDT 24 Aug 17 06:26:49 PM PDT 24 425372641 ps
T1108 /workspace/coverage/cover_reg_top/45.edn_intr_test.4064432110 Aug 17 06:26:59 PM PDT 24 Aug 17 06:27:00 PM PDT 24 13867248 ps
T1109 /workspace/coverage/cover_reg_top/9.edn_intr_test.3636252163 Aug 17 06:26:49 PM PDT 24 Aug 17 06:26:50 PM PDT 24 59436348 ps
T1110 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3991695757 Aug 17 06:26:51 PM PDT 24 Aug 17 06:26:53 PM PDT 24 70751399 ps
T1111 /workspace/coverage/cover_reg_top/21.edn_intr_test.2930658 Aug 17 06:26:56 PM PDT 24 Aug 17 06:26:57 PM PDT 24 55273728 ps

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1774916153
Short name T4
Test name
Test status
Simulation time 2504259532 ps
CPU time 57.9 seconds
Started Aug 17 06:30:19 PM PDT 24
Finished Aug 17 06:31:17 PM PDT 24
Peak memory 218596 kb
Host smart-17131c1c-2fa0-470c-a7ae-58d6de600bff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774916153 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1774916153
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_genbits.2541181887
Short name T9
Test name
Test status
Simulation time 69323720 ps
CPU time 1.34 seconds
Started Aug 17 06:30:18 PM PDT 24
Finished Aug 17 06:30:19 PM PDT 24
Peak memory 217604 kb
Host smart-12ac7480-11b7-4614-a7f3-b1c09ed323b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541181887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2541181887
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4271830579
Short name T13
Test name
Test status
Simulation time 707596486 ps
CPU time 11.07 seconds
Started Aug 17 06:29:11 PM PDT 24
Finished Aug 17 06:29:23 PM PDT 24
Peak memory 237120 kb
Host smart-0f025f51-8f7c-40e7-adce-9259453cfbb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271830579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4271830579
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/80.edn_alert.603431748
Short name T28
Test name
Test status
Simulation time 45122018 ps
CPU time 1.29 seconds
Started Aug 17 06:30:44 PM PDT 24
Finished Aug 17 06:30:46 PM PDT 24
Peak memory 215756 kb
Host smart-3714d9ff-8227-4a68-8eef-82349982a17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603431748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_alert.603431748
Directory /workspace/80.edn_alert/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2942203329
Short name T12
Test name
Test status
Simulation time 107395580 ps
CPU time 1.16 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:27 PM PDT 24
Peak memory 218532 kb
Host smart-fcca44de-d99f-4e11-9012-3465054be890
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942203329 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2942203329
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/196.edn_alert.2521773020
Short name T46
Test name
Test status
Simulation time 107212348 ps
CPU time 1.11 seconds
Started Aug 17 06:30:55 PM PDT 24
Finished Aug 17 06:30:56 PM PDT 24
Peak memory 219208 kb
Host smart-934860c8-f2e9-4dc6-947b-197b35299786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521773020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_alert.2521773020
Directory /workspace/196.edn_alert/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1192364973
Short name T58
Test name
Test status
Simulation time 731392134 ps
CPU time 11.32 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:45 PM PDT 24
Peak memory 240264 kb
Host smart-aed4c168-dfc7-4240-911d-9b67aef5284b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192364973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1192364973
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/24.edn_stress_all.1819487633
Short name T24
Test name
Test status
Simulation time 1827674361 ps
CPU time 5.05 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:43 PM PDT 24
Peak memory 215392 kb
Host smart-357f250d-862d-4bac-b0c4-5a0e1812a826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819487633 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1819487633
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3905256565
Short name T210
Test name
Test status
Simulation time 3680748397 ps
CPU time 81.1 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:30:54 PM PDT 24
Peak memory 218200 kb
Host smart-62c0ce73-b06c-43ed-8536-586f23f6b8a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905256565 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3905256565
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.edn_alert.3317206929
Short name T100
Test name
Test status
Simulation time 29004026 ps
CPU time 1.23 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 218488 kb
Host smart-1d0995bb-e30d-4305-9ee8-df190243f7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317206929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_alert.3317206929
Directory /workspace/69.edn_alert/latest

Test location /workspace/coverage/default/73.edn_genbits.2959378519
Short name T65
Test name
Test status
Simulation time 32991279 ps
CPU time 1.21 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 218616 kb
Host smart-4155f5d1-909b-4f8c-91ba-051a65a10e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959378519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2959378519
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_disable.3390758826
Short name T22
Test name
Test status
Simulation time 29624753 ps
CPU time 0.89 seconds
Started Aug 17 06:30:13 PM PDT 24
Finished Aug 17 06:30:14 PM PDT 24
Peak memory 215408 kb
Host smart-6f48d496-31c1-4b91-a035-5ce69e8fc649
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390758826 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3390758826
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.542902362
Short name T75
Test name
Test status
Simulation time 188354330 ps
CPU time 1.22 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 216952 kb
Host smart-c597ea8a-24cb-4687-a11c-c73bcecb12f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542902362 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.542902362
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/99.edn_err.1337321878
Short name T25
Test name
Test status
Simulation time 90510725 ps
CPU time 1.23 seconds
Started Aug 17 06:31:17 PM PDT 24
Finished Aug 17 06:31:19 PM PDT 24
Peak memory 215484 kb
Host smart-8157f5a2-c7ca-4488-8ddc-7be54e10f13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337321878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1337321878
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/76.edn_alert.2783345520
Short name T29
Test name
Test status
Simulation time 25116303 ps
CPU time 1.27 seconds
Started Aug 17 06:30:32 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 219812 kb
Host smart-8e3bca16-07e6-4138-b1d5-d4d88f9f8bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783345520 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_alert.2783345520
Directory /workspace/76.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3026029774
Short name T283
Test name
Test status
Simulation time 72282570 ps
CPU time 1.53 seconds
Started Aug 17 06:26:31 PM PDT 24
Finished Aug 17 06:26:33 PM PDT 24
Peak memory 207060 kb
Host smart-67409844-3fe8-4071-a110-ec336a8d898a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026029774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3026029774
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/14.edn_disable.3573719631
Short name T189
Test name
Test status
Simulation time 47078172 ps
CPU time 0.87 seconds
Started Aug 17 06:29:44 PM PDT 24
Finished Aug 17 06:29:45 PM PDT 24
Peak memory 215428 kb
Host smart-67f5a0e3-56d5-4b79-ba4b-4d8b3759ecb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573719631 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3573719631
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable.2319055225
Short name T175
Test name
Test status
Simulation time 10610105 ps
CPU time 0.86 seconds
Started Aug 17 06:29:45 PM PDT 24
Finished Aug 17 06:29:46 PM PDT 24
Peak memory 215452 kb
Host smart-e51c55a4-57f1-41d8-a6d9-55506019823a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319055225 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2319055225
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/173.edn_alert.3932378756
Short name T148
Test name
Test status
Simulation time 29932322 ps
CPU time 1.33 seconds
Started Aug 17 06:31:03 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 218696 kb
Host smart-27368e32-353e-4d73-a793-9235a8222036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932378756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_alert.3932378756
Directory /workspace/173.edn_alert/latest

Test location /workspace/coverage/default/179.edn_genbits.172466661
Short name T42
Test name
Test status
Simulation time 50308084 ps
CPU time 1.6 seconds
Started Aug 17 06:31:16 PM PDT 24
Finished Aug 17 06:31:18 PM PDT 24
Peak memory 220032 kb
Host smart-2423ec1b-2f62-4719-a713-4e53e93361a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172466661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.172466661
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_alert.4075646039
Short name T81
Test name
Test status
Simulation time 26296870 ps
CPU time 1.24 seconds
Started Aug 17 06:30:55 PM PDT 24
Finished Aug 17 06:30:57 PM PDT 24
Peak memory 219640 kb
Host smart-cad0598a-1b90-429f-a863-03652e4dc943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075646039 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_alert.4075646039
Directory /workspace/143.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.2221607808
Short name T853
Test name
Test status
Simulation time 19269055 ps
CPU time 0.9 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:32 PM PDT 24
Peak memory 215416 kb
Host smart-d518fa81-4dd4-4dbe-bdea-f1fa1c047813
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221607808 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2221607808
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3712413125
Short name T113
Test name
Test status
Simulation time 45628005 ps
CPU time 1.4 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 217088 kb
Host smart-a6f85e60-a4e4-453b-beb6-9391b1c08948
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712413125 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3712413125
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2149688519
Short name T258
Test name
Test status
Simulation time 14005884 ps
CPU time 0.92 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:58 PM PDT 24
Peak memory 206976 kb
Host smart-23e1331e-b6bc-4513-99b3-b387fbf7cbe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149688519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2149688519
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/default/90.edn_alert.424918961
Short name T162
Test name
Test status
Simulation time 92597332 ps
CPU time 1.05 seconds
Started Aug 17 06:30:53 PM PDT 24
Finished Aug 17 06:30:54 PM PDT 24
Peak memory 218580 kb
Host smart-fa1ee578-d80c-4eec-8cb5-c4568f54839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424918961 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_alert.424918961
Directory /workspace/90.edn_alert/latest

Test location /workspace/coverage/default/115.edn_alert.3347554934
Short name T182
Test name
Test status
Simulation time 120258096 ps
CPU time 1.21 seconds
Started Aug 17 06:30:36 PM PDT 24
Finished Aug 17 06:30:39 PM PDT 24
Peak memory 219724 kb
Host smart-2dfd272e-5c4a-479b-9b38-49baad29e688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347554934 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_alert.3347554934
Directory /workspace/115.edn_alert/latest

Test location /workspace/coverage/default/193.edn_alert.1357038828
Short name T171
Test name
Test status
Simulation time 75927660 ps
CPU time 1.13 seconds
Started Aug 17 06:31:05 PM PDT 24
Finished Aug 17 06:31:06 PM PDT 24
Peak memory 219612 kb
Host smart-b75c0f1d-a334-4455-90cc-1a0655667feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357038828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_alert.1357038828
Directory /workspace/193.edn_alert/latest

Test location /workspace/coverage/default/129.edn_genbits.2724411837
Short name T280
Test name
Test status
Simulation time 537392878 ps
CPU time 5.34 seconds
Started Aug 17 06:30:49 PM PDT 24
Finished Aug 17 06:30:55 PM PDT 24
Peak memory 220712 kb
Host smart-78a2ef1a-7ee2-4290-9962-a1b46f1730ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724411837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2724411837
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_disable.4193924403
Short name T208
Test name
Test status
Simulation time 10905452 ps
CPU time 0.89 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 215408 kb
Host smart-041acdfa-fba9-4ace-a607-4b484f74e18f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193924403 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.4193924403
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/37.edn_alert.3289476954
Short name T247
Test name
Test status
Simulation time 107204515 ps
CPU time 1.33 seconds
Started Aug 17 06:30:09 PM PDT 24
Finished Aug 17 06:30:10 PM PDT 24
Peak memory 215760 kb
Host smart-a246fe81-74d9-40f1-893d-45ae66281fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289476954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3289476954
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/103.edn_alert.1869288586
Short name T71
Test name
Test status
Simulation time 24664127 ps
CPU time 1.17 seconds
Started Aug 17 06:31:12 PM PDT 24
Finished Aug 17 06:31:13 PM PDT 24
Peak memory 219636 kb
Host smart-e62b3497-3ba6-4c88-9003-87c8139ca40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869288586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_alert.1869288586
Directory /workspace/103.edn_alert/latest

Test location /workspace/coverage/default/135.edn_alert.4074123612
Short name T137
Test name
Test status
Simulation time 94416749 ps
CPU time 1.17 seconds
Started Aug 17 06:30:46 PM PDT 24
Finished Aug 17 06:30:47 PM PDT 24
Peak memory 215808 kb
Host smart-1269e768-9be7-4912-ab68-f4d9325b2181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074123612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_alert.4074123612
Directory /workspace/135.edn_alert/latest

Test location /workspace/coverage/default/245.edn_genbits.2292421408
Short name T239
Test name
Test status
Simulation time 38256825 ps
CPU time 1.15 seconds
Started Aug 17 06:31:20 PM PDT 24
Finished Aug 17 06:31:27 PM PDT 24
Peak memory 218560 kb
Host smart-019d4d4f-9ee2-486d-a14c-e959f92dfcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292421408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2292421408
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_alert.2187179497
Short name T123
Test name
Test status
Simulation time 42955634 ps
CPU time 1.23 seconds
Started Aug 17 06:31:05 PM PDT 24
Finished Aug 17 06:31:06 PM PDT 24
Peak memory 220404 kb
Host smart-f1e0fa53-f30d-4525-9380-f5a46cecbbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187179497 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_alert.2187179497
Directory /workspace/167.edn_alert/latest

Test location /workspace/coverage/default/23.edn_intr.1818194049
Short name T36
Test name
Test status
Simulation time 23025625 ps
CPU time 1.03 seconds
Started Aug 17 06:30:01 PM PDT 24
Finished Aug 17 06:30:02 PM PDT 24
Peak memory 215936 kb
Host smart-fc006c70-3821-4343-a442-34772357e5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818194049 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1818194049
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1323458976
Short name T132
Test name
Test status
Simulation time 23416996 ps
CPU time 1.02 seconds
Started Aug 17 06:29:12 PM PDT 24
Finished Aug 17 06:29:13 PM PDT 24
Peak memory 218748 kb
Host smart-ab2874b3-0a8d-42be-a260-1214ecb32664
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323458976 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1323458976
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3529462253
Short name T807
Test name
Test status
Simulation time 146763151 ps
CPU time 1.11 seconds
Started Aug 17 06:29:24 PM PDT 24
Finished Aug 17 06:29:25 PM PDT 24
Peak memory 217136 kb
Host smart-c570d25c-5651-4088-8a62-f26c3d3baf8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529462253 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3529462253
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/101.edn_alert.1960258259
Short name T833
Test name
Test status
Simulation time 90756096 ps
CPU time 1.23 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 215672 kb
Host smart-282e7fe0-4cc0-4222-ae3c-41871edb39d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960258259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_alert.1960258259
Directory /workspace/101.edn_alert/latest

Test location /workspace/coverage/default/111.edn_alert.473660690
Short name T115
Test name
Test status
Simulation time 44954833 ps
CPU time 1.2 seconds
Started Aug 17 06:31:02 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 218680 kb
Host smart-13383e0c-d96a-4100-b057-dcb55ba68dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473660690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_alert.473660690
Directory /workspace/111.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.357688334
Short name T145
Test name
Test status
Simulation time 44327039 ps
CPU time 1.12 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 216860 kb
Host smart-60e91c31-32b4-4b4c-9c45-3689c90a41b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357688334 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.357688334
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/158.edn_alert.2117500628
Short name T74
Test name
Test status
Simulation time 95139524 ps
CPU time 1.18 seconds
Started Aug 17 06:31:07 PM PDT 24
Finished Aug 17 06:31:08 PM PDT 24
Peak memory 215820 kb
Host smart-0e1bf737-3465-4b58-a3f2-ea1abbf978d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117500628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_alert.2117500628
Directory /workspace/158.edn_alert/latest

Test location /workspace/coverage/default/16.edn_disable.1643003111
Short name T160
Test name
Test status
Simulation time 35496604 ps
CPU time 0.85 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 215376 kb
Host smart-fa0ef76e-7d05-4edf-ad23-c1c6abb1d9bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643003111 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1643003111
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.4093088221
Short name T168
Test name
Test status
Simulation time 25241149 ps
CPU time 1.04 seconds
Started Aug 17 06:29:55 PM PDT 24
Finished Aug 17 06:29:56 PM PDT 24
Peak memory 224104 kb
Host smart-cacaa403-049e-40f9-928b-93a3976e30bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093088221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4093088221
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/49.edn_err.3756428063
Short name T180
Test name
Test status
Simulation time 24298397 ps
CPU time 0.9 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 218356 kb
Host smart-45b9ed63-84d5-479c-9ee9-8afc360e1d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756428063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3756428063
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/57.edn_err.3497633324
Short name T184
Test name
Test status
Simulation time 22577582 ps
CPU time 0.96 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 219484 kb
Host smart-9dd3af19-34b3-4eef-a5d1-f9000f2a7292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497633324 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3497633324
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/133.edn_genbits.1262944453
Short name T23
Test name
Test status
Simulation time 40125088 ps
CPU time 1.39 seconds
Started Aug 17 06:31:04 PM PDT 24
Finished Aug 17 06:31:05 PM PDT 24
Peak memory 218660 kb
Host smart-d1c6f1c5-2007-4ac4-a4d4-91c20b20d2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262944453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1262944453
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.687021810
Short name T335
Test name
Test status
Simulation time 20455425 ps
CPU time 1.06 seconds
Started Aug 17 06:29:15 PM PDT 24
Finished Aug 17 06:29:17 PM PDT 24
Peak memory 206888 kb
Host smart-7ff95eb0-ba58-453b-9d85-e53e9cb7f926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687021810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.687021810
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_stress_all.2495155114
Short name T631
Test name
Test status
Simulation time 424714640 ps
CPU time 3.81 seconds
Started Aug 17 06:29:20 PM PDT 24
Finished Aug 17 06:29:24 PM PDT 24
Peak memory 215408 kb
Host smart-85c6aa90-b33d-4cdc-a19a-ff2a8b319bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495155114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2495155114
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/102.edn_genbits.2867246588
Short name T316
Test name
Test status
Simulation time 158892083 ps
CPU time 3.25 seconds
Started Aug 17 06:30:47 PM PDT 24
Finished Aug 17 06:30:50 PM PDT 24
Peak memory 218640 kb
Host smart-6fae7694-5187-47a3-87ca-46ced0196d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867246588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2867246588
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.2040864557
Short name T312
Test name
Test status
Simulation time 229291427 ps
CPU time 1.24 seconds
Started Aug 17 06:30:55 PM PDT 24
Finished Aug 17 06:30:56 PM PDT 24
Peak memory 218108 kb
Host smart-89798234-8062-46fc-a587-21edd348e6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040864557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2040864557
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.444572546
Short name T34
Test name
Test status
Simulation time 49144342 ps
CPU time 0.83 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 215652 kb
Host smart-82739d16-2eb0-4fe4-b11b-bffde8065c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444572546 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.444572546
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3146922064
Short name T264
Test name
Test status
Simulation time 51376157 ps
CPU time 0.96 seconds
Started Aug 17 06:26:17 PM PDT 24
Finished Aug 17 06:26:18 PM PDT 24
Peak memory 207096 kb
Host smart-55bd85c0-7986-43c1-83b2-43a1581e8253
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146922064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3146922064
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3795378850
Short name T223
Test name
Test status
Simulation time 356829245 ps
CPU time 2.43 seconds
Started Aug 17 06:26:53 PM PDT 24
Finished Aug 17 06:26:55 PM PDT 24
Peak memory 207024 kb
Host smart-bb658380-9954-4eb8-8184-903fd1229bae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795378850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3795378850
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/107.edn_genbits.4166747897
Short name T225
Test name
Test status
Simulation time 118881967 ps
CPU time 1.53 seconds
Started Aug 17 06:30:58 PM PDT 24
Finished Aug 17 06:30:59 PM PDT 24
Peak memory 219124 kb
Host smart-c15ea911-001e-40c5-9c56-87bc42486f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166747897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.4166747897
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_genbits.2211086608
Short name T305
Test name
Test status
Simulation time 52732571 ps
CPU time 2.02 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 218524 kb
Host smart-6bcf78cd-a391-44ef-89a9-375351015adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211086608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2211086608
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3633440174
Short name T861
Test name
Test status
Simulation time 24210676 ps
CPU time 1.14 seconds
Started Aug 17 06:30:46 PM PDT 24
Finished Aug 17 06:30:47 PM PDT 24
Peak memory 215448 kb
Host smart-13fbb069-b146-45d7-9c05-0e7bb19e12d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633440174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3633440174
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1483354189
Short name T3
Test name
Test status
Simulation time 35839043 ps
CPU time 1.16 seconds
Started Aug 17 06:30:41 PM PDT 24
Finished Aug 17 06:30:42 PM PDT 24
Peak memory 220472 kb
Host smart-3620334c-216f-41c2-a36d-fa64cb2b754a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483354189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1483354189
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.948072756
Short name T296
Test name
Test status
Simulation time 101873408 ps
CPU time 1.47 seconds
Started Aug 17 06:30:59 PM PDT 24
Finished Aug 17 06:31:00 PM PDT 24
Peak memory 218708 kb
Host smart-cbfced51-bb83-47de-a89c-97ca750c2ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948072756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.948072756
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/170.edn_genbits.2440214690
Short name T297
Test name
Test status
Simulation time 81822322 ps
CPU time 2.89 seconds
Started Aug 17 06:30:55 PM PDT 24
Finished Aug 17 06:30:57 PM PDT 24
Peak memory 217780 kb
Host smart-42a4e5b1-2946-4b15-91ec-7fd4455deaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440214690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2440214690
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1454212893
Short name T313
Test name
Test status
Simulation time 81459162 ps
CPU time 1.11 seconds
Started Aug 17 06:31:10 PM PDT 24
Finished Aug 17 06:31:12 PM PDT 24
Peak memory 217472 kb
Host smart-e552b2cf-15be-4001-8b35-8d699bd6b014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454212893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1454212893
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1724981820
Short name T309
Test name
Test status
Simulation time 26099499 ps
CPU time 1.35 seconds
Started Aug 17 06:31:22 PM PDT 24
Finished Aug 17 06:31:24 PM PDT 24
Peak memory 218688 kb
Host smart-c1e7ff9f-bcd0-452b-abda-60ec171dfb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724981820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1724981820
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3946403733
Short name T37
Test name
Test status
Simulation time 23236958 ps
CPU time 0.9 seconds
Started Aug 17 06:30:21 PM PDT 24
Finished Aug 17 06:30:22 PM PDT 24
Peak memory 215836 kb
Host smart-3b7d2859-d359-4127-96b0-c72d98dff6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946403733 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3946403733
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/11.edn_intr.1212926456
Short name T107
Test name
Test status
Simulation time 32377696 ps
CPU time 0.9 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 215308 kb
Host smart-709c49bf-31aa-40e2-95f9-8b6297be17ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212926456 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1212926456
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/105.edn_alert.2483133458
Short name T971
Test name
Test status
Simulation time 23392450 ps
CPU time 1.17 seconds
Started Aug 17 06:30:32 PM PDT 24
Finished Aug 17 06:30:33 PM PDT 24
Peak memory 218656 kb
Host smart-d0233882-30b4-43b8-8294-0a3271efd69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483133458 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_alert.2483133458
Directory /workspace/105.edn_alert/latest

Test location /workspace/coverage/default/129.edn_alert.3752914303
Short name T205
Test name
Test status
Simulation time 44315197 ps
CPU time 1.23 seconds
Started Aug 17 06:30:36 PM PDT 24
Finished Aug 17 06:30:38 PM PDT 24
Peak memory 221216 kb
Host smart-009499be-ae8a-4edb-a4b6-1a9eb1a3fd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752914303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_alert.3752914303
Directory /workspace/129.edn_alert/latest

Test location /workspace/coverage/default/61.edn_alert.2277777798
Short name T102
Test name
Test status
Simulation time 86594160 ps
CPU time 1.22 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 218404 kb
Host smart-ff1b0f5b-19b3-4703-91e9-5053b68406e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277777798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_alert.2277777798
Directory /workspace/61.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2064415385
Short name T1026
Test name
Test status
Simulation time 64093469 ps
CPU time 1 seconds
Started Aug 17 06:26:38 PM PDT 24
Finished Aug 17 06:26:39 PM PDT 24
Peak memory 207064 kb
Host smart-88ba2f0e-8ebb-4599-9039-16b5b72306a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064415385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2064415385
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1476815026
Short name T1000
Test name
Test status
Simulation time 141473857 ps
CPU time 3.27 seconds
Started Aug 17 06:26:11 PM PDT 24
Finished Aug 17 06:26:14 PM PDT 24
Peak memory 206916 kb
Host smart-7a91015b-adc6-4407-a034-2435a0431d67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476815026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1476815026
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.659766059
Short name T1009
Test name
Test status
Simulation time 28477953 ps
CPU time 0.95 seconds
Started Aug 17 06:26:34 PM PDT 24
Finished Aug 17 06:26:35 PM PDT 24
Peak memory 206960 kb
Host smart-5a56a7e2-eab4-4f8a-87fd-6a89ed70ecd2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659766059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.659766059
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3699315465
Short name T1097
Test name
Test status
Simulation time 340819336 ps
CPU time 2.06 seconds
Started Aug 17 06:26:31 PM PDT 24
Finished Aug 17 06:26:33 PM PDT 24
Peak memory 215312 kb
Host smart-c962341c-0559-4d1d-b714-51f16e5e7002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699315465 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3699315465
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3544755670
Short name T257
Test name
Test status
Simulation time 24356422 ps
CPU time 0.91 seconds
Started Aug 17 06:26:29 PM PDT 24
Finished Aug 17 06:26:30 PM PDT 24
Peak memory 206992 kb
Host smart-ae70cf9d-d503-4108-b4e1-6fb31d4efecc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544755670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3544755670
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.253700296
Short name T989
Test name
Test status
Simulation time 35198114 ps
CPU time 0.86 seconds
Started Aug 17 06:26:40 PM PDT 24
Finished Aug 17 06:26:41 PM PDT 24
Peak memory 206852 kb
Host smart-a3e42610-256b-4c50-b721-8dd2ed45d079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253700296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.253700296
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.397633732
Short name T1104
Test name
Test status
Simulation time 35058594 ps
CPU time 1.39 seconds
Started Aug 17 06:26:21 PM PDT 24
Finished Aug 17 06:26:22 PM PDT 24
Peak memory 215288 kb
Host smart-ec1cde0a-cad1-4555-9428-6d2239c0209c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397633732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.397633732
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1299740473
Short name T1044
Test name
Test status
Simulation time 131790967 ps
CPU time 1.48 seconds
Started Aug 17 06:26:12 PM PDT 24
Finished Aug 17 06:26:13 PM PDT 24
Peak memory 206956 kb
Host smart-af066236-c700-4c5c-ab85-02352c143b68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299740473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1299740473
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.535445765
Short name T1045
Test name
Test status
Simulation time 66352709 ps
CPU time 3.41 seconds
Started Aug 17 06:26:34 PM PDT 24
Finished Aug 17 06:26:38 PM PDT 24
Peak memory 206952 kb
Host smart-d1e2c8a6-e2ce-4b06-a105-63f90c15621b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535445765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.535445765
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3433707401
Short name T983
Test name
Test status
Simulation time 26508650 ps
CPU time 0.91 seconds
Started Aug 17 06:26:33 PM PDT 24
Finished Aug 17 06:26:34 PM PDT 24
Peak memory 206988 kb
Host smart-c685019d-178f-408b-a8d7-f65030148be3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433707401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3433707401
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2261995477
Short name T1068
Test name
Test status
Simulation time 54364940 ps
CPU time 1.83 seconds
Started Aug 17 06:26:43 PM PDT 24
Finished Aug 17 06:26:45 PM PDT 24
Peak memory 215312 kb
Host smart-174a8fa6-0f26-4140-95f8-fd83d932ed5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261995477 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2261995477
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3218280639
Short name T1024
Test name
Test status
Simulation time 16263532 ps
CPU time 1 seconds
Started Aug 17 06:26:40 PM PDT 24
Finished Aug 17 06:26:41 PM PDT 24
Peak memory 206952 kb
Host smart-888ae27f-35aa-4340-9c31-6dab0d3e54d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218280639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3218280639
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3218046600
Short name T1098
Test name
Test status
Simulation time 75644644 ps
CPU time 0.91 seconds
Started Aug 17 06:26:38 PM PDT 24
Finished Aug 17 06:26:39 PM PDT 24
Peak memory 206904 kb
Host smart-a1f26386-50ef-45a8-b0a3-96448e15f93b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218046600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3218046600
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3517296442
Short name T269
Test name
Test status
Simulation time 126723169 ps
CPU time 1.41 seconds
Started Aug 17 06:26:32 PM PDT 24
Finished Aug 17 06:26:33 PM PDT 24
Peak memory 207036 kb
Host smart-bc1806e8-81dc-4509-828a-c98c974dcadc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517296442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3517296442
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.226537661
Short name T1025
Test name
Test status
Simulation time 71114187 ps
CPU time 2.54 seconds
Started Aug 17 06:26:30 PM PDT 24
Finished Aug 17 06:26:33 PM PDT 24
Peak memory 223436 kb
Host smart-135be178-fe85-448c-8b94-44f9637f3d47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226537661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.226537661
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3579219685
Short name T1054
Test name
Test status
Simulation time 135375479 ps
CPU time 2.14 seconds
Started Aug 17 06:26:33 PM PDT 24
Finished Aug 17 06:26:36 PM PDT 24
Peak memory 207116 kb
Host smart-a3ed90b9-668c-4b99-9313-99a6578e6a04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579219685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3579219685
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2633757782
Short name T1003
Test name
Test status
Simulation time 27845359 ps
CPU time 1.33 seconds
Started Aug 17 06:26:47 PM PDT 24
Finished Aug 17 06:26:49 PM PDT 24
Peak memory 218356 kb
Host smart-c22bbbf5-34db-42de-aed2-6f520bda43d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633757782 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2633757782
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.317894375
Short name T982
Test name
Test status
Simulation time 21641195 ps
CPU time 0.89 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:52 PM PDT 24
Peak memory 206928 kb
Host smart-e6b9862c-9aa4-45e0-9458-076ab29199b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317894375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.317894375
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2900367237
Short name T1042
Test name
Test status
Simulation time 38029274 ps
CPU time 0.8 seconds
Started Aug 17 06:26:53 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 206936 kb
Host smart-1016db7a-b2c2-4410-a26b-9efbb56199fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900367237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2900367237
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2101214766
Short name T268
Test name
Test status
Simulation time 46946800 ps
CPU time 1.26 seconds
Started Aug 17 06:26:46 PM PDT 24
Finished Aug 17 06:26:48 PM PDT 24
Peak memory 207064 kb
Host smart-77912a91-9fe6-423c-8521-b6df6cbcdace
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101214766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2101214766
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1900543046
Short name T1060
Test name
Test status
Simulation time 127185898 ps
CPU time 4.06 seconds
Started Aug 17 06:26:56 PM PDT 24
Finished Aug 17 06:27:01 PM PDT 24
Peak memory 215144 kb
Host smart-953439dc-7c6c-4da0-85dd-ec3c315b2ced
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900543046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1900543046
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1542441745
Short name T1043
Test name
Test status
Simulation time 386816887 ps
CPU time 1.98 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 207036 kb
Host smart-b89e62c0-3bcd-4cbf-8054-ada703018357
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542441745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1542441745
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1888043849
Short name T1013
Test name
Test status
Simulation time 62985013 ps
CPU time 1.08 seconds
Started Aug 17 06:26:47 PM PDT 24
Finished Aug 17 06:26:48 PM PDT 24
Peak memory 207060 kb
Host smart-61a9550e-fe10-41b5-a0fd-111147adb4ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888043849 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1888043849
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3808648731
Short name T1055
Test name
Test status
Simulation time 14454697 ps
CPU time 0.9 seconds
Started Aug 17 06:26:53 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 206964 kb
Host smart-91d73bc5-2c73-4d80-a36b-a9a8da71b2a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808648731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3808648731
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.516096898
Short name T1015
Test name
Test status
Simulation time 30414848 ps
CPU time 0.91 seconds
Started Aug 17 06:26:53 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 206868 kb
Host smart-51ea3546-ab85-436f-acb9-2e3879695ffc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516096898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.516096898
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1977435731
Short name T1081
Test name
Test status
Simulation time 74815648 ps
CPU time 0.89 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 207040 kb
Host smart-6d301a7e-8c09-426c-aa38-cb6f7887b43c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977435731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1977435731
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1663421945
Short name T992
Test name
Test status
Simulation time 250153542 ps
CPU time 2.62 seconds
Started Aug 17 06:26:48 PM PDT 24
Finished Aug 17 06:26:50 PM PDT 24
Peak memory 215236 kb
Host smart-1aa79066-f594-4764-a913-6cfe7e97dea2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663421945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1663421945
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2774029397
Short name T987
Test name
Test status
Simulation time 43311565 ps
CPU time 1.18 seconds
Started Aug 17 06:26:50 PM PDT 24
Finished Aug 17 06:26:51 PM PDT 24
Peak memory 215344 kb
Host smart-055564c1-eee6-4cac-b9c6-b394b16a3b3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774029397 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2774029397
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1342360476
Short name T991
Test name
Test status
Simulation time 14636370 ps
CPU time 0.89 seconds
Started Aug 17 06:26:42 PM PDT 24
Finished Aug 17 06:26:43 PM PDT 24
Peak memory 206936 kb
Host smart-24612948-cc4d-4795-a678-2fe1c87ac43e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342360476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1342360476
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1653466277
Short name T1065
Test name
Test status
Simulation time 63571709 ps
CPU time 0.95 seconds
Started Aug 17 06:26:50 PM PDT 24
Finished Aug 17 06:26:51 PM PDT 24
Peak memory 206936 kb
Host smart-f906a0c6-4ecc-49d6-baea-c6699d376abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653466277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1653466277
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1046178433
Short name T1020
Test name
Test status
Simulation time 37963112 ps
CPU time 0.97 seconds
Started Aug 17 06:26:43 PM PDT 24
Finished Aug 17 06:26:44 PM PDT 24
Peak memory 207104 kb
Host smart-bb335f1d-90f3-4930-bfc0-2ef06ae734ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046178433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1046178433
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1689339554
Short name T1073
Test name
Test status
Simulation time 50398019 ps
CPU time 2.16 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 215152 kb
Host smart-97e4dd46-b934-4c11-a992-bd0b7ee47b79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689339554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1689339554
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3114008909
Short name T1102
Test name
Test status
Simulation time 92400057 ps
CPU time 1.68 seconds
Started Aug 17 06:26:47 PM PDT 24
Finished Aug 17 06:26:49 PM PDT 24
Peak memory 215196 kb
Host smart-738af932-42b5-4e08-8e5c-96a48e4fc230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114008909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3114008909
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2692455919
Short name T1091
Test name
Test status
Simulation time 30478877 ps
CPU time 1.39 seconds
Started Aug 17 06:26:54 PM PDT 24
Finished Aug 17 06:27:00 PM PDT 24
Peak memory 215280 kb
Host smart-18675bb7-04ab-4a10-b9c0-ef9c4cb0c2f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692455919 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2692455919
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3324872611
Short name T235
Test name
Test status
Simulation time 30287534 ps
CPU time 0.95 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 206988 kb
Host smart-83a9b95d-2156-462c-ba58-15c48ab99398
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324872611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3324872611
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1059782870
Short name T1053
Test name
Test status
Simulation time 12086718 ps
CPU time 0.9 seconds
Started Aug 17 06:26:53 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 206912 kb
Host smart-c14c0a0a-6194-4763-97c8-75674f8bec8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059782870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1059782870
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.698344937
Short name T263
Test name
Test status
Simulation time 71240155 ps
CPU time 1.07 seconds
Started Aug 17 06:26:53 PM PDT 24
Finished Aug 17 06:26:55 PM PDT 24
Peak memory 206884 kb
Host smart-5dc67151-e917-4b7d-b330-6750edd813e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698344937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.698344937
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2499287365
Short name T1050
Test name
Test status
Simulation time 108293584 ps
CPU time 4.18 seconds
Started Aug 17 06:26:43 PM PDT 24
Finished Aug 17 06:26:47 PM PDT 24
Peak memory 215208 kb
Host smart-032cc943-1924-461d-b539-0b7dbe208985
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499287365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2499287365
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3204592586
Short name T1052
Test name
Test status
Simulation time 176212058 ps
CPU time 1.57 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 207112 kb
Host smart-20a62a09-5994-449b-889e-97d74d0e7881
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204592586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3204592586
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3871682017
Short name T1076
Test name
Test status
Simulation time 19127123 ps
CPU time 1.07 seconds
Started Aug 17 06:26:49 PM PDT 24
Finished Aug 17 06:26:51 PM PDT 24
Peak memory 215296 kb
Host smart-413d6df1-fd92-4984-ad78-969c60163f68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871682017 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3871682017
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3508564839
Short name T1103
Test name
Test status
Simulation time 29934988 ps
CPU time 0.77 seconds
Started Aug 17 06:26:54 PM PDT 24
Finished Aug 17 06:26:55 PM PDT 24
Peak memory 206712 kb
Host smart-6ba51ba5-79f2-4d50-bdca-ce95d82fe7f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508564839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3508564839
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1148134911
Short name T1089
Test name
Test status
Simulation time 34796002 ps
CPU time 1.41 seconds
Started Aug 17 06:26:54 PM PDT 24
Finished Aug 17 06:26:55 PM PDT 24
Peak memory 207060 kb
Host smart-1239c4be-f6d9-456c-9524-15b4af7d246b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148134911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1148134911
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.968457805
Short name T1022
Test name
Test status
Simulation time 36878926 ps
CPU time 2.17 seconds
Started Aug 17 06:26:57 PM PDT 24
Finished Aug 17 06:26:59 PM PDT 24
Peak memory 215176 kb
Host smart-51544c4d-03b3-46eb-bb19-bbc09e015478
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968457805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.968457805
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2668916586
Short name T284
Test name
Test status
Simulation time 94095778 ps
CPU time 2.57 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 207288 kb
Host smart-bee0bb7c-c18a-4f1d-9f93-f6cf3266c44e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668916586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2668916586
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.59261521
Short name T1021
Test name
Test status
Simulation time 21453841 ps
CPU time 1.45 seconds
Started Aug 17 06:26:55 PM PDT 24
Finished Aug 17 06:26:56 PM PDT 24
Peak memory 215308 kb
Host smart-85e85821-7b0a-49dc-a22d-f7a2e5c75628
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59261521 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.59261521
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2163638945
Short name T265
Test name
Test status
Simulation time 41432079 ps
CPU time 0.84 seconds
Started Aug 17 06:26:58 PM PDT 24
Finished Aug 17 06:26:59 PM PDT 24
Peak memory 206768 kb
Host smart-d46f2637-990f-4e04-be3f-0146cdc23194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163638945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2163638945
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2350069796
Short name T1059
Test name
Test status
Simulation time 27392683 ps
CPU time 0.87 seconds
Started Aug 17 06:26:50 PM PDT 24
Finished Aug 17 06:26:51 PM PDT 24
Peak memory 206892 kb
Host smart-8b222e02-b4e7-40db-a66f-3c32baecbd37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350069796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2350069796
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.496714270
Short name T1086
Test name
Test status
Simulation time 14681285 ps
CPU time 1.01 seconds
Started Aug 17 06:26:47 PM PDT 24
Finished Aug 17 06:26:48 PM PDT 24
Peak memory 207024 kb
Host smart-888c5d1b-a42e-4ac5-9b51-46d941f59ff6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496714270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.496714270
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.813013758
Short name T1071
Test name
Test status
Simulation time 61717875 ps
CPU time 1.45 seconds
Started Aug 17 06:26:45 PM PDT 24
Finished Aug 17 06:26:47 PM PDT 24
Peak memory 215176 kb
Host smart-9f354fed-421e-4e4b-87db-22d8431f4b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813013758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.813013758
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1844419589
Short name T1082
Test name
Test status
Simulation time 88810543 ps
CPU time 2.49 seconds
Started Aug 17 06:27:05 PM PDT 24
Finished Aug 17 06:27:07 PM PDT 24
Peak memory 215136 kb
Host smart-946a5eeb-128a-4782-92e5-d71201be9737
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844419589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1844419589
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1097174819
Short name T993
Test name
Test status
Simulation time 56276941 ps
CPU time 0.99 seconds
Started Aug 17 06:26:56 PM PDT 24
Finished Aug 17 06:26:57 PM PDT 24
Peak memory 207028 kb
Host smart-99eadd27-c19f-4d24-b679-cb731239ed5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097174819 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1097174819
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3501953564
Short name T251
Test name
Test status
Simulation time 24823819 ps
CPU time 0.93 seconds
Started Aug 17 06:26:45 PM PDT 24
Finished Aug 17 06:26:46 PM PDT 24
Peak memory 207016 kb
Host smart-4fbf9c86-215a-4ab6-8a88-852bc7f0b2fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501953564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3501953564
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1005714445
Short name T1088
Test name
Test status
Simulation time 15472863 ps
CPU time 0.86 seconds
Started Aug 17 06:26:53 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 206892 kb
Host smart-1d7b115c-17ec-4fe4-8a5f-ae122ba9e061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005714445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1005714445
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1143228348
Short name T1031
Test name
Test status
Simulation time 112805602 ps
CPU time 1.02 seconds
Started Aug 17 06:27:00 PM PDT 24
Finished Aug 17 06:27:01 PM PDT 24
Peak memory 207020 kb
Host smart-3d8524db-643f-4fa1-96f2-5478ac2c8919
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143228348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1143228348
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3087432280
Short name T1064
Test name
Test status
Simulation time 355529143 ps
CPU time 2.5 seconds
Started Aug 17 06:26:54 PM PDT 24
Finished Aug 17 06:26:57 PM PDT 24
Peak memory 215216 kb
Host smart-f237e007-8e9a-49bf-a590-4f1b34998476
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087432280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3087432280
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3164344352
Short name T1016
Test name
Test status
Simulation time 137156653 ps
CPU time 2.39 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 215256 kb
Host smart-23786faa-3fb6-4aa1-97e4-25bd0ebf8558
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164344352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3164344352
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2909803360
Short name T997
Test name
Test status
Simulation time 29676055 ps
CPU time 2.01 seconds
Started Aug 17 06:26:46 PM PDT 24
Finished Aug 17 06:26:48 PM PDT 24
Peak memory 215296 kb
Host smart-c5880323-0134-4d1c-8007-4ef22c00482e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909803360 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2909803360
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3405653393
Short name T267
Test name
Test status
Simulation time 30760580 ps
CPU time 0.85 seconds
Started Aug 17 06:26:49 PM PDT 24
Finished Aug 17 06:26:50 PM PDT 24
Peak memory 206804 kb
Host smart-d2a4a89c-78c6-4966-8424-66091f9c4381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405653393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3405653393
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2749056957
Short name T981
Test name
Test status
Simulation time 38047191 ps
CPU time 0.8 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 206884 kb
Host smart-0dc1f1e8-77bb-4e6f-b173-e14bbd2881af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749056957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2749056957
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3370504199
Short name T1029
Test name
Test status
Simulation time 176011921 ps
CPU time 1.36 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 207104 kb
Host smart-9bf985fb-45c4-4820-9542-a15cdaa17a42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370504199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3370504199
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3245753275
Short name T978
Test name
Test status
Simulation time 93767597 ps
CPU time 3.19 seconds
Started Aug 17 06:26:54 PM PDT 24
Finished Aug 17 06:26:57 PM PDT 24
Peak memory 215248 kb
Host smart-86663cf3-052f-4108-ad6a-ab9cd9a19e94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245753275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3245753275
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3736316985
Short name T1105
Test name
Test status
Simulation time 102905854 ps
CPU time 2.83 seconds
Started Aug 17 06:26:50 PM PDT 24
Finished Aug 17 06:26:52 PM PDT 24
Peak memory 215232 kb
Host smart-edd3920d-a347-4d56-84bf-672b7e367bc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736316985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3736316985
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1886685994
Short name T1067
Test name
Test status
Simulation time 26321634 ps
CPU time 1 seconds
Started Aug 17 06:26:47 PM PDT 24
Finished Aug 17 06:26:48 PM PDT 24
Peak memory 215200 kb
Host smart-0fb0ed68-143e-4352-b4ee-5d4f66f75182
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886685994 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1886685994
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1809553185
Short name T1101
Test name
Test status
Simulation time 41143350 ps
CPU time 0.9 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 206948 kb
Host smart-87b277e4-9e4e-4082-8a8a-15241aaac13b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809553185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1809553185
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2836661034
Short name T1047
Test name
Test status
Simulation time 36344757 ps
CPU time 0.79 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 206736 kb
Host smart-3eeb2256-0f79-46d4-82a1-1babe375ed8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836661034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2836661034
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3914252178
Short name T270
Test name
Test status
Simulation time 26789893 ps
CPU time 0.99 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 207072 kb
Host smart-a4158e90-5844-4029-8a9c-a4498d9b68d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914252178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3914252178
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1553827324
Short name T1092
Test name
Test status
Simulation time 39327055 ps
CPU time 2.76 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:55 PM PDT 24
Peak memory 215296 kb
Host smart-4d826038-194a-49e9-99d0-3560472f7c24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553827324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1553827324
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1739939653
Short name T1006
Test name
Test status
Simulation time 117313322 ps
CPU time 1.77 seconds
Started Aug 17 06:26:53 PM PDT 24
Finished Aug 17 06:26:55 PM PDT 24
Peak memory 207268 kb
Host smart-12dc47c4-400e-429e-a5a3-b9222446e45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739939653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1739939653
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3194814242
Short name T1033
Test name
Test status
Simulation time 87547090 ps
CPU time 1.46 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 215224 kb
Host smart-a8a1da1e-64bf-4cb3-b14b-9bda1229f89e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194814242 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3194814242
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2767195342
Short name T1106
Test name
Test status
Simulation time 103251678 ps
CPU time 0.9 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 206984 kb
Host smart-3fdc0d81-aeaf-4b1a-aaca-eb0b93b23767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767195342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2767195342
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2944191741
Short name T995
Test name
Test status
Simulation time 19000087 ps
CPU time 0.91 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 206920 kb
Host smart-6abb6464-6e68-4361-85b5-4a24f04b9672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944191741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2944191741
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1783085313
Short name T266
Test name
Test status
Simulation time 86591596 ps
CPU time 1.33 seconds
Started Aug 17 06:26:55 PM PDT 24
Finished Aug 17 06:26:56 PM PDT 24
Peak memory 207084 kb
Host smart-2f55cc8f-8584-4e11-b41f-ef7e99c3f489
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783085313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1783085313
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3991695757
Short name T1110
Test name
Test status
Simulation time 70751399 ps
CPU time 2.52 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 215288 kb
Host smart-bb4bc60d-d9e3-46df-9f8d-297f960ef62a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991695757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3991695757
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1214762962
Short name T1046
Test name
Test status
Simulation time 128086171 ps
CPU time 1.53 seconds
Started Aug 17 06:26:54 PM PDT 24
Finished Aug 17 06:26:56 PM PDT 24
Peak memory 215296 kb
Host smart-849eb05f-eb59-44b5-8d82-6e9844805646
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214762962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1214762962
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1156884414
Short name T262
Test name
Test status
Simulation time 71688699 ps
CPU time 1.55 seconds
Started Aug 17 06:26:46 PM PDT 24
Finished Aug 17 06:26:48 PM PDT 24
Peak memory 206984 kb
Host smart-46c85e28-a947-48c8-bc30-49e9b483fa54
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156884414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1156884414
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3565586554
Short name T1072
Test name
Test status
Simulation time 361655904 ps
CPU time 3 seconds
Started Aug 17 06:26:35 PM PDT 24
Finished Aug 17 06:26:38 PM PDT 24
Peak memory 206944 kb
Host smart-e5e22672-e563-449d-931b-1a0de96c87f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565586554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3565586554
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3248725501
Short name T1085
Test name
Test status
Simulation time 54841279 ps
CPU time 0.95 seconds
Started Aug 17 06:26:36 PM PDT 24
Finished Aug 17 06:26:37 PM PDT 24
Peak memory 206892 kb
Host smart-ebf3e5bc-f6b1-4b14-9ad1-d58fdfe6e5cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248725501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3248725501
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1115494787
Short name T986
Test name
Test status
Simulation time 202263811 ps
CPU time 1.25 seconds
Started Aug 17 06:26:37 PM PDT 24
Finished Aug 17 06:26:38 PM PDT 24
Peak memory 218448 kb
Host smart-44d096bb-100d-4d82-a8c9-866f097259c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115494787 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1115494787
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3646843526
Short name T1095
Test name
Test status
Simulation time 41246735 ps
CPU time 0.88 seconds
Started Aug 17 06:26:50 PM PDT 24
Finished Aug 17 06:26:51 PM PDT 24
Peak memory 206856 kb
Host smart-2a6195c5-b44b-48c8-ac1c-8026aba2cb15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646843526 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3646843526
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3249679268
Short name T1010
Test name
Test status
Simulation time 36555058 ps
CPU time 0.83 seconds
Started Aug 17 06:26:37 PM PDT 24
Finished Aug 17 06:26:38 PM PDT 24
Peak memory 206740 kb
Host smart-c174dbde-55d1-4656-a90e-5860fa884982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249679268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3249679268
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3589169410
Short name T1049
Test name
Test status
Simulation time 19980243 ps
CPU time 1.13 seconds
Started Aug 17 06:26:43 PM PDT 24
Finished Aug 17 06:26:45 PM PDT 24
Peak memory 207048 kb
Host smart-11c1faea-aa67-4a24-b7ac-122cb4e4f8e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589169410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3589169410
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1410563901
Short name T1078
Test name
Test status
Simulation time 76452651 ps
CPU time 1.71 seconds
Started Aug 17 06:26:13 PM PDT 24
Finished Aug 17 06:26:15 PM PDT 24
Peak memory 215324 kb
Host smart-ab31c566-a8f5-42d6-b9cc-96eb7849797f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410563901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1410563901
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4241270982
Short name T277
Test name
Test status
Simulation time 142291270 ps
CPU time 3.24 seconds
Started Aug 17 06:26:32 PM PDT 24
Finished Aug 17 06:26:36 PM PDT 24
Peak memory 207096 kb
Host smart-6130a6e8-1f06-469d-929f-171813d5b126
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241270982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4241270982
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.793788385
Short name T977
Test name
Test status
Simulation time 22449433 ps
CPU time 0.83 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 206932 kb
Host smart-8e75af4b-aa33-4a68-9320-4e332f80394f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793788385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.793788385
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2930658
Short name T1111
Test name
Test status
Simulation time 55273728 ps
CPU time 0.86 seconds
Started Aug 17 06:26:56 PM PDT 24
Finished Aug 17 06:26:57 PM PDT 24
Peak memory 206888 kb
Host smart-c5870eba-eef1-4b79-be54-525e602e6a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2930658
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1282109183
Short name T1100
Test name
Test status
Simulation time 14561941 ps
CPU time 0.97 seconds
Started Aug 17 06:26:48 PM PDT 24
Finished Aug 17 06:26:49 PM PDT 24
Peak memory 206924 kb
Host smart-7e91e3ea-c71c-4890-b656-c205591ceea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282109183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1282109183
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1225576355
Short name T1058
Test name
Test status
Simulation time 24881867 ps
CPU time 0.86 seconds
Started Aug 17 06:26:59 PM PDT 24
Finished Aug 17 06:27:05 PM PDT 24
Peak memory 206928 kb
Host smart-9dce3a10-668c-4008-85ae-bcb0fb4e06d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225576355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1225576355
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4125628044
Short name T1027
Test name
Test status
Simulation time 15184677 ps
CPU time 0.95 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:52 PM PDT 24
Peak memory 206828 kb
Host smart-9ccc8f25-8e77-4e88-a64f-c5c94548e817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125628044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4125628044
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3409840484
Short name T1018
Test name
Test status
Simulation time 60417155 ps
CPU time 0.85 seconds
Started Aug 17 06:27:01 PM PDT 24
Finished Aug 17 06:27:02 PM PDT 24
Peak memory 206756 kb
Host smart-3ccc03ca-ed7d-4cd3-960a-443ca64749ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409840484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3409840484
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1863011966
Short name T1080
Test name
Test status
Simulation time 17334557 ps
CPU time 0.8 seconds
Started Aug 17 06:27:03 PM PDT 24
Finished Aug 17 06:27:04 PM PDT 24
Peak memory 206868 kb
Host smart-e9dd3c6e-ab3c-4fd8-889d-cdec21275947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863011966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1863011966
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2982947876
Short name T1090
Test name
Test status
Simulation time 14507941 ps
CPU time 0.8 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 206756 kb
Host smart-4b012283-83c8-4816-88c6-ab5aa04208bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982947876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2982947876
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3876359352
Short name T1041
Test name
Test status
Simulation time 14091905 ps
CPU time 0.97 seconds
Started Aug 17 06:26:53 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 206812 kb
Host smart-dec61e5d-e310-4054-9b4b-d0f780877dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876359352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3876359352
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.640202017
Short name T1056
Test name
Test status
Simulation time 28913289 ps
CPU time 0.82 seconds
Started Aug 17 06:26:50 PM PDT 24
Finished Aug 17 06:26:51 PM PDT 24
Peak memory 206948 kb
Host smart-6e5e15aa-d43b-4a8a-91f5-3f2dea051ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640202017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.640202017
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1393438979
Short name T253
Test name
Test status
Simulation time 37703226 ps
CPU time 1.62 seconds
Started Aug 17 06:26:40 PM PDT 24
Finished Aug 17 06:26:42 PM PDT 24
Peak memory 206956 kb
Host smart-cdf08b47-a00e-4ed4-be20-3686b5d3d54e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393438979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1393438979
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.310503135
Short name T1002
Test name
Test status
Simulation time 471397322 ps
CPU time 6.11 seconds
Started Aug 17 06:26:36 PM PDT 24
Finished Aug 17 06:26:42 PM PDT 24
Peak memory 207004 kb
Host smart-68066c8e-1cad-42e4-8d54-c88a1652d364
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310503135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.310503135
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3424728951
Short name T990
Test name
Test status
Simulation time 17029063 ps
CPU time 0.94 seconds
Started Aug 17 06:26:41 PM PDT 24
Finished Aug 17 06:26:42 PM PDT 24
Peak memory 206920 kb
Host smart-26e61ad2-ad57-473d-806d-524e408932a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424728951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3424728951
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2015678628
Short name T1062
Test name
Test status
Simulation time 40496249 ps
CPU time 1.12 seconds
Started Aug 17 06:26:33 PM PDT 24
Finished Aug 17 06:26:35 PM PDT 24
Peak memory 215408 kb
Host smart-bd0a2330-9c81-400c-958d-503eaf5944cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015678628 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2015678628
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2246187681
Short name T1093
Test name
Test status
Simulation time 13424518 ps
CPU time 0.91 seconds
Started Aug 17 06:26:37 PM PDT 24
Finished Aug 17 06:26:38 PM PDT 24
Peak memory 206536 kb
Host smart-63b09010-58ca-4c45-a067-0daf7d56847f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246187681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2246187681
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1228062987
Short name T1014
Test name
Test status
Simulation time 16048130 ps
CPU time 0.89 seconds
Started Aug 17 06:26:49 PM PDT 24
Finished Aug 17 06:26:50 PM PDT 24
Peak memory 206900 kb
Host smart-29e25e8c-7847-466f-992d-6442d2a4c476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228062987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1228062987
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1284726092
Short name T1037
Test name
Test status
Simulation time 38781643 ps
CPU time 1.07 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 207108 kb
Host smart-d88bb1a2-6cf7-4b45-a904-7f06421b2f3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284726092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1284726092
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2650399235
Short name T1034
Test name
Test status
Simulation time 183704696 ps
CPU time 3.15 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 215324 kb
Host smart-ae8baf02-e6b4-4b1a-a366-034b5335843a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650399235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2650399235
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.690800895
Short name T1048
Test name
Test status
Simulation time 69362417 ps
CPU time 1.72 seconds
Started Aug 17 06:26:43 PM PDT 24
Finished Aug 17 06:26:45 PM PDT 24
Peak memory 207336 kb
Host smart-740a907c-4449-4bc1-81ea-ccac0fc73cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690800895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.690800895
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3815375721
Short name T1087
Test name
Test status
Simulation time 14432694 ps
CPU time 0.86 seconds
Started Aug 17 06:26:57 PM PDT 24
Finished Aug 17 06:26:58 PM PDT 24
Peak memory 206892 kb
Host smart-3f62518e-6067-4589-8fd9-65517500ac4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815375721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3815375721
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2344260928
Short name T984
Test name
Test status
Simulation time 20564661 ps
CPU time 0.82 seconds
Started Aug 17 06:27:03 PM PDT 24
Finished Aug 17 06:27:04 PM PDT 24
Peak memory 206868 kb
Host smart-bc60cb10-52f4-4ef2-bfcb-ee462270b02c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344260928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2344260928
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1271248219
Short name T1051
Test name
Test status
Simulation time 14664730 ps
CPU time 0.86 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 206928 kb
Host smart-3ab55068-7d59-4827-8caa-9fc1ac1a4370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271248219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1271248219
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.4116466385
Short name T998
Test name
Test status
Simulation time 11601753 ps
CPU time 0.81 seconds
Started Aug 17 06:26:59 PM PDT 24
Finished Aug 17 06:27:00 PM PDT 24
Peak memory 206880 kb
Host smart-b28fbe0a-f4ed-4d44-978e-3024b61b466f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116466385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.4116466385
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3729035010
Short name T999
Test name
Test status
Simulation time 19257321 ps
CPU time 0.83 seconds
Started Aug 17 06:26:55 PM PDT 24
Finished Aug 17 06:26:56 PM PDT 24
Peak memory 206816 kb
Host smart-9b4fdd77-47eb-44c3-a79b-9aa8d03bb593
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729035010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3729035010
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3224767514
Short name T1074
Test name
Test status
Simulation time 23386813 ps
CPU time 0.83 seconds
Started Aug 17 06:26:56 PM PDT 24
Finished Aug 17 06:26:57 PM PDT 24
Peak memory 206900 kb
Host smart-b50b5d27-23d9-4a1d-a395-89eb4dc01683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224767514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3224767514
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.400067283
Short name T979
Test name
Test status
Simulation time 25897214 ps
CPU time 0.85 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:57 PM PDT 24
Peak memory 206904 kb
Host smart-0b583da7-c986-4060-858d-31fcc03e4534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400067283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.400067283
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3681240575
Short name T976
Test name
Test status
Simulation time 19706583 ps
CPU time 0.8 seconds
Started Aug 17 06:26:59 PM PDT 24
Finished Aug 17 06:27:00 PM PDT 24
Peak memory 206884 kb
Host smart-6c5a68ab-717a-41a6-a78d-7980821986f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681240575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3681240575
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.3092988795
Short name T1007
Test name
Test status
Simulation time 15445332 ps
CPU time 0.88 seconds
Started Aug 17 06:26:59 PM PDT 24
Finished Aug 17 06:27:00 PM PDT 24
Peak memory 206904 kb
Host smart-0dc85871-e1dd-4ff1-b7de-c57a8890cc00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092988795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3092988795
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3656079612
Short name T1036
Test name
Test status
Simulation time 21448561 ps
CPU time 0.84 seconds
Started Aug 17 06:27:01 PM PDT 24
Finished Aug 17 06:27:07 PM PDT 24
Peak memory 206868 kb
Host smart-90542171-5bd4-470b-84a8-28ef69de70bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656079612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3656079612
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1065983533
Short name T261
Test name
Test status
Simulation time 14572917 ps
CPU time 0.98 seconds
Started Aug 17 06:26:37 PM PDT 24
Finished Aug 17 06:26:38 PM PDT 24
Peak memory 206732 kb
Host smart-55505810-6623-4256-8cb0-67c06966a1f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065983533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1065983533
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1207466271
Short name T1063
Test name
Test status
Simulation time 291690334 ps
CPU time 3.22 seconds
Started Aug 17 06:26:28 PM PDT 24
Finished Aug 17 06:26:36 PM PDT 24
Peak memory 207040 kb
Host smart-61e9f49f-3a49-445a-8365-d156645b5b65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207466271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1207466271
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2763110226
Short name T256
Test name
Test status
Simulation time 201431087 ps
CPU time 0.86 seconds
Started Aug 17 06:26:30 PM PDT 24
Finished Aug 17 06:26:31 PM PDT 24
Peak memory 206904 kb
Host smart-42d04f32-4b67-42de-bc51-e11453dc2a0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763110226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2763110226
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.475575978
Short name T980
Test name
Test status
Simulation time 30084963 ps
CPU time 1.44 seconds
Started Aug 17 06:26:35 PM PDT 24
Finished Aug 17 06:26:37 PM PDT 24
Peak memory 218356 kb
Host smart-848a08f6-8794-467f-9c0a-f955b320fe33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475575978 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.475575978
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.486135144
Short name T1004
Test name
Test status
Simulation time 32250629 ps
CPU time 0.91 seconds
Started Aug 17 06:26:46 PM PDT 24
Finished Aug 17 06:26:47 PM PDT 24
Peak memory 206968 kb
Host smart-7bff4c97-fe9e-4baf-aaef-e899b80d1020
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486135144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.486135144
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.130815888
Short name T1040
Test name
Test status
Simulation time 37886032 ps
CPU time 0.85 seconds
Started Aug 17 06:26:33 PM PDT 24
Finished Aug 17 06:26:34 PM PDT 24
Peak memory 206680 kb
Host smart-454e7bb1-bde4-47a2-b14c-5cf97587dd09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130815888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.130815888
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3312406671
Short name T250
Test name
Test status
Simulation time 26088526 ps
CPU time 1.28 seconds
Started Aug 17 06:26:38 PM PDT 24
Finished Aug 17 06:26:39 PM PDT 24
Peak memory 207048 kb
Host smart-7fd398ee-4932-4e0d-9d2f-f36fef1a7c56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312406671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3312406671
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3778002030
Short name T1008
Test name
Test status
Simulation time 141944766 ps
CPU time 2.73 seconds
Started Aug 17 06:26:33 PM PDT 24
Finished Aug 17 06:26:36 PM PDT 24
Peak memory 215216 kb
Host smart-9be487f2-689f-46e3-b5ba-f5a7ed5e5e25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778002030 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3778002030
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.944772530
Short name T1069
Test name
Test status
Simulation time 96883857 ps
CPU time 2.5 seconds
Started Aug 17 06:26:29 PM PDT 24
Finished Aug 17 06:26:32 PM PDT 24
Peak memory 207236 kb
Host smart-b2ed2704-8bac-45c9-aeb8-8a018741e7b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944772530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.944772530
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.4023348173
Short name T1070
Test name
Test status
Simulation time 12223634 ps
CPU time 0.86 seconds
Started Aug 17 06:26:55 PM PDT 24
Finished Aug 17 06:26:56 PM PDT 24
Peak memory 206896 kb
Host smart-d37c72e9-0a23-4365-852f-ac499351fe3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023348173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.4023348173
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.399259689
Short name T1084
Test name
Test status
Simulation time 11683612 ps
CPU time 0.86 seconds
Started Aug 17 06:26:53 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 206888 kb
Host smart-c8a2963f-5b97-4bdd-bb28-d51a984ccd03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399259689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.399259689
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3448887299
Short name T1012
Test name
Test status
Simulation time 55329249 ps
CPU time 0.92 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 206828 kb
Host smart-0fe93049-3464-4a12-b1b3-3164f2f1a1ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448887299 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3448887299
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1420374932
Short name T1061
Test name
Test status
Simulation time 48171013 ps
CPU time 0.84 seconds
Started Aug 17 06:26:54 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 206828 kb
Host smart-41323ea0-e80a-4201-8900-23f5d267aa36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420374932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1420374932
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2256384565
Short name T1057
Test name
Test status
Simulation time 35897156 ps
CPU time 0.86 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 206820 kb
Host smart-cf3c26ef-b17a-4226-a236-6f55acf8894b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256384565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2256384565
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.4064432110
Short name T1108
Test name
Test status
Simulation time 13867248 ps
CPU time 0.89 seconds
Started Aug 17 06:26:59 PM PDT 24
Finished Aug 17 06:27:00 PM PDT 24
Peak memory 206924 kb
Host smart-3416f428-d239-4032-8389-7b0c383421d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064432110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.4064432110
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.766019409
Short name T1017
Test name
Test status
Simulation time 36868855 ps
CPU time 0.78 seconds
Started Aug 17 06:26:56 PM PDT 24
Finished Aug 17 06:26:57 PM PDT 24
Peak memory 206748 kb
Host smart-0e60a1ae-a5c2-4461-b92f-ebc650a2c68e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766019409 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.766019409
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1159401987
Short name T988
Test name
Test status
Simulation time 45144028 ps
CPU time 0.84 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:52 PM PDT 24
Peak memory 206920 kb
Host smart-1afa74eb-6896-486e-ae44-14d95ce3230d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159401987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1159401987
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4104079944
Short name T1032
Test name
Test status
Simulation time 34660117 ps
CPU time 0.81 seconds
Started Aug 17 06:26:55 PM PDT 24
Finished Aug 17 06:26:56 PM PDT 24
Peak memory 206752 kb
Host smart-a7fa8cae-229e-4678-ad96-0e5a9fc91960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104079944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4104079944
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2674073849
Short name T1083
Test name
Test status
Simulation time 50497559 ps
CPU time 0.87 seconds
Started Aug 17 06:26:52 PM PDT 24
Finished Aug 17 06:26:54 PM PDT 24
Peak memory 206836 kb
Host smart-2a4cef77-977b-4bf5-8df8-9f3bde3dcb76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674073849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2674073849
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4095907314
Short name T1001
Test name
Test status
Simulation time 31375107 ps
CPU time 1.51 seconds
Started Aug 17 06:26:44 PM PDT 24
Finished Aug 17 06:26:46 PM PDT 24
Peak memory 215368 kb
Host smart-a968712b-a7ec-4d8a-b14c-cfd90e4e3fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095907314 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.4095907314
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2848885933
Short name T254
Test name
Test status
Simulation time 17531010 ps
CPU time 0.98 seconds
Started Aug 17 06:26:44 PM PDT 24
Finished Aug 17 06:26:45 PM PDT 24
Peak memory 206988 kb
Host smart-7a660195-34f5-4e60-be7e-4981d6681c7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848885933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2848885933
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1418373095
Short name T985
Test name
Test status
Simulation time 26338325 ps
CPU time 0.81 seconds
Started Aug 17 06:27:00 PM PDT 24
Finished Aug 17 06:27:01 PM PDT 24
Peak memory 206724 kb
Host smart-7d6ce266-64b8-477d-85c1-cd7f18cfeeba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418373095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1418373095
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1290716941
Short name T1077
Test name
Test status
Simulation time 115304277 ps
CPU time 1.13 seconds
Started Aug 17 06:26:46 PM PDT 24
Finished Aug 17 06:26:47 PM PDT 24
Peak memory 207100 kb
Host smart-0fca27c9-57cc-4269-bbf5-be3904232198
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290716941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1290716941
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2220595730
Short name T220
Test name
Test status
Simulation time 150992929 ps
CPU time 4.88 seconds
Started Aug 17 06:26:48 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 215244 kb
Host smart-81682fac-fc1f-4b08-86e8-c6ff413c668a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220595730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2220595730
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2846966093
Short name T1023
Test name
Test status
Simulation time 173858823 ps
CPU time 2.14 seconds
Started Aug 17 06:26:55 PM PDT 24
Finished Aug 17 06:26:57 PM PDT 24
Peak memory 215712 kb
Host smart-2d0e5ee8-579a-40e9-a68d-65a3d6917e09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846966093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2846966093
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.274847141
Short name T1107
Test name
Test status
Simulation time 425372641 ps
CPU time 1.32 seconds
Started Aug 17 06:26:47 PM PDT 24
Finished Aug 17 06:26:49 PM PDT 24
Peak memory 215352 kb
Host smart-6b63b3d6-20f5-40cc-a603-4ec3161dc936
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274847141 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.274847141
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3397105211
Short name T255
Test name
Test status
Simulation time 24673356 ps
CPU time 0.89 seconds
Started Aug 17 06:26:45 PM PDT 24
Finished Aug 17 06:26:46 PM PDT 24
Peak memory 206800 kb
Host smart-9eaf8c16-9c23-44d6-baa8-a4d7041ee6b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397105211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3397105211
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3953879605
Short name T1079
Test name
Test status
Simulation time 24148196 ps
CPU time 0.91 seconds
Started Aug 17 06:26:44 PM PDT 24
Finished Aug 17 06:26:45 PM PDT 24
Peak memory 206912 kb
Host smart-e926a801-0001-4869-bd2b-4bc6f9b252ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953879605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3953879605
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4268998619
Short name T1039
Test name
Test status
Simulation time 18475239 ps
CPU time 1.15 seconds
Started Aug 17 06:26:45 PM PDT 24
Finished Aug 17 06:26:46 PM PDT 24
Peak memory 207068 kb
Host smart-4403f727-08bb-4969-84e1-3229ef9138c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268998619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.4268998619
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2916283105
Short name T1011
Test name
Test status
Simulation time 220503636 ps
CPU time 4 seconds
Started Aug 17 06:26:45 PM PDT 24
Finished Aug 17 06:26:49 PM PDT 24
Peak memory 215252 kb
Host smart-6bb77139-c8d2-45f9-a4f1-457aaaddd689
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916283105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2916283105
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2969910534
Short name T282
Test name
Test status
Simulation time 215944277 ps
CPU time 1.52 seconds
Started Aug 17 06:26:38 PM PDT 24
Finished Aug 17 06:26:40 PM PDT 24
Peak memory 207120 kb
Host smart-16fb507c-585d-47a8-b59f-bb8e5965d87e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969910534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2969910534
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2929062948
Short name T1038
Test name
Test status
Simulation time 97380300 ps
CPU time 1.3 seconds
Started Aug 17 06:26:35 PM PDT 24
Finished Aug 17 06:26:37 PM PDT 24
Peak memory 218080 kb
Host smart-1c09adf0-4a66-4caf-9547-c56b3c80a8ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929062948 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2929062948
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.407004079
Short name T260
Test name
Test status
Simulation time 11943157 ps
CPU time 0.87 seconds
Started Aug 17 06:26:40 PM PDT 24
Finished Aug 17 06:26:41 PM PDT 24
Peak memory 206928 kb
Host smart-4eaea507-bb4c-4eda-949c-0126f7ef1c59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407004079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.407004079
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1449270771
Short name T1099
Test name
Test status
Simulation time 44797768 ps
CPU time 0.79 seconds
Started Aug 17 06:26:43 PM PDT 24
Finished Aug 17 06:26:43 PM PDT 24
Peak memory 206744 kb
Host smart-d00a1230-d668-4904-ac89-5a99d1481e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449270771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1449270771
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1936720790
Short name T1030
Test name
Test status
Simulation time 19812780 ps
CPU time 1.22 seconds
Started Aug 17 06:26:47 PM PDT 24
Finished Aug 17 06:26:48 PM PDT 24
Peak memory 207084 kb
Host smart-1748a38d-6e70-4611-9f5c-16ab48f402b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936720790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1936720790
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3178259781
Short name T1035
Test name
Test status
Simulation time 76206696 ps
CPU time 1.92 seconds
Started Aug 17 06:26:40 PM PDT 24
Finished Aug 17 06:26:42 PM PDT 24
Peak memory 215208 kb
Host smart-3994790f-df1a-490c-b92d-b9c408c675e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178259781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3178259781
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.871063935
Short name T278
Test name
Test status
Simulation time 47367250 ps
CPU time 1.6 seconds
Started Aug 17 06:26:50 PM PDT 24
Finished Aug 17 06:26:52 PM PDT 24
Peak memory 207096 kb
Host smart-7095f1f7-6fc6-482c-be83-28289ed9f2cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871063935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.871063935
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3258810893
Short name T996
Test name
Test status
Simulation time 23819575 ps
CPU time 1.3 seconds
Started Aug 17 06:26:35 PM PDT 24
Finished Aug 17 06:26:36 PM PDT 24
Peak memory 215344 kb
Host smart-e1e8af5d-239b-422d-8514-58d41fab4cf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258810893 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3258810893
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1474529051
Short name T252
Test name
Test status
Simulation time 13445338 ps
CPU time 0.9 seconds
Started Aug 17 06:26:38 PM PDT 24
Finished Aug 17 06:26:38 PM PDT 24
Peak memory 206980 kb
Host smart-3569d461-775a-4005-a883-cf2deed6efbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474529051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1474529051
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.906520417
Short name T994
Test name
Test status
Simulation time 21836563 ps
CPU time 0.81 seconds
Started Aug 17 06:26:46 PM PDT 24
Finished Aug 17 06:26:47 PM PDT 24
Peak memory 206704 kb
Host smart-f10bbf31-2689-4865-8417-38ad727e5d83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906520417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.906520417
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2828815151
Short name T1075
Test name
Test status
Simulation time 21798791 ps
CPU time 1.09 seconds
Started Aug 17 06:26:49 PM PDT 24
Finished Aug 17 06:26:50 PM PDT 24
Peak memory 207012 kb
Host smart-65f2dac1-e598-47bc-a933-40586b0baa65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828815151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2828815151
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2612939500
Short name T1005
Test name
Test status
Simulation time 125433649 ps
CPU time 4.4 seconds
Started Aug 17 06:26:48 PM PDT 24
Finished Aug 17 06:26:52 PM PDT 24
Peak memory 215288 kb
Host smart-24fc2bb3-814d-446c-9224-b2f0fae4ac95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612939500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2612939500
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4065852006
Short name T1094
Test name
Test status
Simulation time 62231226 ps
CPU time 1.87 seconds
Started Aug 17 06:26:42 PM PDT 24
Finished Aug 17 06:26:44 PM PDT 24
Peak memory 207432 kb
Host smart-4cc2b67f-4129-4b98-8325-46ea3bc9f307
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065852006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4065852006
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.716757784
Short name T1066
Test name
Test status
Simulation time 56328882 ps
CPU time 1.24 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 217500 kb
Host smart-25c15ed8-2b04-49e6-a113-b7e550c2fb0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716757784 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.716757784
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.824123891
Short name T259
Test name
Test status
Simulation time 46853809 ps
CPU time 0.81 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:52 PM PDT 24
Peak memory 206736 kb
Host smart-81b3f567-dfff-428f-bdd8-2a0ff03efc5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824123891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.824123891
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3636252163
Short name T1109
Test name
Test status
Simulation time 59436348 ps
CPU time 0.84 seconds
Started Aug 17 06:26:49 PM PDT 24
Finished Aug 17 06:26:50 PM PDT 24
Peak memory 206928 kb
Host smart-e2e40a8d-7975-48cd-8208-ce835dae3e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636252163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3636252163
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1853931516
Short name T1019
Test name
Test status
Simulation time 38345329 ps
CPU time 1.39 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 207112 kb
Host smart-fc567b26-6c3f-46b7-b38e-16e15b929cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853931516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1853931516
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3010235357
Short name T1096
Test name
Test status
Simulation time 69985825 ps
CPU time 1.28 seconds
Started Aug 17 06:26:51 PM PDT 24
Finished Aug 17 06:26:53 PM PDT 24
Peak memory 215256 kb
Host smart-e15eaf7c-de29-4f59-b22f-5932eb2ae417
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010235357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3010235357
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3259469655
Short name T1028
Test name
Test status
Simulation time 87772043 ps
CPU time 2.46 seconds
Started Aug 17 06:26:54 PM PDT 24
Finished Aug 17 06:26:57 PM PDT 24
Peak memory 207020 kb
Host smart-b5c7eaa5-58a8-4e49-a766-3c0e2f2d50fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259469655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3259469655
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2890365697
Short name T276
Test name
Test status
Simulation time 26278610 ps
CPU time 1.17 seconds
Started Aug 17 06:29:28 PM PDT 24
Finished Aug 17 06:29:30 PM PDT 24
Peak memory 220796 kb
Host smart-f5888bfb-46b3-43ba-8772-b1187fbfd3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890365697 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2890365697
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.686716994
Short name T775
Test name
Test status
Simulation time 73365254 ps
CPU time 0.83 seconds
Started Aug 17 06:29:16 PM PDT 24
Finished Aug 17 06:29:17 PM PDT 24
Peak memory 215368 kb
Host smart-5395bb32-760f-4eeb-9867-b03a014e9e82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686716994 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.686716994
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.1959983088
Short name T136
Test name
Test status
Simulation time 19788122 ps
CPU time 1.23 seconds
Started Aug 17 06:29:26 PM PDT 24
Finished Aug 17 06:29:28 PM PDT 24
Peak memory 224024 kb
Host smart-960c192c-d1ce-49dc-97a0-bef92d0c94c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959983088 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1959983088
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.280620739
Short name T303
Test name
Test status
Simulation time 51824980 ps
CPU time 1.22 seconds
Started Aug 17 06:29:30 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 219592 kb
Host smart-525d5c4a-f8c6-4d74-8d65-07a61c1b345b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280620739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.280620739
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.775041603
Short name T31
Test name
Test status
Simulation time 20653951 ps
CPU time 1.1 seconds
Started Aug 17 06:29:20 PM PDT 24
Finished Aug 17 06:29:21 PM PDT 24
Peak memory 215776 kb
Host smart-c0015b19-276d-4be1-8265-74c33f21f3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775041603 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.775041603
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2301785259
Short name T927
Test name
Test status
Simulation time 172247455 ps
CPU time 0.87 seconds
Started Aug 17 06:29:30 PM PDT 24
Finished Aug 17 06:29:31 PM PDT 24
Peak memory 207180 kb
Host smart-b58a1d30-9de9-47e3-842a-6f58e73526d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301785259 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2301785259
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.2262921232
Short name T696
Test name
Test status
Simulation time 42737262 ps
CPU time 0.9 seconds
Started Aug 17 06:29:01 PM PDT 24
Finished Aug 17 06:29:02 PM PDT 24
Peak memory 215328 kb
Host smart-82ec87f5-bc19-42eb-944d-95cad3ae1a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262921232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2262921232
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_alert.1327254503
Short name T828
Test name
Test status
Simulation time 339916550 ps
CPU time 1.54 seconds
Started Aug 17 06:29:15 PM PDT 24
Finished Aug 17 06:29:16 PM PDT 24
Peak memory 219652 kb
Host smart-59159fee-6700-4195-b329-297f7bf7aea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327254503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1327254503
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1040219002
Short name T587
Test name
Test status
Simulation time 162188960 ps
CPU time 0.95 seconds
Started Aug 17 06:29:27 PM PDT 24
Finished Aug 17 06:29:28 PM PDT 24
Peak memory 206880 kb
Host smart-6863d40e-87cd-4925-8c68-5626f9f9c461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040219002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1040219002
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3620315105
Short name T176
Test name
Test status
Simulation time 95086710 ps
CPU time 0.87 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:32 PM PDT 24
Peak memory 215364 kb
Host smart-e288f890-4645-44e7-9a1e-f44c86afc517
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620315105 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3620315105
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2454736455
Short name T818
Test name
Test status
Simulation time 123070365 ps
CPU time 1.04 seconds
Started Aug 17 06:29:15 PM PDT 24
Finished Aug 17 06:29:16 PM PDT 24
Peak memory 218556 kb
Host smart-d6f15302-da87-45ef-aeea-aa984f813620
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454736455 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2454736455
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.530231421
Short name T108
Test name
Test status
Simulation time 34864681 ps
CPU time 1.03 seconds
Started Aug 17 06:29:12 PM PDT 24
Finished Aug 17 06:29:13 PM PDT 24
Peak memory 220528 kb
Host smart-dd859f30-d0af-4132-8e84-58dbc6f9d56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530231421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.530231421
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3761834572
Short name T96
Test name
Test status
Simulation time 73249580 ps
CPU time 1.13 seconds
Started Aug 17 06:29:10 PM PDT 24
Finished Aug 17 06:29:11 PM PDT 24
Peak memory 217544 kb
Host smart-d4c843b0-9c5e-401f-841a-fa2be600d2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761834572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3761834572
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.1242310522
Short name T813
Test name
Test status
Simulation time 20383842 ps
CPU time 1.05 seconds
Started Aug 17 06:29:23 PM PDT 24
Finished Aug 17 06:29:24 PM PDT 24
Peak memory 207124 kb
Host smart-758e5ce5-5ed1-4eb3-9c35-32f3e4d232a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242310522 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1242310522
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.134228483
Short name T57
Test name
Test status
Simulation time 488506210 ps
CPU time 4.26 seconds
Started Aug 17 06:29:30 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 235236 kb
Host smart-c65a5273-d8f8-4926-8170-9e1360f1fac7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134228483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.134228483
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1093188411
Short name T352
Test name
Test status
Simulation time 44913752 ps
CPU time 0.89 seconds
Started Aug 17 06:29:17 PM PDT 24
Finished Aug 17 06:29:18 PM PDT 24
Peak memory 215364 kb
Host smart-c11b8cd3-f877-4fa1-9e15-2cec9ede324c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093188411 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1093188411
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1933947934
Short name T776
Test name
Test status
Simulation time 142944945 ps
CPU time 2.1 seconds
Started Aug 17 06:29:23 PM PDT 24
Finished Aug 17 06:29:30 PM PDT 24
Peak memory 220152 kb
Host smart-6ed2a6b7-260a-4aad-8185-3d4daca445eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933947934 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1933947934
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.735712494
Short name T575
Test name
Test status
Simulation time 37336301 ps
CPU time 1.26 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 219508 kb
Host smart-035a1c4f-0a45-4a0f-8169-368a8c476f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735712494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.735712494
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.243644670
Short name T946
Test name
Test status
Simulation time 130295346 ps
CPU time 0.96 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 206720 kb
Host smart-5b4af450-43d3-478c-9e8c-c4e1bb402a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243644670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.243644670
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.387729317
Short name T810
Test name
Test status
Simulation time 22707712 ps
CPU time 0.86 seconds
Started Aug 17 06:29:36 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 218120 kb
Host smart-5e691751-7c33-454a-a1a9-c6fc2b2e440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387729317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.387729317
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2082907276
Short name T653
Test name
Test status
Simulation time 45749840 ps
CPU time 1.49 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 217212 kb
Host smart-76316603-0c36-4bc9-9c21-5bca1d22286a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082907276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2082907276
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3435346856
Short name T87
Test name
Test status
Simulation time 24872904 ps
CPU time 1 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 215856 kb
Host smart-4aff6633-3eab-4b24-a626-7917c52e7108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435346856 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3435346856
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1849416613
Short name T364
Test name
Test status
Simulation time 44331826 ps
CPU time 0.9 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 215320 kb
Host smart-dfc6b9a4-96de-4c2f-ba13-fa7637c848f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849416613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1849416613
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.145475166
Short name T233
Test name
Test status
Simulation time 385569940 ps
CPU time 7.07 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 217248 kb
Host smart-af7786e4-aec5-4289-98d3-793f88eca722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145475166 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.145475166
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_alert.189422571
Short name T574
Test name
Test status
Simulation time 44968390 ps
CPU time 1.11 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 220840 kb
Host smart-a77a09b7-aee8-4519-9fd1-279a9912309e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189422571 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_alert.189422571
Directory /workspace/100.edn_alert/latest

Test location /workspace/coverage/default/100.edn_genbits.2196962493
Short name T936
Test name
Test status
Simulation time 96744610 ps
CPU time 1.37 seconds
Started Aug 17 06:30:35 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 218736 kb
Host smart-37cd7504-db56-4f4a-816c-35ad8204fb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196962493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2196962493
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.928385809
Short name T670
Test name
Test status
Simulation time 153719601 ps
CPU time 1.61 seconds
Started Aug 17 06:30:59 PM PDT 24
Finished Aug 17 06:31:00 PM PDT 24
Peak memory 218728 kb
Host smart-e6f1ed25-c4ba-4582-b468-40542c4a6dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928385809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.928385809
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_alert.105519403
Short name T752
Test name
Test status
Simulation time 43458276 ps
CPU time 1.1 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 219952 kb
Host smart-889d7f36-bced-45ec-b21c-9e71c05f3d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105519403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_alert.105519403
Directory /workspace/102.edn_alert/latest

Test location /workspace/coverage/default/103.edn_genbits.2557569761
Short name T454
Test name
Test status
Simulation time 60738595 ps
CPU time 1.14 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 218980 kb
Host smart-ab879351-c87d-43ad-9dcd-6615e2ee8342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557569761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2557569761
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_alert.1755611222
Short name T512
Test name
Test status
Simulation time 35176207 ps
CPU time 1.21 seconds
Started Aug 17 06:30:54 PM PDT 24
Finished Aug 17 06:30:55 PM PDT 24
Peak memory 219484 kb
Host smart-63bb1a8d-17a0-4743-a2b1-29d3d1d31bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755611222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_alert.1755611222
Directory /workspace/104.edn_alert/latest

Test location /workspace/coverage/default/104.edn_genbits.2381471617
Short name T447
Test name
Test status
Simulation time 72161743 ps
CPU time 1.02 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 217280 kb
Host smart-5ca529dc-3579-454d-bdb0-326180545b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381471617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2381471617
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1620871856
Short name T422
Test name
Test status
Simulation time 68296156 ps
CPU time 1.1 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 217580 kb
Host smart-5c938945-f0a7-4fa8-9d57-0d556989540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620871856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1620871856
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_alert.2878170557
Short name T545
Test name
Test status
Simulation time 23434320 ps
CPU time 1.21 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 218740 kb
Host smart-1e809767-780a-4f3f-aae5-dc35706fac0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878170557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_alert.2878170557
Directory /workspace/106.edn_alert/latest

Test location /workspace/coverage/default/106.edn_genbits.2449390931
Short name T569
Test name
Test status
Simulation time 52005508 ps
CPU time 1.64 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:35 PM PDT 24
Peak memory 218436 kb
Host smart-f6dc8466-beed-4dfb-9523-135bb375ec4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449390931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2449390931
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_alert.517163668
Short name T93
Test name
Test status
Simulation time 82644029 ps
CPU time 1.23 seconds
Started Aug 17 06:31:10 PM PDT 24
Finished Aug 17 06:31:11 PM PDT 24
Peak memory 218940 kb
Host smart-4f4fcf13-243a-4093-b63b-131804317ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517163668 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_alert.517163668
Directory /workspace/107.edn_alert/latest

Test location /workspace/coverage/default/108.edn_alert.355283932
Short name T238
Test name
Test status
Simulation time 35496695 ps
CPU time 1.21 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 218588 kb
Host smart-b2b01a75-d353-44be-872c-f7a753ce1450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355283932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_alert.355283932
Directory /workspace/108.edn_alert/latest

Test location /workspace/coverage/default/108.edn_genbits.1654508078
Short name T403
Test name
Test status
Simulation time 27481817 ps
CPU time 1.28 seconds
Started Aug 17 06:30:39 PM PDT 24
Finished Aug 17 06:30:40 PM PDT 24
Peak memory 217736 kb
Host smart-ca3dcc22-f042-4c26-b270-425b7fe0edea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654508078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1654508078
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_alert.602217117
Short name T242
Test name
Test status
Simulation time 48096660 ps
CPU time 1.16 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 219804 kb
Host smart-9546d17d-48fb-4ec1-90a8-cdea68b43862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602217117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_alert.602217117
Directory /workspace/109.edn_alert/latest

Test location /workspace/coverage/default/109.edn_genbits.4252155300
Short name T778
Test name
Test status
Simulation time 117003087 ps
CPU time 1.68 seconds
Started Aug 17 06:30:52 PM PDT 24
Finished Aug 17 06:30:54 PM PDT 24
Peak memory 218584 kb
Host smart-efb04166-311e-487a-8568-bc6cfa2e81a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252155300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.4252155300
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1753166798
Short name T712
Test name
Test status
Simulation time 66962412 ps
CPU time 1.09 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 218764 kb
Host smart-28db0059-bfbc-4f62-9766-add55fd17287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753166798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1753166798
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1006851417
Short name T506
Test name
Test status
Simulation time 28066253 ps
CPU time 0.87 seconds
Started Aug 17 06:29:26 PM PDT 24
Finished Aug 17 06:29:27 PM PDT 24
Peak memory 206576 kb
Host smart-5b717c69-e2c5-48b2-8d8a-3d1bc34b7b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006851417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1006851417
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.691000073
Short name T161
Test name
Test status
Simulation time 10561050 ps
CPU time 0.91 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 215392 kb
Host smart-4644528f-ad85-4a98-9e63-e45523b7342b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691000073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.691000073
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2567961335
Short name T481
Test name
Test status
Simulation time 65775644 ps
CPU time 1.02 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 217088 kb
Host smart-d9b96361-7c97-499f-9c74-3f196e3491c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567961335 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2567961335
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.686818439
Short name T192
Test name
Test status
Simulation time 72208836 ps
CPU time 1.08 seconds
Started Aug 17 06:29:54 PM PDT 24
Finished Aug 17 06:29:55 PM PDT 24
Peak memory 219640 kb
Host smart-a9e56c47-789c-463f-bee7-e07cd6257ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686818439 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.686818439
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_smoke.379973407
Short name T798
Test name
Test status
Simulation time 28390005 ps
CPU time 0.96 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 215376 kb
Host smart-3af9ab00-750e-47cb-807b-123a0705cf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379973407 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.379973407
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3810385443
Short name T187
Test name
Test status
Simulation time 206087879 ps
CPU time 2.56 seconds
Started Aug 17 06:29:43 PM PDT 24
Finished Aug 17 06:29:45 PM PDT 24
Peak memory 217164 kb
Host smart-24335bf5-560a-414e-b35e-26beb4079948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810385443 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3810385443
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2492666561
Short name T215
Test name
Test status
Simulation time 2689252283 ps
CPU time 62.07 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:30:41 PM PDT 24
Peak memory 220848 kb
Host smart-75c468e6-ab0b-4934-aaec-e264de38670b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492666561 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2492666561
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_alert.1724856622
Short name T426
Test name
Test status
Simulation time 61943837 ps
CPU time 1.13 seconds
Started Aug 17 06:30:35 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 220796 kb
Host smart-366020b1-fbfa-482f-b7d2-9f7ac7bd5ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724856622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_alert.1724856622
Directory /workspace/110.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.1551832139
Short name T663
Test name
Test status
Simulation time 89563350 ps
CPU time 1.49 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:27 PM PDT 24
Peak memory 215320 kb
Host smart-c1dd8a24-da4b-4de0-9798-711e5d84c9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551832139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1551832139
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1565059128
Short name T535
Test name
Test status
Simulation time 39730265 ps
CPU time 1.67 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 218536 kb
Host smart-3df42d06-d49b-436e-aad9-f7289c33c892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565059128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1565059128
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_alert.2615132424
Short name T559
Test name
Test status
Simulation time 61268578 ps
CPU time 1.22 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 219184 kb
Host smart-3598ba68-cc6b-40fb-b4b5-48e4f7baacfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615132424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_alert.2615132424
Directory /workspace/112.edn_alert/latest

Test location /workspace/coverage/default/112.edn_genbits.1944636123
Short name T362
Test name
Test status
Simulation time 42217906 ps
CPU time 1.42 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 218492 kb
Host smart-74aa9865-3a32-4f15-9c68-cc5819bb3ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944636123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1944636123
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_alert.1544501508
Short name T947
Test name
Test status
Simulation time 29657340 ps
CPU time 1.27 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 215768 kb
Host smart-ece70471-1ffe-4836-9e48-8be81f138332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544501508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_alert.1544501508
Directory /workspace/113.edn_alert/latest

Test location /workspace/coverage/default/113.edn_genbits.1047949211
Short name T376
Test name
Test status
Simulation time 38727916 ps
CPU time 1.43 seconds
Started Aug 17 06:30:49 PM PDT 24
Finished Aug 17 06:30:51 PM PDT 24
Peak memory 218516 kb
Host smart-b7fd4487-c4b5-494b-b8be-96ddf240292f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047949211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1047949211
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_alert.4173864867
Short name T680
Test name
Test status
Simulation time 105441458 ps
CPU time 1.14 seconds
Started Aug 17 06:30:45 PM PDT 24
Finished Aug 17 06:30:46 PM PDT 24
Peak memory 221312 kb
Host smart-023b021e-3982-4ec8-bedc-b58dfaf50bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173864867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_alert.4173864867
Directory /workspace/114.edn_alert/latest

Test location /workspace/coverage/default/114.edn_genbits.2970660552
Short name T320
Test name
Test status
Simulation time 67932799 ps
CPU time 2.57 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 219804 kb
Host smart-95e66db6-eea4-471f-a3ce-43a71be9bfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970660552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2970660552
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3426501319
Short name T467
Test name
Test status
Simulation time 80139688 ps
CPU time 1.14 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 217748 kb
Host smart-ba7c042b-3b59-4802-972e-853edc555d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426501319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3426501319
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_alert.389800313
Short name T476
Test name
Test status
Simulation time 38693452 ps
CPU time 1.13 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 221380 kb
Host smart-74a0852a-eff7-43dd-aaa4-dc5119aee54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389800313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_alert.389800313
Directory /workspace/116.edn_alert/latest

Test location /workspace/coverage/default/116.edn_genbits.2702825798
Short name T318
Test name
Test status
Simulation time 113897045 ps
CPU time 1.29 seconds
Started Aug 17 06:30:39 PM PDT 24
Finished Aug 17 06:30:40 PM PDT 24
Peak memory 218856 kb
Host smart-b10ddb65-5897-4466-81d8-1ced1c566e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702825798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2702825798
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_alert.1541028054
Short name T642
Test name
Test status
Simulation time 26495277 ps
CPU time 1.26 seconds
Started Aug 17 06:30:54 PM PDT 24
Finished Aug 17 06:30:55 PM PDT 24
Peak memory 218784 kb
Host smart-f3cfd32f-3a2c-4330-aef0-04bff0895cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541028054 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_alert.1541028054
Directory /workspace/117.edn_alert/latest

Test location /workspace/coverage/default/117.edn_genbits.1337949760
Short name T965
Test name
Test status
Simulation time 31430817 ps
CPU time 1.22 seconds
Started Aug 17 06:31:17 PM PDT 24
Finished Aug 17 06:31:18 PM PDT 24
Peak memory 217420 kb
Host smart-3fe70adb-5aa0-4f48-87a2-b5821f63a651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337949760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1337949760
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_alert.3870551797
Short name T744
Test name
Test status
Simulation time 27758788 ps
CPU time 1.19 seconds
Started Aug 17 06:31:14 PM PDT 24
Finished Aug 17 06:31:15 PM PDT 24
Peak memory 219812 kb
Host smart-d9267138-732f-47f4-ab1a-ca2f87e4d8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870551797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_alert.3870551797
Directory /workspace/118.edn_alert/latest

Test location /workspace/coverage/default/118.edn_genbits.2787751833
Short name T890
Test name
Test status
Simulation time 40497372 ps
CPU time 1.31 seconds
Started Aug 17 06:30:36 PM PDT 24
Finished Aug 17 06:30:38 PM PDT 24
Peak memory 218576 kb
Host smart-90c23090-8eca-4884-80b8-462435f96a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787751833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2787751833
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_alert.2965044541
Short name T563
Test name
Test status
Simulation time 42325575 ps
CPU time 1.12 seconds
Started Aug 17 06:30:37 PM PDT 24
Finished Aug 17 06:30:38 PM PDT 24
Peak memory 219892 kb
Host smart-8ce8d185-0a8a-41d3-8a0b-9ddb4aa420e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965044541 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_alert.2965044541
Directory /workspace/119.edn_alert/latest

Test location /workspace/coverage/default/119.edn_genbits.744024917
Short name T446
Test name
Test status
Simulation time 39553106 ps
CPU time 1.43 seconds
Started Aug 17 06:30:39 PM PDT 24
Finished Aug 17 06:30:41 PM PDT 24
Peak memory 217288 kb
Host smart-0a636f49-1794-4aae-8fe8-b13ec9c409bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744024917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.744024917
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2666512819
Short name T273
Test name
Test status
Simulation time 83851746 ps
CPU time 1.19 seconds
Started Aug 17 06:29:44 PM PDT 24
Finished Aug 17 06:29:45 PM PDT 24
Peak memory 218920 kb
Host smart-dc063759-07bc-452f-acd5-e077b8fa8214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666512819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2666512819
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.4010837293
Short name T61
Test name
Test status
Simulation time 35799401 ps
CPU time 1.23 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 206924 kb
Host smart-40385ad0-ab34-4fb3-96e7-22da2de48820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010837293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.4010837293
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.830233893
Short name T203
Test name
Test status
Simulation time 38059403 ps
CPU time 0.82 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 215432 kb
Host smart-c84fe73c-6709-4678-8ba4-61d965bac998
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830233893 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.830233893
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.2857687190
Short name T715
Test name
Test status
Simulation time 18055445 ps
CPU time 1.06 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:43 PM PDT 24
Peak memory 218324 kb
Host smart-174dceab-3a9e-4abf-bfdd-eb037cc7c2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857687190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2857687190
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.910633720
Short name T328
Test name
Test status
Simulation time 94358394 ps
CPU time 1.34 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 219000 kb
Host smart-d46af4f0-159a-4f1e-ab66-3d7dbf399a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910633720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.910633720
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1012461752
Short name T572
Test name
Test status
Simulation time 20334827 ps
CPU time 1.2 seconds
Started Aug 17 06:29:52 PM PDT 24
Finished Aug 17 06:29:53 PM PDT 24
Peak memory 224208 kb
Host smart-f452f80f-549d-4560-b8fd-fbb7d4f7780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012461752 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1012461752
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3086305898
Short name T963
Test name
Test status
Simulation time 75789234 ps
CPU time 0.98 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:32 PM PDT 24
Peak memory 214144 kb
Host smart-9c373e96-08f0-4808-b2fb-c7b80e87616f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086305898 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3086305898
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.715146187
Short name T958
Test name
Test status
Simulation time 263602660 ps
CPU time 1.88 seconds
Started Aug 17 06:29:36 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 217348 kb
Host smart-9c07a968-a49a-48fe-ba88-6af040a87ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715146187 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.715146187
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.956692979
Short name T969
Test name
Test status
Simulation time 12746173715 ps
CPU time 49.92 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 218272 kb
Host smart-ab63af86-d8af-4d32-85c5-24d601433f6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956692979 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.956692979
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_alert.451560110
Short name T99
Test name
Test status
Simulation time 263273025 ps
CPU time 1.21 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 219620 kb
Host smart-cd27bab3-bc91-47ae-93d2-cdea428065bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451560110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_alert.451560110
Directory /workspace/120.edn_alert/latest

Test location /workspace/coverage/default/120.edn_genbits.3467805356
Short name T534
Test name
Test status
Simulation time 42570695 ps
CPU time 1.42 seconds
Started Aug 17 06:30:52 PM PDT 24
Finished Aug 17 06:30:54 PM PDT 24
Peak memory 217288 kb
Host smart-5b4f07a3-af30-4e35-a6c3-e618f489f1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467805356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3467805356
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_alert.1446538664
Short name T341
Test name
Test status
Simulation time 89319202 ps
CPU time 1.1 seconds
Started Aug 17 06:31:01 PM PDT 24
Finished Aug 17 06:31:02 PM PDT 24
Peak memory 215756 kb
Host smart-2f5ec284-65f4-464a-bf6c-984d9408932e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446538664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_alert.1446538664
Directory /workspace/121.edn_alert/latest

Test location /workspace/coverage/default/122.edn_alert.892292544
Short name T582
Test name
Test status
Simulation time 39077557 ps
CPU time 1.13 seconds
Started Aug 17 06:31:00 PM PDT 24
Finished Aug 17 06:31:01 PM PDT 24
Peak memory 220172 kb
Host smart-f00a1603-9b17-48e4-ba58-9065c902b9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892292544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_alert.892292544
Directory /workspace/122.edn_alert/latest

Test location /workspace/coverage/default/122.edn_genbits.1580043391
Short name T459
Test name
Test status
Simulation time 43089119 ps
CPU time 1.22 seconds
Started Aug 17 06:30:35 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 218812 kb
Host smart-91295eae-43f1-49be-bddf-1513c3809c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580043391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1580043391
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_alert.1821347962
Short name T657
Test name
Test status
Simulation time 52135453 ps
CPU time 1.24 seconds
Started Aug 17 06:30:55 PM PDT 24
Finished Aug 17 06:30:56 PM PDT 24
Peak memory 218216 kb
Host smart-f2ac567f-204d-4ea7-8eb3-50ae6ec15786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821347962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_alert.1821347962
Directory /workspace/123.edn_alert/latest

Test location /workspace/coverage/default/123.edn_genbits.1658717080
Short name T957
Test name
Test status
Simulation time 65802883 ps
CPU time 1.95 seconds
Started Aug 17 06:30:46 PM PDT 24
Finished Aug 17 06:30:48 PM PDT 24
Peak memory 218692 kb
Host smart-55d339da-3bc4-4daa-b837-aabbc6951f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658717080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1658717080
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_alert.1791708865
Short name T163
Test name
Test status
Simulation time 27500589 ps
CPU time 1.21 seconds
Started Aug 17 06:30:48 PM PDT 24
Finished Aug 17 06:30:49 PM PDT 24
Peak memory 219844 kb
Host smart-5e69ceb4-79a8-49e9-aac1-2a89c9d6d3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791708865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_alert.1791708865
Directory /workspace/124.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.3934722150
Short name T435
Test name
Test status
Simulation time 41507093 ps
CPU time 1.5 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:25 PM PDT 24
Peak memory 217316 kb
Host smart-bc46886a-47b0-4a25-bc1e-ddd76592afd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934722150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3934722150
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_alert.3165231764
Short name T178
Test name
Test status
Simulation time 82919364 ps
CPU time 1.17 seconds
Started Aug 17 06:31:03 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 220476 kb
Host smart-0d2054e8-1f9a-4e66-99fc-6b5a51e8ad03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165231764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_alert.3165231764
Directory /workspace/125.edn_alert/latest

Test location /workspace/coverage/default/126.edn_alert.608584723
Short name T860
Test name
Test status
Simulation time 38794853 ps
CPU time 1.06 seconds
Started Aug 17 06:30:54 PM PDT 24
Finished Aug 17 06:30:55 PM PDT 24
Peak memory 218812 kb
Host smart-c73665fe-f813-4a75-a22d-04b2bac78ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608584723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_alert.608584723
Directory /workspace/126.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.3701181432
Short name T627
Test name
Test status
Simulation time 33497031 ps
CPU time 1.38 seconds
Started Aug 17 06:30:52 PM PDT 24
Finished Aug 17 06:30:54 PM PDT 24
Peak memory 218628 kb
Host smart-020576de-3d32-4043-b480-9179952c9334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701181432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3701181432
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_alert.2005231706
Short name T455
Test name
Test status
Simulation time 87542556 ps
CPU time 1.33 seconds
Started Aug 17 06:30:36 PM PDT 24
Finished Aug 17 06:30:38 PM PDT 24
Peak memory 219704 kb
Host smart-a6eabf5c-9826-4578-ad2f-30cba17c7152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005231706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_alert.2005231706
Directory /workspace/127.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.2704403784
Short name T355
Test name
Test status
Simulation time 102787591 ps
CPU time 1.63 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 218804 kb
Host smart-8a3bd949-c2a7-4741-b686-ce2080548d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704403784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2704403784
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_alert.4208491313
Short name T83
Test name
Test status
Simulation time 74818373 ps
CPU time 1.23 seconds
Started Aug 17 06:30:35 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 219740 kb
Host smart-a8fdc0aa-ee1d-4a7d-8cb8-2da7dface4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208491313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_alert.4208491313
Directory /workspace/128.edn_alert/latest

Test location /workspace/coverage/default/128.edn_genbits.3995854088
Short name T82
Test name
Test status
Simulation time 33468836 ps
CPU time 1.42 seconds
Started Aug 17 06:30:47 PM PDT 24
Finished Aug 17 06:30:48 PM PDT 24
Peak memory 218948 kb
Host smart-822542dc-e265-4b49-8654-005a63c48fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995854088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3995854088
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3978370891
Short name T401
Test name
Test status
Simulation time 56403266 ps
CPU time 1.32 seconds
Started Aug 17 06:29:40 PM PDT 24
Finished Aug 17 06:29:41 PM PDT 24
Peak memory 215720 kb
Host smart-3f4150f9-c4ce-4dd8-a3aa-dcf2bbb48c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978370891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3978370891
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.899991751
Short name T507
Test name
Test status
Simulation time 26515350 ps
CPU time 0.85 seconds
Started Aug 17 06:29:46 PM PDT 24
Finished Aug 17 06:29:47 PM PDT 24
Peak memory 206636 kb
Host smart-08d42dd9-f3c7-4b72-84d2-deaf5b7bb799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899991751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.899991751
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.3361368980
Short name T7
Test name
Test status
Simulation time 25693096 ps
CPU time 1.07 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 219716 kb
Host smart-3f332146-d18a-4521-85bb-4cd257b9bf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361368980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3361368980
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1698085479
Short name T869
Test name
Test status
Simulation time 43657668 ps
CPU time 1.75 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 218664 kb
Host smart-e5aa7957-9425-4263-8dd2-42db892f7666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698085479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1698085479
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1215700173
Short name T686
Test name
Test status
Simulation time 22012946 ps
CPU time 1.17 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 224252 kb
Host smart-cbea019f-c6fa-4090-82d0-eb3d746360df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215700173 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1215700173
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.298901897
Short name T492
Test name
Test status
Simulation time 33856805 ps
CPU time 0.89 seconds
Started Aug 17 06:29:36 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 215320 kb
Host smart-ba120c3b-af44-4ad0-86ae-d25e16b76b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298901897 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.298901897
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2515008687
Short name T934
Test name
Test status
Simulation time 506831200 ps
CPU time 3.18 seconds
Started Aug 17 06:29:52 PM PDT 24
Finished Aug 17 06:29:55 PM PDT 24
Peak memory 215360 kb
Host smart-6fcf6ed1-55c6-4986-9f8b-1d8102d30ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515008687 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2515008687
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.864940564
Short name T90
Test name
Test status
Simulation time 7704852731 ps
CPU time 44.9 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:30:20 PM PDT 24
Peak memory 216396 kb
Host smart-882150e1-21f8-4d7d-9c95-5f0a33cdffc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864940564 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.864940564
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_alert.3881531291
Short name T564
Test name
Test status
Simulation time 29209709 ps
CPU time 1.25 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 215800 kb
Host smart-57e8e077-af5e-45ac-8373-80112e259488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881531291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_alert.3881531291
Directory /workspace/130.edn_alert/latest

Test location /workspace/coverage/default/130.edn_genbits.531361794
Short name T924
Test name
Test status
Simulation time 55663095 ps
CPU time 1.2 seconds
Started Aug 17 06:30:37 PM PDT 24
Finished Aug 17 06:30:38 PM PDT 24
Peak memory 218624 kb
Host smart-c6201673-8cb9-49b7-835b-6d2afe1898dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531361794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.531361794
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_alert.3628535974
Short name T770
Test name
Test status
Simulation time 24931736 ps
CPU time 1.17 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:27 PM PDT 24
Peak memory 221000 kb
Host smart-1fddffe8-cef4-4db6-84f2-6ad9ca14032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628535974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_alert.3628535974
Directory /workspace/131.edn_alert/latest

Test location /workspace/coverage/default/131.edn_genbits.3219630055
Short name T473
Test name
Test status
Simulation time 69073686 ps
CPU time 1.11 seconds
Started Aug 17 06:30:58 PM PDT 24
Finished Aug 17 06:30:59 PM PDT 24
Peak memory 217376 kb
Host smart-f5cf77ea-20d9-4ffa-90f0-1f6222a18c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219630055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3219630055
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_alert.1160287204
Short name T628
Test name
Test status
Simulation time 111996322 ps
CPU time 1.17 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 220868 kb
Host smart-3302d4a6-766d-4d40-a9f4-d60be2b09c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160287204 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_alert.1160287204
Directory /workspace/132.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.3534372801
Short name T331
Test name
Test status
Simulation time 48346895 ps
CPU time 1.54 seconds
Started Aug 17 06:30:50 PM PDT 24
Finished Aug 17 06:30:51 PM PDT 24
Peak memory 218408 kb
Host smart-86642feb-afde-46a1-ad88-d2225f80b58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534372801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3534372801
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_alert.764101701
Short name T916
Test name
Test status
Simulation time 27908900 ps
CPU time 1.2 seconds
Started Aug 17 06:31:09 PM PDT 24
Finished Aug 17 06:31:11 PM PDT 24
Peak memory 221072 kb
Host smart-1ea3d8da-d75b-4840-96cd-eb02fc25399a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764101701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_alert.764101701
Directory /workspace/133.edn_alert/latest

Test location /workspace/coverage/default/134.edn_alert.2688064716
Short name T524
Test name
Test status
Simulation time 96213275 ps
CPU time 1.14 seconds
Started Aug 17 06:30:48 PM PDT 24
Finished Aug 17 06:30:49 PM PDT 24
Peak memory 219220 kb
Host smart-3bb839c9-8e1e-4d89-a152-77734a332446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688064716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_alert.2688064716
Directory /workspace/134.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.2437585481
Short name T511
Test name
Test status
Simulation time 64958482 ps
CPU time 1.1 seconds
Started Aug 17 06:30:51 PM PDT 24
Finished Aug 17 06:30:52 PM PDT 24
Peak memory 216400 kb
Host smart-8ac40a66-8d31-452a-8300-9d0ded3a99e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437585481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2437585481
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2281080393
Short name T826
Test name
Test status
Simulation time 65205201 ps
CPU time 1.27 seconds
Started Aug 17 06:30:58 PM PDT 24
Finished Aug 17 06:31:00 PM PDT 24
Peak memory 218576 kb
Host smart-271e4e11-767e-43d2-b903-a9221cdb79ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281080393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2281080393
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_alert.1219059000
Short name T170
Test name
Test status
Simulation time 27453383 ps
CPU time 1.22 seconds
Started Aug 17 06:30:58 PM PDT 24
Finished Aug 17 06:30:59 PM PDT 24
Peak memory 220100 kb
Host smart-cc3ca5ad-f895-49d6-aea6-181e1f07de23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219059000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_alert.1219059000
Directory /workspace/136.edn_alert/latest

Test location /workspace/coverage/default/136.edn_genbits.1598408304
Short name T953
Test name
Test status
Simulation time 39745287 ps
CPU time 1.37 seconds
Started Aug 17 06:30:47 PM PDT 24
Finished Aug 17 06:30:48 PM PDT 24
Peak memory 218628 kb
Host smart-404513fe-d150-462f-b4b8-d8f1c99cdea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598408304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1598408304
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_alert.2500862511
Short name T169
Test name
Test status
Simulation time 94106974 ps
CPU time 1.17 seconds
Started Aug 17 06:30:54 PM PDT 24
Finished Aug 17 06:30:55 PM PDT 24
Peak memory 220516 kb
Host smart-f125d042-aa47-49d7-bc06-8c493c5b4b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500862511 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_alert.2500862511
Directory /workspace/137.edn_alert/latest

Test location /workspace/coverage/default/137.edn_genbits.2624342337
Short name T384
Test name
Test status
Simulation time 22446478 ps
CPU time 1.07 seconds
Started Aug 17 06:30:56 PM PDT 24
Finished Aug 17 06:30:58 PM PDT 24
Peak memory 217256 kb
Host smart-fd86f19f-9ea3-4254-bd1f-5e7549c43d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624342337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2624342337
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_alert.548268328
Short name T371
Test name
Test status
Simulation time 64327352 ps
CPU time 1.17 seconds
Started Aug 17 06:31:03 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 218888 kb
Host smart-3746efbf-d69c-4082-a875-7562c57949dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548268328 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_alert.548268328
Directory /workspace/138.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.1049420994
Short name T508
Test name
Test status
Simulation time 28623519 ps
CPU time 1.23 seconds
Started Aug 17 06:31:07 PM PDT 24
Finished Aug 17 06:31:09 PM PDT 24
Peak memory 217516 kb
Host smart-3b70ba0d-c71a-47b0-a3f5-fea02dda989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049420994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1049420994
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_alert.2836888624
Short name T157
Test name
Test status
Simulation time 26853749 ps
CPU time 1.21 seconds
Started Aug 17 06:31:04 PM PDT 24
Finished Aug 17 06:31:05 PM PDT 24
Peak memory 218592 kb
Host smart-72ccd5bc-888c-4cfe-a6bf-3eb2ad5b1703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836888624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_alert.2836888624
Directory /workspace/139.edn_alert/latest

Test location /workspace/coverage/default/139.edn_genbits.3769024339
Short name T650
Test name
Test status
Simulation time 171111639 ps
CPU time 2.02 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 220888 kb
Host smart-2afdc471-814b-481e-8f14-ae53fdb030cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769024339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3769024339
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3867646737
Short name T578
Test name
Test status
Simulation time 62721340 ps
CPU time 1.11 seconds
Started Aug 17 06:30:01 PM PDT 24
Finished Aug 17 06:30:02 PM PDT 24
Peak memory 218684 kb
Host smart-928b0b2e-471c-4bac-a0c5-32d0a7eb8848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867646737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3867646737
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.786810353
Short name T912
Test name
Test status
Simulation time 29992596 ps
CPU time 0.93 seconds
Started Aug 17 06:29:44 PM PDT 24
Finished Aug 17 06:29:45 PM PDT 24
Peak memory 206792 kb
Host smart-debc53d3-9304-4a3d-8ac7-307abfc4305f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786810353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.786810353
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.917320943
Short name T701
Test name
Test status
Simulation time 65789219 ps
CPU time 1.03 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 218676 kb
Host smart-31adbd2f-6825-47eb-9856-3965679e063e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917320943 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.917320943
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2182623117
Short name T172
Test name
Test status
Simulation time 19462698 ps
CPU time 1.07 seconds
Started Aug 17 06:29:45 PM PDT 24
Finished Aug 17 06:29:47 PM PDT 24
Peak memory 218552 kb
Host smart-7817ab44-1114-4a76-b84f-3b1fe8baf502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182623117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2182623117
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1059859271
Short name T302
Test name
Test status
Simulation time 32523965 ps
CPU time 1.39 seconds
Started Aug 17 06:29:40 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 219972 kb
Host smart-b29a48a2-da3e-449a-bf8a-7419c71a1ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059859271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1059859271
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.296937162
Short name T32
Test name
Test status
Simulation time 24835749 ps
CPU time 1.03 seconds
Started Aug 17 06:30:20 PM PDT 24
Finished Aug 17 06:30:21 PM PDT 24
Peak memory 215976 kb
Host smart-31f04256-3cbf-4d08-8a47-8eebc3961a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296937162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.296937162
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2903228033
Short name T437
Test name
Test status
Simulation time 17844882 ps
CPU time 1.01 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:32 PM PDT 24
Peak memory 215376 kb
Host smart-e37cbb94-d1ea-40ee-8ad0-4d4f7fce1d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903228033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2903228033
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.25320703
Short name T689
Test name
Test status
Simulation time 251143323 ps
CPU time 5.07 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 220300 kb
Host smart-33ab7a6a-50f9-4b4a-bddc-0cea7dead38b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25320703 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.25320703
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2494127728
Short name T489
Test name
Test status
Simulation time 18506267944 ps
CPU time 76.43 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:30:58 PM PDT 24
Peak memory 218832 kb
Host smart-e985d886-9f1c-4da9-8587-d5a1a3897a3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494127728 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2494127728
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_alert.345574776
Short name T361
Test name
Test status
Simulation time 74913083 ps
CPU time 1.11 seconds
Started Aug 17 06:30:52 PM PDT 24
Finished Aug 17 06:30:53 PM PDT 24
Peak memory 218756 kb
Host smart-58cb8d1e-b91e-4a2c-be1e-8a2a75b05760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345574776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_alert.345574776
Directory /workspace/140.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.1472982585
Short name T695
Test name
Test status
Simulation time 75415379 ps
CPU time 1.36 seconds
Started Aug 17 06:30:38 PM PDT 24
Finished Aug 17 06:30:39 PM PDT 24
Peak memory 218980 kb
Host smart-90201dc2-f4f9-451f-9612-e099b70f45e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472982585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1472982585
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_alert.3151411506
Short name T47
Test name
Test status
Simulation time 49037825 ps
CPU time 1.13 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:35 PM PDT 24
Peak memory 219932 kb
Host smart-d9183019-aebe-441c-b8fa-15f2f8a8b976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151411506 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_alert.3151411506
Directory /workspace/141.edn_alert/latest

Test location /workspace/coverage/default/141.edn_genbits.1728636916
Short name T570
Test name
Test status
Simulation time 69533422 ps
CPU time 1.11 seconds
Started Aug 17 06:30:37 PM PDT 24
Finished Aug 17 06:30:38 PM PDT 24
Peak memory 218892 kb
Host smart-157521d6-5f54-4d07-9930-1e45170d89f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728636916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1728636916
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_alert.2977922126
Short name T856
Test name
Test status
Simulation time 50872723 ps
CPU time 1.32 seconds
Started Aug 17 06:30:41 PM PDT 24
Finished Aug 17 06:30:42 PM PDT 24
Peak memory 220504 kb
Host smart-08878275-4461-43c8-8f08-07e8489723ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977922126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_alert.2977922126
Directory /workspace/142.edn_alert/latest

Test location /workspace/coverage/default/143.edn_genbits.2541169491
Short name T959
Test name
Test status
Simulation time 52953227 ps
CPU time 2.11 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 220528 kb
Host smart-6afdcdf6-9905-4bb4-9736-9dff6b32d893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541169491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2541169491
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_alert.338876875
Short name T905
Test name
Test status
Simulation time 23810732 ps
CPU time 1.16 seconds
Started Aug 17 06:30:32 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 219792 kb
Host smart-7f7390c5-88bb-4b4c-90fa-c9801145e8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338876875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_alert.338876875
Directory /workspace/144.edn_alert/latest

Test location /workspace/coverage/default/144.edn_genbits.2708600884
Short name T694
Test name
Test status
Simulation time 44540181 ps
CPU time 1.09 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 217244 kb
Host smart-cfc59833-efdd-45de-9466-374667b69d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708600884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2708600884
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_alert.1727874623
Short name T789
Test name
Test status
Simulation time 29821002 ps
CPU time 1.27 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 219412 kb
Host smart-c4407121-f479-4b86-bdde-d1775f0df096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727874623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_alert.1727874623
Directory /workspace/145.edn_alert/latest

Test location /workspace/coverage/default/145.edn_genbits.313223025
Short name T373
Test name
Test status
Simulation time 96346515 ps
CPU time 1.62 seconds
Started Aug 17 06:30:35 PM PDT 24
Finished Aug 17 06:30:37 PM PDT 24
Peak memory 218668 kb
Host smart-8cbf6f31-6d0f-417e-9613-573a4c8874dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313223025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.313223025
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_alert.1501030792
Short name T421
Test name
Test status
Simulation time 233782929 ps
CPU time 1.18 seconds
Started Aug 17 06:30:49 PM PDT 24
Finished Aug 17 06:30:50 PM PDT 24
Peak memory 220184 kb
Host smart-317293cd-9684-41ca-8538-7fe0586984f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501030792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_alert.1501030792
Directory /workspace/146.edn_alert/latest

Test location /workspace/coverage/default/146.edn_genbits.2945222748
Short name T918
Test name
Test status
Simulation time 92225372 ps
CPU time 1.18 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 217300 kb
Host smart-8dec52aa-d8c1-4f99-a1e8-5760ffa0abe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945222748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2945222748
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_alert.4148392174
Short name T103
Test name
Test status
Simulation time 42111030 ps
CPU time 1.16 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 219464 kb
Host smart-a430c36d-37e6-412a-bd3b-016250c9f143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148392174 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_alert.4148392174
Directory /workspace/147.edn_alert/latest

Test location /workspace/coverage/default/147.edn_genbits.3789091719
Short name T68
Test name
Test status
Simulation time 77702408 ps
CPU time 1.14 seconds
Started Aug 17 06:30:59 PM PDT 24
Finished Aug 17 06:31:01 PM PDT 24
Peak memory 217288 kb
Host smart-d9cc1ce1-c3f6-49d0-a3aa-cadac22190ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789091719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3789091719
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_alert.46064207
Short name T374
Test name
Test status
Simulation time 391746164 ps
CPU time 1.55 seconds
Started Aug 17 06:31:02 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 215764 kb
Host smart-1f55b5bc-b146-4ef7-b58e-a13b1347a902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46064207 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_alert.46064207
Directory /workspace/148.edn_alert/latest

Test location /workspace/coverage/default/148.edn_genbits.1410070647
Short name T618
Test name
Test status
Simulation time 27765782 ps
CPU time 1.29 seconds
Started Aug 17 06:30:36 PM PDT 24
Finished Aug 17 06:30:37 PM PDT 24
Peak memory 220228 kb
Host smart-8fd7207a-a93e-4b52-a610-bb638797c933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410070647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1410070647
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_alert.2595328160
Short name T589
Test name
Test status
Simulation time 49651411 ps
CPU time 1.19 seconds
Started Aug 17 06:31:01 PM PDT 24
Finished Aug 17 06:31:02 PM PDT 24
Peak memory 219840 kb
Host smart-a4eda91f-e765-4439-8d2c-e477b0e06550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595328160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_alert.2595328160
Directory /workspace/149.edn_alert/latest

Test location /workspace/coverage/default/149.edn_genbits.3322109664
Short name T62
Test name
Test status
Simulation time 54791516 ps
CPU time 0.9 seconds
Started Aug 17 06:30:35 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 217292 kb
Host smart-e5c7601d-1fe2-4a9f-b096-9de204e47a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322109664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3322109664
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1625683557
Short name T77
Test name
Test status
Simulation time 31648214 ps
CPU time 1.34 seconds
Started Aug 17 06:29:46 PM PDT 24
Finished Aug 17 06:29:48 PM PDT 24
Peak memory 215704 kb
Host smart-5e26c3a1-c98b-47b8-b795-cb709834f87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625683557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1625683557
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3000317856
Short name T714
Test name
Test status
Simulation time 35326623 ps
CPU time 0.96 seconds
Started Aug 17 06:29:46 PM PDT 24
Finished Aug 17 06:29:47 PM PDT 24
Peak memory 206800 kb
Host smart-9159c054-dd6c-4647-bbcd-b230f4f8d881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000317856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3000317856
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1268212988
Short name T119
Test name
Test status
Simulation time 76451859 ps
CPU time 1.04 seconds
Started Aug 17 06:29:36 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 216884 kb
Host smart-3b9cd632-eb20-4091-9245-36e7e2a4de11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268212988 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1268212988
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2704879352
Short name T411
Test name
Test status
Simulation time 31021748 ps
CPU time 0.86 seconds
Started Aug 17 06:29:45 PM PDT 24
Finished Aug 17 06:29:46 PM PDT 24
Peak memory 219404 kb
Host smart-662e7455-556d-4b66-9b7a-013d54f30693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704879352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2704879352
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2856562083
Short name T806
Test name
Test status
Simulation time 42328313 ps
CPU time 1.56 seconds
Started Aug 17 06:30:01 PM PDT 24
Finished Aug 17 06:30:03 PM PDT 24
Peak memory 217360 kb
Host smart-d22bda4a-0a9d-4a8a-80f5-747e515b7fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856562083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2856562083
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3801038387
Short name T919
Test name
Test status
Simulation time 23599237 ps
CPU time 0.99 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 215588 kb
Host smart-61aba089-3aff-4539-b91f-f6f9a42fd90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801038387 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3801038387
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2067612399
Short name T617
Test name
Test status
Simulation time 16427800 ps
CPU time 0.96 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 215340 kb
Host smart-1430e073-6dbc-4dd4-adf3-a8f05fb902e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067612399 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2067612399
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1733965166
Short name T224
Test name
Test status
Simulation time 63492510 ps
CPU time 1.32 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 207180 kb
Host smart-4827cc62-bc62-420a-91fc-bda9dcabb875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733965166 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1733965166
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1455383244
Short name T214
Test name
Test status
Simulation time 8764515314 ps
CPU time 54.85 seconds
Started Aug 17 06:29:46 PM PDT 24
Finished Aug 17 06:30:40 PM PDT 24
Peak memory 218176 kb
Host smart-548c21a3-2e88-4a30-98f4-5bd9c3499773
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455383244 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1455383244
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_alert.1356776074
Short name T598
Test name
Test status
Simulation time 44049757 ps
CPU time 1.16 seconds
Started Aug 17 06:30:48 PM PDT 24
Finished Aug 17 06:30:49 PM PDT 24
Peak memory 218984 kb
Host smart-5ba947e3-86df-4737-ad1c-0fd474739544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356776074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_alert.1356776074
Directory /workspace/150.edn_alert/latest

Test location /workspace/coverage/default/150.edn_genbits.139903191
Short name T819
Test name
Test status
Simulation time 23383993 ps
CPU time 1.2 seconds
Started Aug 17 06:30:35 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 217484 kb
Host smart-f8537883-e678-45a3-8b85-35c24be9a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139903191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.139903191
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_alert.3082852996
Short name T179
Test name
Test status
Simulation time 40991330 ps
CPU time 1.27 seconds
Started Aug 17 06:30:48 PM PDT 24
Finished Aug 17 06:30:49 PM PDT 24
Peak memory 221212 kb
Host smart-c26a459d-c99e-45d3-8f91-03a3cbadfa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082852996 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_alert.3082852996
Directory /workspace/151.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.254164982
Short name T691
Test name
Test status
Simulation time 80429265 ps
CPU time 1.19 seconds
Started Aug 17 06:30:50 PM PDT 24
Finished Aug 17 06:30:51 PM PDT 24
Peak memory 219088 kb
Host smart-2a71a830-693b-42eb-adad-3e4724801f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254164982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.254164982
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_alert.3302053089
Short name T603
Test name
Test status
Simulation time 41850592 ps
CPU time 1.17 seconds
Started Aug 17 06:31:06 PM PDT 24
Finished Aug 17 06:31:07 PM PDT 24
Peak memory 218640 kb
Host smart-7b0baead-e112-4963-989d-4c371455fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302053089 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_alert.3302053089
Directory /workspace/152.edn_alert/latest

Test location /workspace/coverage/default/152.edn_genbits.2521829421
Short name T917
Test name
Test status
Simulation time 73429683 ps
CPU time 1.03 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 217332 kb
Host smart-c06e229b-d75f-4a4d-82b1-cb7ee97cd5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521829421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2521829421
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_alert.1441858308
Short name T660
Test name
Test status
Simulation time 24637396 ps
CPU time 1.25 seconds
Started Aug 17 06:30:35 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 219844 kb
Host smart-50859253-4f14-4be4-9623-5745fc68d8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441858308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_alert.1441858308
Directory /workspace/153.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.1507830006
Short name T529
Test name
Test status
Simulation time 138500056 ps
CPU time 1.94 seconds
Started Aug 17 06:30:46 PM PDT 24
Finished Aug 17 06:30:48 PM PDT 24
Peak memory 217524 kb
Host smart-1bb14609-1c8e-4b0d-9361-954967aa68a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507830006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1507830006
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_alert.2571560747
Short name T584
Test name
Test status
Simulation time 47054033 ps
CPU time 1.17 seconds
Started Aug 17 06:31:00 PM PDT 24
Finished Aug 17 06:31:01 PM PDT 24
Peak memory 220052 kb
Host smart-72f1e0eb-4575-4675-ae77-48a74290404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571560747 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_alert.2571560747
Directory /workspace/154.edn_alert/latest

Test location /workspace/coverage/default/154.edn_genbits.1443550144
Short name T889
Test name
Test status
Simulation time 30009330 ps
CPU time 1.21 seconds
Started Aug 17 06:30:40 PM PDT 24
Finished Aug 17 06:30:41 PM PDT 24
Peak memory 217436 kb
Host smart-76432fe0-9409-48e5-89d9-0590efe50013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443550144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1443550144
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_alert.2383333759
Short name T487
Test name
Test status
Simulation time 29609944 ps
CPU time 1.21 seconds
Started Aug 17 06:30:44 PM PDT 24
Finished Aug 17 06:30:45 PM PDT 24
Peak memory 218668 kb
Host smart-9fd28a19-6210-4a05-9506-6f53af3edfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383333759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_alert.2383333759
Directory /workspace/155.edn_alert/latest

Test location /workspace/coverage/default/156.edn_alert.3289042327
Short name T76
Test name
Test status
Simulation time 39468571 ps
CPU time 1.15 seconds
Started Aug 17 06:31:13 PM PDT 24
Finished Aug 17 06:31:14 PM PDT 24
Peak memory 215768 kb
Host smart-65bf07c5-a06b-4678-8730-4d825f55f1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289042327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_alert.3289042327
Directory /workspace/156.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2104507319
Short name T771
Test name
Test status
Simulation time 84060949 ps
CPU time 1.12 seconds
Started Aug 17 06:30:39 PM PDT 24
Finished Aug 17 06:30:40 PM PDT 24
Peak memory 219628 kb
Host smart-201b766a-40ae-4f2d-904a-64ba670477b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104507319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2104507319
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_alert.2755792400
Short name T245
Test name
Test status
Simulation time 82208650 ps
CPU time 1.26 seconds
Started Aug 17 06:30:37 PM PDT 24
Finished Aug 17 06:30:39 PM PDT 24
Peak memory 218992 kb
Host smart-4dc8a97a-140b-4289-90c3-113fc7c3e85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755792400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_alert.2755792400
Directory /workspace/157.edn_alert/latest

Test location /workspace/coverage/default/157.edn_genbits.3593591882
Short name T787
Test name
Test status
Simulation time 35513769 ps
CPU time 1.26 seconds
Started Aug 17 06:30:58 PM PDT 24
Finished Aug 17 06:30:59 PM PDT 24
Peak memory 217284 kb
Host smart-1bbe918f-c9f3-4d6c-8200-0ca757bd990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593591882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3593591882
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.248380085
Short name T281
Test name
Test status
Simulation time 4368951788 ps
CPU time 88.35 seconds
Started Aug 17 06:31:02 PM PDT 24
Finished Aug 17 06:32:31 PM PDT 24
Peak memory 218696 kb
Host smart-f3018972-1e0c-4f4c-b2e0-df51eaec6a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248380085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.248380085
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_alert.4148479715
Short name T128
Test name
Test status
Simulation time 36294861 ps
CPU time 1.25 seconds
Started Aug 17 06:30:42 PM PDT 24
Finished Aug 17 06:30:48 PM PDT 24
Peak memory 218608 kb
Host smart-1c215bcd-999a-478b-9ef9-3ba9bdebd961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148479715 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_alert.4148479715
Directory /workspace/159.edn_alert/latest

Test location /workspace/coverage/default/159.edn_genbits.536447895
Short name T10
Test name
Test status
Simulation time 98657065 ps
CPU time 1.49 seconds
Started Aug 17 06:30:53 PM PDT 24
Finished Aug 17 06:30:55 PM PDT 24
Peak memory 219096 kb
Host smart-440cf008-5fb8-406d-b2f6-2650b145a6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536447895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.536447895
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3047837109
Short name T616
Test name
Test status
Simulation time 53094813 ps
CPU time 1.22 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 220932 kb
Host smart-ac4c4da2-e644-451a-981f-f303fa2c4c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047837109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3047837109
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2501848346
Short name T398
Test name
Test status
Simulation time 24424695 ps
CPU time 0.91 seconds
Started Aug 17 06:29:42 PM PDT 24
Finished Aug 17 06:29:43 PM PDT 24
Peak memory 206784 kb
Host smart-16381377-c8f7-4c8c-a6f8-eaed703566d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501848346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2501848346
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2845231799
Short name T513
Test name
Test status
Simulation time 32318712 ps
CPU time 1.13 seconds
Started Aug 17 06:29:44 PM PDT 24
Finished Aug 17 06:29:45 PM PDT 24
Peak memory 215440 kb
Host smart-d0d0f1c1-2acf-46b4-9df3-9de00fc54be9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845231799 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2845231799
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.948172442
Short name T573
Test name
Test status
Simulation time 19461326 ps
CPU time 1.17 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 224064 kb
Host smart-0507705a-6a47-4a20-8c16-cac0242bafd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948172442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.948172442
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1211914829
Short name T910
Test name
Test status
Simulation time 93946098 ps
CPU time 1.87 seconds
Started Aug 17 06:29:44 PM PDT 24
Finished Aug 17 06:29:46 PM PDT 24
Peak memory 220460 kb
Host smart-346e59a4-2fa7-4097-9f4d-2e14c8bd0073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211914829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1211914829
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.325169859
Short name T51
Test name
Test status
Simulation time 23355095 ps
CPU time 1.15 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 224380 kb
Host smart-91d0f5e6-beb0-4792-aa8d-1c6b32d9c5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325169859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.325169859
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1153344925
Short name T230
Test name
Test status
Simulation time 21209037 ps
CPU time 0.96 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 215340 kb
Host smart-174a392f-0179-443e-9e5c-a1c81a6dd73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153344925 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1153344925
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2449838659
Short name T89
Test name
Test status
Simulation time 662090010 ps
CPU time 3.19 seconds
Started Aug 17 06:29:46 PM PDT 24
Finished Aug 17 06:29:49 PM PDT 24
Peak memory 217416 kb
Host smart-0daca8e2-d9af-41e6-8e53-256042e52cfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449838659 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2449838659
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_alert.3069742779
Short name T892
Test name
Test status
Simulation time 364554274 ps
CPU time 1.12 seconds
Started Aug 17 06:30:53 PM PDT 24
Finished Aug 17 06:30:54 PM PDT 24
Peak memory 218504 kb
Host smart-aaa85d53-891a-46a8-9f97-666eaea28671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069742779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_alert.3069742779
Directory /workspace/160.edn_alert/latest

Test location /workspace/coverage/default/160.edn_genbits.1968311992
Short name T728
Test name
Test status
Simulation time 50026711 ps
CPU time 2.05 seconds
Started Aug 17 06:31:05 PM PDT 24
Finished Aug 17 06:31:08 PM PDT 24
Peak memory 218648 kb
Host smart-773bd679-8a50-46cd-9bd0-1838b545aca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968311992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1968311992
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_alert.4165506456
Short name T482
Test name
Test status
Simulation time 30114208 ps
CPU time 1.25 seconds
Started Aug 17 06:31:03 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 219396 kb
Host smart-f40e9179-e8a0-45bd-87dd-8ad71806ef2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165506456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_alert.4165506456
Directory /workspace/161.edn_alert/latest

Test location /workspace/coverage/default/161.edn_genbits.3341838915
Short name T11
Test name
Test status
Simulation time 72980870 ps
CPU time 1.38 seconds
Started Aug 17 06:31:00 PM PDT 24
Finished Aug 17 06:31:01 PM PDT 24
Peak memory 219824 kb
Host smart-18e2cc55-bdb1-4fbf-82b8-23ee8cc231e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341838915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3341838915
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_alert.3600801351
Short name T516
Test name
Test status
Simulation time 38297018 ps
CPU time 1.16 seconds
Started Aug 17 06:30:44 PM PDT 24
Finished Aug 17 06:30:46 PM PDT 24
Peak memory 219856 kb
Host smart-842b246f-ccc6-49bc-9a44-b16cd9fe3827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600801351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_alert.3600801351
Directory /workspace/162.edn_alert/latest

Test location /workspace/coverage/default/162.edn_genbits.189683273
Short name T911
Test name
Test status
Simulation time 110271270 ps
CPU time 2.43 seconds
Started Aug 17 06:30:34 PM PDT 24
Finished Aug 17 06:30:37 PM PDT 24
Peak memory 220076 kb
Host smart-53c7e5f0-2653-4131-867c-b10f865e255f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189683273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.189683273
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_alert.934045649
Short name T620
Test name
Test status
Simulation time 73103006 ps
CPU time 1.11 seconds
Started Aug 17 06:31:15 PM PDT 24
Finished Aug 17 06:31:16 PM PDT 24
Peak memory 219568 kb
Host smart-465f6f45-1547-494d-aba9-e2c7416d1be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934045649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_alert.934045649
Directory /workspace/163.edn_alert/latest

Test location /workspace/coverage/default/163.edn_genbits.879512654
Short name T904
Test name
Test status
Simulation time 34771348 ps
CPU time 1.5 seconds
Started Aug 17 06:31:05 PM PDT 24
Finished Aug 17 06:31:06 PM PDT 24
Peak memory 218652 kb
Host smart-e064e9b8-bf3d-4ceb-af08-36e26dc5e76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879512654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.879512654
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_alert.3737921094
Short name T440
Test name
Test status
Simulation time 25488463 ps
CPU time 1.21 seconds
Started Aug 17 06:31:09 PM PDT 24
Finished Aug 17 06:31:10 PM PDT 24
Peak memory 218832 kb
Host smart-60a12243-d9df-4788-936b-8a342c297e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737921094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_alert.3737921094
Directory /workspace/164.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.2510912872
Short name T644
Test name
Test status
Simulation time 76824474 ps
CPU time 1.49 seconds
Started Aug 17 06:30:50 PM PDT 24
Finished Aug 17 06:30:52 PM PDT 24
Peak memory 218492 kb
Host smart-d9e0ba97-ea19-48f7-b9d1-6896103515cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510912872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2510912872
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_alert.729124425
Short name T525
Test name
Test status
Simulation time 31250217 ps
CPU time 1.3 seconds
Started Aug 17 06:31:01 PM PDT 24
Finished Aug 17 06:31:02 PM PDT 24
Peak memory 219864 kb
Host smart-0c9880d3-0692-4326-8696-76fe9e5ce2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729124425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_alert.729124425
Directory /workspace/165.edn_alert/latest

Test location /workspace/coverage/default/165.edn_genbits.1590468674
Short name T67
Test name
Test status
Simulation time 47181760 ps
CPU time 1.68 seconds
Started Aug 17 06:30:57 PM PDT 24
Finished Aug 17 06:30:59 PM PDT 24
Peak memory 218496 kb
Host smart-b6fa55b9-591d-414e-af0e-e7728a6ca960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590468674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1590468674
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_alert.3163480898
Short name T654
Test name
Test status
Simulation time 25024084 ps
CPU time 1.09 seconds
Started Aug 17 06:30:54 PM PDT 24
Finished Aug 17 06:30:55 PM PDT 24
Peak memory 220000 kb
Host smart-6032424d-b2eb-4c0e-a00f-3aa11b59c9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163480898 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_alert.3163480898
Directory /workspace/166.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.289906092
Short name T565
Test name
Test status
Simulation time 74618288 ps
CPU time 1.65 seconds
Started Aug 17 06:31:00 PM PDT 24
Finished Aug 17 06:31:02 PM PDT 24
Peak memory 218864 kb
Host smart-bff15ee8-3a8d-49a2-9ac2-5e60a8e1e900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289906092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.289906092
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1852211458
Short name T228
Test name
Test status
Simulation time 47494860 ps
CPU time 1.15 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 215336 kb
Host smart-7d3068ea-e3ea-4b1d-8d0b-98f7425c4ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852211458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1852211458
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_alert.1616633074
Short name T825
Test name
Test status
Simulation time 58221159 ps
CPU time 1.31 seconds
Started Aug 17 06:31:07 PM PDT 24
Finished Aug 17 06:31:08 PM PDT 24
Peak memory 215736 kb
Host smart-6b06a3ae-1e74-4704-9fb1-be4eec84dc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616633074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_alert.1616633074
Directory /workspace/168.edn_alert/latest

Test location /workspace/coverage/default/168.edn_genbits.3802625132
Short name T755
Test name
Test status
Simulation time 51168435 ps
CPU time 1.16 seconds
Started Aug 17 06:30:42 PM PDT 24
Finished Aug 17 06:30:44 PM PDT 24
Peak memory 217268 kb
Host smart-4d4b5b51-86b2-4d2c-95b9-aa04c0326c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802625132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3802625132
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_alert.1827954439
Short name T662
Test name
Test status
Simulation time 27013308 ps
CPU time 1.23 seconds
Started Aug 17 06:30:50 PM PDT 24
Finished Aug 17 06:30:51 PM PDT 24
Peak memory 220616 kb
Host smart-4e36a083-5c93-48e3-a8a8-4b602b479e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827954439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_alert.1827954439
Directory /workspace/169.edn_alert/latest

Test location /workspace/coverage/default/169.edn_genbits.411715044
Short name T78
Test name
Test status
Simulation time 57844514 ps
CPU time 1.63 seconds
Started Aug 17 06:30:59 PM PDT 24
Finished Aug 17 06:31:00 PM PDT 24
Peak memory 218492 kb
Host smart-813073bb-fdb5-47a6-bbae-8507f234e55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411715044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.411715044
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2673658145
Short name T275
Test name
Test status
Simulation time 38173622 ps
CPU time 1.03 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 220952 kb
Host smart-1e2707b8-bbbc-40ed-98f5-bc8fa50c4d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673658145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2673658145
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3902775383
Short name T706
Test name
Test status
Simulation time 19163944 ps
CPU time 0.81 seconds
Started Aug 17 06:29:47 PM PDT 24
Finished Aug 17 06:29:48 PM PDT 24
Peak memory 206508 kb
Host smart-ba84eacb-8d11-4045-94ca-1c8e834f94e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902775383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3902775383
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3224764945
Short name T186
Test name
Test status
Simulation time 14141196 ps
CPU time 0.89 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 215460 kb
Host smart-072f705d-7ab2-4aff-8937-3e7b09f2a1d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224764945 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3224764945
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.37422512
Short name T560
Test name
Test status
Simulation time 45875550 ps
CPU time 1.13 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 217148 kb
Host smart-1f89c328-6b74-4abc-b2d0-24287adf4a6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37422512 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_dis
able_auto_req_mode.37422512
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_genbits.1926628474
Short name T658
Test name
Test status
Simulation time 55504915 ps
CPU time 1.16 seconds
Started Aug 17 06:29:42 PM PDT 24
Finished Aug 17 06:29:43 PM PDT 24
Peak memory 220484 kb
Host smart-6a68c8ea-e794-47a6-afce-f93e3c5bd5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926628474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1926628474
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1337722027
Short name T824
Test name
Test status
Simulation time 39586590 ps
CPU time 0.89 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 215552 kb
Host smart-fccb84cb-0644-4e83-851d-10da3fe30c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337722027 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1337722027
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.256332301
Short name T416
Test name
Test status
Simulation time 100726168 ps
CPU time 0.95 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 207140 kb
Host smart-165de593-7dbe-4db2-a4e8-23f1277340be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256332301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.256332301
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2705431732
Short name T91
Test name
Test status
Simulation time 267543086 ps
CPU time 5.41 seconds
Started Aug 17 06:29:49 PM PDT 24
Finished Aug 17 06:29:55 PM PDT 24
Peak memory 215408 kb
Host smart-588746ac-a04e-408e-bd38-44591aeb9c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705431732 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2705431732
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1280030891
Short name T687
Test name
Test status
Simulation time 12036775061 ps
CPU time 75.7 seconds
Started Aug 17 06:29:43 PM PDT 24
Finished Aug 17 06:30:58 PM PDT 24
Peak memory 221532 kb
Host smart-8cf70995-5bca-4ed3-9612-85dec7ae2d19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280030891 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1280030891
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_alert.3108284534
Short name T750
Test name
Test status
Simulation time 44295205 ps
CPU time 1.16 seconds
Started Aug 17 06:31:01 PM PDT 24
Finished Aug 17 06:31:03 PM PDT 24
Peak memory 219364 kb
Host smart-796322c0-cc6f-41d6-85b8-4f4cdcb6938d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108284534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_alert.3108284534
Directory /workspace/170.edn_alert/latest

Test location /workspace/coverage/default/171.edn_alert.3429235170
Short name T116
Test name
Test status
Simulation time 25610744 ps
CPU time 1.17 seconds
Started Aug 17 06:30:50 PM PDT 24
Finished Aug 17 06:30:51 PM PDT 24
Peak memory 220548 kb
Host smart-5386bc14-d466-4742-add0-f37652b75241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429235170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_alert.3429235170
Directory /workspace/171.edn_alert/latest

Test location /workspace/coverage/default/171.edn_genbits.1165396766
Short name T827
Test name
Test status
Simulation time 40523221 ps
CPU time 1.41 seconds
Started Aug 17 06:31:03 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 217324 kb
Host smart-1ddd20c4-a7d5-451c-a9c9-357fb2056c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165396766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1165396766
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_alert.1010830577
Short name T206
Test name
Test status
Simulation time 37823606 ps
CPU time 1.16 seconds
Started Aug 17 06:30:56 PM PDT 24
Finished Aug 17 06:30:57 PM PDT 24
Peak memory 219888 kb
Host smart-110dc643-022e-4349-b232-5a30c90599a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010830577 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_alert.1010830577
Directory /workspace/172.edn_alert/latest

Test location /workspace/coverage/default/172.edn_genbits.3820743235
Short name T586
Test name
Test status
Simulation time 47464876 ps
CPU time 1.56 seconds
Started Aug 17 06:31:02 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 218736 kb
Host smart-78971d5b-bcd3-4356-80c1-e1beff20ccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820743235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3820743235
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.4131842829
Short name T66
Test name
Test status
Simulation time 91563949 ps
CPU time 1.53 seconds
Started Aug 17 06:30:57 PM PDT 24
Finished Aug 17 06:30:59 PM PDT 24
Peak memory 219020 kb
Host smart-fefe15ff-bb40-4ce4-87b4-b6a24e640588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131842829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.4131842829
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_alert.396993085
Short name T158
Test name
Test status
Simulation time 25902141 ps
CPU time 1.23 seconds
Started Aug 17 06:31:09 PM PDT 24
Finished Aug 17 06:31:10 PM PDT 24
Peak memory 218672 kb
Host smart-17acd258-7f24-456e-accf-10b91daafec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396993085 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_alert.396993085
Directory /workspace/174.edn_alert/latest

Test location /workspace/coverage/default/174.edn_genbits.4118826015
Short name T780
Test name
Test status
Simulation time 60461387 ps
CPU time 1.23 seconds
Started Aug 17 06:31:09 PM PDT 24
Finished Aug 17 06:31:10 PM PDT 24
Peak memory 218644 kb
Host smart-e1f9df01-b1af-4434-b8ae-2703033e6a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118826015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.4118826015
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_alert.135439003
Short name T167
Test name
Test status
Simulation time 44457807 ps
CPU time 1.1 seconds
Started Aug 17 06:31:05 PM PDT 24
Finished Aug 17 06:31:07 PM PDT 24
Peak memory 219724 kb
Host smart-0a25f42b-1b2e-4cc7-a152-89f88efa2261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135439003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_alert.135439003
Directory /workspace/175.edn_alert/latest

Test location /workspace/coverage/default/175.edn_genbits.262194530
Short name T458
Test name
Test status
Simulation time 34394990 ps
CPU time 1.42 seconds
Started Aug 17 06:31:02 PM PDT 24
Finished Aug 17 06:31:03 PM PDT 24
Peak memory 217772 kb
Host smart-723c4c2a-27dd-485a-bc02-80a8c2ef8ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262194530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.262194530
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_alert.2182665653
Short name T705
Test name
Test status
Simulation time 31376674 ps
CPU time 1.23 seconds
Started Aug 17 06:31:00 PM PDT 24
Finished Aug 17 06:31:01 PM PDT 24
Peak memory 220528 kb
Host smart-43030daa-b872-4556-8243-278813ff9e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182665653 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_alert.2182665653
Directory /workspace/176.edn_alert/latest

Test location /workspace/coverage/default/176.edn_genbits.1608246764
Short name T300
Test name
Test status
Simulation time 43606744 ps
CPU time 1.59 seconds
Started Aug 17 06:31:05 PM PDT 24
Finished Aug 17 06:31:07 PM PDT 24
Peak memory 218376 kb
Host smart-d34f0a62-2ede-4844-86ed-22c1e2bf3584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608246764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1608246764
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_alert.2294418117
Short name T349
Test name
Test status
Simulation time 47863829 ps
CPU time 1.31 seconds
Started Aug 17 06:31:11 PM PDT 24
Finished Aug 17 06:31:13 PM PDT 24
Peak memory 220600 kb
Host smart-7aeed3db-0f61-4552-9de4-1015f93df7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294418117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_alert.2294418117
Directory /workspace/177.edn_alert/latest

Test location /workspace/coverage/default/177.edn_genbits.886154228
Short name T812
Test name
Test status
Simulation time 49686105 ps
CPU time 1.81 seconds
Started Aug 17 06:31:14 PM PDT 24
Finished Aug 17 06:31:16 PM PDT 24
Peak memory 217564 kb
Host smart-e0b9e221-51ba-4b0f-a28c-391f6addbb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886154228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.886154228
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_alert.3283286375
Short name T166
Test name
Test status
Simulation time 25110857 ps
CPU time 1.14 seconds
Started Aug 17 06:31:19 PM PDT 24
Finished Aug 17 06:31:20 PM PDT 24
Peak memory 219724 kb
Host smart-32d8d940-4408-4134-b704-78a189539233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283286375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_alert.3283286375
Directory /workspace/178.edn_alert/latest

Test location /workspace/coverage/default/178.edn_genbits.3346731697
Short name T428
Test name
Test status
Simulation time 463049894 ps
CPU time 1.67 seconds
Started Aug 17 06:31:08 PM PDT 24
Finished Aug 17 06:31:09 PM PDT 24
Peak memory 219000 kb
Host smart-7444cfa8-2b31-405d-ba7e-8631765cc88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346731697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3346731697
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_alert.1318253813
Short name T926
Test name
Test status
Simulation time 57037232 ps
CPU time 1.26 seconds
Started Aug 17 06:31:12 PM PDT 24
Finished Aug 17 06:31:14 PM PDT 24
Peak memory 218888 kb
Host smart-3273686c-fe5a-494c-afc3-067452727e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318253813 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_alert.1318253813
Directory /workspace/179.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert.3508166729
Short name T114
Test name
Test status
Simulation time 91041052 ps
CPU time 1.3 seconds
Started Aug 17 06:30:09 PM PDT 24
Finished Aug 17 06:30:10 PM PDT 24
Peak memory 218552 kb
Host smart-eb61fefb-0c41-46be-a500-438dc8ef6a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508166729 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3508166729
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2622864233
Short name T567
Test name
Test status
Simulation time 23716246 ps
CPU time 0.88 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 215136 kb
Host smart-806bfa4b-484a-40bb-b1ef-42ffcaadedc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622864233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2622864233
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3927590676
Short name T72
Test name
Test status
Simulation time 30142173 ps
CPU time 0.87 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 215084 kb
Host smart-49010d84-05ad-417b-96ea-97ec92ffc931
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927590676 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3927590676
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.488994709
Short name T427
Test name
Test status
Simulation time 181605047 ps
CPU time 1.12 seconds
Started Aug 17 06:29:42 PM PDT 24
Finished Aug 17 06:29:43 PM PDT 24
Peak memory 219712 kb
Host smart-9c760939-c056-452f-a984-5a7783b2405e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488994709 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.488994709
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1673199748
Short name T747
Test name
Test status
Simulation time 24652231 ps
CPU time 0.91 seconds
Started Aug 17 06:29:50 PM PDT 24
Finished Aug 17 06:29:51 PM PDT 24
Peak memory 218364 kb
Host smart-74dd88d5-b160-4f00-b0c4-cb3318008dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673199748 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1673199748
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.173259467
Short name T682
Test name
Test status
Simulation time 36730635 ps
CPU time 1.31 seconds
Started Aug 17 06:29:47 PM PDT 24
Finished Aug 17 06:29:49 PM PDT 24
Peak memory 218660 kb
Host smart-15c5fb62-b03e-4522-bb88-3aebcf28584b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173259467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.173259467
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1923915107
Short name T741
Test name
Test status
Simulation time 24991777 ps
CPU time 0.91 seconds
Started Aug 17 06:29:52 PM PDT 24
Finished Aug 17 06:29:53 PM PDT 24
Peak memory 215824 kb
Host smart-d8e952b4-e1ba-4f15-8366-22a713cb2a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923915107 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1923915107
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2446871855
Short name T290
Test name
Test status
Simulation time 23336493 ps
CPU time 0.92 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 207096 kb
Host smart-648eafb7-fc2c-460c-8c7e-a34cd014e802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446871855 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2446871855
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2881946752
Short name T875
Test name
Test status
Simulation time 1845940084 ps
CPU time 4.13 seconds
Started Aug 17 06:29:50 PM PDT 24
Finished Aug 17 06:29:54 PM PDT 24
Peak memory 215344 kb
Host smart-68dce07d-986c-4af0-aaeb-18711d30568c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881946752 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2881946752
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_alert.2515863386
Short name T588
Test name
Test status
Simulation time 40284799 ps
CPU time 1.07 seconds
Started Aug 17 06:31:04 PM PDT 24
Finished Aug 17 06:31:05 PM PDT 24
Peak memory 220740 kb
Host smart-2b82d5f5-f6e6-40c3-b545-d0dda1b1a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515863386 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_alert.2515863386
Directory /workspace/180.edn_alert/latest

Test location /workspace/coverage/default/180.edn_genbits.2930373272
Short name T859
Test name
Test status
Simulation time 34710585 ps
CPU time 1.18 seconds
Started Aug 17 06:30:58 PM PDT 24
Finished Aug 17 06:30:59 PM PDT 24
Peak memory 217496 kb
Host smart-13fc95cb-5976-4c91-9077-28ddfddae3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930373272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2930373272
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_alert.2021974388
Short name T720
Test name
Test status
Simulation time 96016876 ps
CPU time 1.3 seconds
Started Aug 17 06:31:07 PM PDT 24
Finished Aug 17 06:31:09 PM PDT 24
Peak memory 215768 kb
Host smart-7b842ebe-3d95-4ebd-a458-06cd54ab5aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021974388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_alert.2021974388
Directory /workspace/181.edn_alert/latest

Test location /workspace/coverage/default/181.edn_genbits.3577731924
Short name T943
Test name
Test status
Simulation time 67211013 ps
CPU time 2.3 seconds
Started Aug 17 06:31:02 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 219008 kb
Host smart-a15a7f65-1ee0-4f45-bd31-8203faaeabae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577731924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3577731924
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_alert.3893408604
Short name T347
Test name
Test status
Simulation time 29576345 ps
CPU time 1.3 seconds
Started Aug 17 06:30:59 PM PDT 24
Finished Aug 17 06:31:01 PM PDT 24
Peak memory 218612 kb
Host smart-7fdc201c-6c0d-4749-a99e-d43a7d1e0d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893408604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_alert.3893408604
Directory /workspace/182.edn_alert/latest

Test location /workspace/coverage/default/182.edn_genbits.3893731668
Short name T700
Test name
Test status
Simulation time 40915801 ps
CPU time 1.29 seconds
Started Aug 17 06:31:06 PM PDT 24
Finished Aug 17 06:31:07 PM PDT 24
Peak memory 218476 kb
Host smart-46a8e561-e4b4-4772-8d9b-a11d8997ff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893731668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3893731668
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_alert.2586401172
Short name T445
Test name
Test status
Simulation time 40495593 ps
CPU time 1.04 seconds
Started Aug 17 06:31:09 PM PDT 24
Finished Aug 17 06:31:11 PM PDT 24
Peak memory 220800 kb
Host smart-7b5ffb0d-29a5-4de9-9fb3-40ed681a25a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586401172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_alert.2586401172
Directory /workspace/183.edn_alert/latest

Test location /workspace/coverage/default/183.edn_genbits.4273720611
Short name T704
Test name
Test status
Simulation time 54528853 ps
CPU time 1.24 seconds
Started Aug 17 06:31:19 PM PDT 24
Finished Aug 17 06:31:21 PM PDT 24
Peak memory 215360 kb
Host smart-c6020cd2-064a-4a7e-9589-c9358b0d1fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273720611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.4273720611
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_alert.48531082
Short name T181
Test name
Test status
Simulation time 60241741 ps
CPU time 1.19 seconds
Started Aug 17 06:31:14 PM PDT 24
Finished Aug 17 06:31:15 PM PDT 24
Peak memory 220688 kb
Host smart-57b34219-0537-436f-9ce0-568ebbae5c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48531082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_alert.48531082
Directory /workspace/184.edn_alert/latest

Test location /workspace/coverage/default/184.edn_genbits.1943774357
Short name T450
Test name
Test status
Simulation time 33935674 ps
CPU time 1.45 seconds
Started Aug 17 06:31:05 PM PDT 24
Finished Aug 17 06:31:06 PM PDT 24
Peak memory 217476 kb
Host smart-0ad32c19-11cd-4f88-93ad-99d7dbb8d0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943774357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1943774357
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_alert.3972503658
Short name T619
Test name
Test status
Simulation time 91483017 ps
CPU time 1.26 seconds
Started Aug 17 06:31:15 PM PDT 24
Finished Aug 17 06:31:17 PM PDT 24
Peak memory 220160 kb
Host smart-d5f63bc2-4dfd-41cb-9fc6-2cc20d8be309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972503658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_alert.3972503658
Directory /workspace/185.edn_alert/latest

Test location /workspace/coverage/default/185.edn_genbits.418435761
Short name T709
Test name
Test status
Simulation time 49548886 ps
CPU time 1.23 seconds
Started Aug 17 06:31:06 PM PDT 24
Finished Aug 17 06:31:08 PM PDT 24
Peak memory 217480 kb
Host smart-4b16c332-60cf-4e3d-8a6d-2b609ca59be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418435761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.418435761
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_alert.3908922
Short name T285
Test name
Test status
Simulation time 47386201 ps
CPU time 1.24 seconds
Started Aug 17 06:31:14 PM PDT 24
Finished Aug 17 06:31:15 PM PDT 24
Peak memory 219764 kb
Host smart-48bbdb15-b8d5-491f-bcbb-f63264df71bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908922 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_alert.3908922
Directory /workspace/186.edn_alert/latest

Test location /workspace/coverage/default/186.edn_genbits.799769104
Short name T413
Test name
Test status
Simulation time 40285592 ps
CPU time 1.64 seconds
Started Aug 17 06:30:51 PM PDT 24
Finished Aug 17 06:30:53 PM PDT 24
Peak memory 220584 kb
Host smart-0ab6d6e4-ffeb-4a3a-b3ff-dcc5645b1b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799769104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.799769104
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_alert.2814866461
Short name T610
Test name
Test status
Simulation time 38467578 ps
CPU time 1.16 seconds
Started Aug 17 06:31:03 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 219928 kb
Host smart-c42489cb-9717-4913-b143-d09f7d7e4537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814866461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_alert.2814866461
Directory /workspace/187.edn_alert/latest

Test location /workspace/coverage/default/187.edn_genbits.677020616
Short name T562
Test name
Test status
Simulation time 40739957 ps
CPU time 1.44 seconds
Started Aug 17 06:31:07 PM PDT 24
Finished Aug 17 06:31:08 PM PDT 24
Peak memory 218768 kb
Host smart-ddcc26ed-46bc-4eb8-bd00-7ace7b1e3f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677020616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.677020616
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_alert.2733911288
Short name T133
Test name
Test status
Simulation time 266772151 ps
CPU time 1.17 seconds
Started Aug 17 06:31:10 PM PDT 24
Finished Aug 17 06:31:11 PM PDT 24
Peak memory 218792 kb
Host smart-fd404f68-4d6d-4cd2-8432-327a08d027bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733911288 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_alert.2733911288
Directory /workspace/188.edn_alert/latest

Test location /workspace/coverage/default/188.edn_genbits.2758781613
Short name T20
Test name
Test status
Simulation time 62395367 ps
CPU time 1.3 seconds
Started Aug 17 06:31:10 PM PDT 24
Finished Aug 17 06:31:12 PM PDT 24
Peak memory 217312 kb
Host smart-a4df4275-fb0a-4780-9521-33cde5cc3230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758781613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.2758781613
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_alert.1168622414
Short name T164
Test name
Test status
Simulation time 77785018 ps
CPU time 1.13 seconds
Started Aug 17 06:30:59 PM PDT 24
Finished Aug 17 06:31:00 PM PDT 24
Peak memory 219792 kb
Host smart-172feca8-ffd7-4de9-8fde-21fd663a5875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168622414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_alert.1168622414
Directory /workspace/189.edn_alert/latest

Test location /workspace/coverage/default/189.edn_genbits.2620196829
Short name T8
Test name
Test status
Simulation time 1337327667 ps
CPU time 10.72 seconds
Started Aug 17 06:31:05 PM PDT 24
Finished Aug 17 06:31:16 PM PDT 24
Peak memory 217540 kb
Host smart-45ee048c-aa97-45df-ae47-5d004d833bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620196829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2620196829
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.256972733
Short name T972
Test name
Test status
Simulation time 249845311 ps
CPU time 1.27 seconds
Started Aug 17 06:29:40 PM PDT 24
Finished Aug 17 06:29:41 PM PDT 24
Peak memory 219276 kb
Host smart-b1b7e4e1-eb59-46a3-8fa4-d2f169dcd098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256972733 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.256972733
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.295130444
Short name T673
Test name
Test status
Simulation time 105244227 ps
CPU time 0.86 seconds
Started Aug 17 06:29:52 PM PDT 24
Finished Aug 17 06:29:53 PM PDT 24
Peak memory 206732 kb
Host smart-bef9629b-f48f-45b2-bef3-11bc46363eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295130444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.295130444
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3770757489
Short name T625
Test name
Test status
Simulation time 24782345 ps
CPU time 0.83 seconds
Started Aug 17 06:29:48 PM PDT 24
Finished Aug 17 06:29:49 PM PDT 24
Peak memory 215172 kb
Host smart-19d8ca7a-5d31-43ec-b4a2-1fdddc511ae6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770757489 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3770757489
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3172285332
Short name T194
Test name
Test status
Simulation time 104497036 ps
CPU time 1.14 seconds
Started Aug 17 06:29:50 PM PDT 24
Finished Aug 17 06:29:52 PM PDT 24
Peak memory 216980 kb
Host smart-8132c1f0-b56f-43ae-9cca-12d43435e14c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172285332 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3172285332
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1591439583
Short name T109
Test name
Test status
Simulation time 20901741 ps
CPU time 1.25 seconds
Started Aug 17 06:30:06 PM PDT 24
Finished Aug 17 06:30:07 PM PDT 24
Peak memory 229676 kb
Host smart-c007fad0-0b06-475b-a8fa-866c799d6e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591439583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1591439583
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3413084445
Short name T886
Test name
Test status
Simulation time 25913303 ps
CPU time 1.19 seconds
Started Aug 17 06:29:55 PM PDT 24
Finished Aug 17 06:29:56 PM PDT 24
Peak memory 217336 kb
Host smart-f9d843ee-31b6-4e6d-86ba-03cc7ffc5684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413084445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3413084445
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3047353380
Short name T800
Test name
Test status
Simulation time 23331250 ps
CPU time 1.05 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 215496 kb
Host smart-6cc5e4a0-db91-4c9f-9389-1dd5bf5f780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047353380 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3047353380
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3591438547
Short name T323
Test name
Test status
Simulation time 63962282 ps
CPU time 0.92 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 214904 kb
Host smart-32ffc57d-d2ed-4663-b72a-b9f9aa5be789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591438547 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3591438547
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.542782910
Short name T231
Test name
Test status
Simulation time 106267864 ps
CPU time 2.39 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 217264 kb
Host smart-24c94462-bf21-4b6a-a007-00ddcc5238a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542782910 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.542782910
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_alert.1829214493
Short name T138
Test name
Test status
Simulation time 155530894 ps
CPU time 1.19 seconds
Started Aug 17 06:31:10 PM PDT 24
Finished Aug 17 06:31:11 PM PDT 24
Peak memory 218412 kb
Host smart-3658c560-3dbe-4331-8040-dfbd359af2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829214493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_alert.1829214493
Directory /workspace/190.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.2528749299
Short name T734
Test name
Test status
Simulation time 44107463 ps
CPU time 1.34 seconds
Started Aug 17 06:31:00 PM PDT 24
Finished Aug 17 06:31:02 PM PDT 24
Peak memory 218444 kb
Host smart-6e230fe0-94c8-41f6-872b-c7edb74f4506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528749299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2528749299
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_alert.4009130889
Short name T396
Test name
Test status
Simulation time 25326068 ps
CPU time 1.23 seconds
Started Aug 17 06:31:16 PM PDT 24
Finished Aug 17 06:31:17 PM PDT 24
Peak memory 220516 kb
Host smart-4ef22298-483e-4abd-9722-c4f87b1fd5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009130889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_alert.4009130889
Directory /workspace/191.edn_alert/latest

Test location /workspace/coverage/default/191.edn_genbits.1720305579
Short name T608
Test name
Test status
Simulation time 39621334 ps
CPU time 1.4 seconds
Started Aug 17 06:31:19 PM PDT 24
Finished Aug 17 06:31:21 PM PDT 24
Peak memory 219556 kb
Host smart-c105e3fd-cb0d-4b9d-b9ea-16f30446015a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720305579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1720305579
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_alert.669191395
Short name T745
Test name
Test status
Simulation time 75388610 ps
CPU time 1.12 seconds
Started Aug 17 06:31:10 PM PDT 24
Finished Aug 17 06:31:12 PM PDT 24
Peak memory 218700 kb
Host smart-9e70d533-00ba-4f38-a98b-1e0b0ec87453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669191395 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_alert.669191395
Directory /workspace/192.edn_alert/latest

Test location /workspace/coverage/default/192.edn_genbits.990755237
Short name T505
Test name
Test status
Simulation time 62422095 ps
CPU time 1.42 seconds
Started Aug 17 06:31:18 PM PDT 24
Finished Aug 17 06:31:20 PM PDT 24
Peak memory 218520 kb
Host smart-a3a9d3d4-a8a5-48d5-8beb-05cd6c41a2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990755237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.990755237
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2314212014
Short name T698
Test name
Test status
Simulation time 37643870 ps
CPU time 1.51 seconds
Started Aug 17 06:31:19 PM PDT 24
Finished Aug 17 06:31:31 PM PDT 24
Peak memory 219604 kb
Host smart-b5de4546-e359-46e6-a639-20c639dc4417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314212014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2314212014
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_alert.3039896795
Short name T613
Test name
Test status
Simulation time 96342570 ps
CPU time 1.21 seconds
Started Aug 17 06:31:04 PM PDT 24
Finished Aug 17 06:31:06 PM PDT 24
Peak memory 218528 kb
Host smart-6882aaa0-574f-42df-89f8-664e275b9c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039896795 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_alert.3039896795
Directory /workspace/194.edn_alert/latest

Test location /workspace/coverage/default/194.edn_genbits.3823927586
Short name T18
Test name
Test status
Simulation time 264907727 ps
CPU time 2.1 seconds
Started Aug 17 06:31:01 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 215396 kb
Host smart-eb802e9b-9a5a-4242-b7cc-e516e02edccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823927586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3823927586
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_alert.1422350330
Short name T143
Test name
Test status
Simulation time 83930904 ps
CPU time 1.35 seconds
Started Aug 17 06:31:14 PM PDT 24
Finished Aug 17 06:31:16 PM PDT 24
Peak memory 219708 kb
Host smart-48a46139-5208-4d5f-9af1-5e18a857c6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422350330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_alert.1422350330
Directory /workspace/195.edn_alert/latest

Test location /workspace/coverage/default/195.edn_genbits.1441499622
Short name T600
Test name
Test status
Simulation time 94501520 ps
CPU time 1.44 seconds
Started Aug 17 06:31:05 PM PDT 24
Finished Aug 17 06:31:07 PM PDT 24
Peak memory 220376 kb
Host smart-0da931c3-dd9b-4833-89b7-6b92f9485aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441499622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1441499622
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.1983366095
Short name T552
Test name
Test status
Simulation time 43887604 ps
CPU time 1.52 seconds
Started Aug 17 06:31:04 PM PDT 24
Finished Aug 17 06:31:06 PM PDT 24
Peak memory 217408 kb
Host smart-a899144b-7ee1-4a75-996f-fc670f69de0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983366095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1983366095
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_alert.552749168
Short name T939
Test name
Test status
Simulation time 27100687 ps
CPU time 1.16 seconds
Started Aug 17 06:31:04 PM PDT 24
Finished Aug 17 06:31:05 PM PDT 24
Peak memory 218440 kb
Host smart-2173873d-0e62-4c02-82c4-22ba54b3be39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552749168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_alert.552749168
Directory /workspace/197.edn_alert/latest

Test location /workspace/coverage/default/197.edn_genbits.2694647035
Short name T39
Test name
Test status
Simulation time 29927566 ps
CPU time 1.14 seconds
Started Aug 17 06:31:06 PM PDT 24
Finished Aug 17 06:31:07 PM PDT 24
Peak memory 217668 kb
Host smart-f180b370-2ef3-4932-a43d-303a1a70b247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694647035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2694647035
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_alert.810411240
Short name T149
Test name
Test status
Simulation time 28551950 ps
CPU time 1.31 seconds
Started Aug 17 06:31:02 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 218696 kb
Host smart-23bb6d8e-abbc-414e-ae12-fa7b4695cccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810411240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_alert.810411240
Directory /workspace/198.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.3769342957
Short name T725
Test name
Test status
Simulation time 32204174 ps
CPU time 1.41 seconds
Started Aug 17 06:31:08 PM PDT 24
Finished Aug 17 06:31:09 PM PDT 24
Peak memory 219908 kb
Host smart-f4efeb38-294d-4567-907f-9b011b451160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769342957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3769342957
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_alert.1711193823
Short name T460
Test name
Test status
Simulation time 77231689 ps
CPU time 1.18 seconds
Started Aug 17 06:31:03 PM PDT 24
Finished Aug 17 06:31:05 PM PDT 24
Peak memory 219780 kb
Host smart-119d65a2-1d6f-45a3-bbb2-a94a1b5f5b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711193823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_alert.1711193823
Directory /workspace/199.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert.2987665547
Short name T343
Test name
Test status
Simulation time 72541463 ps
CPU time 1.19 seconds
Started Aug 17 06:29:19 PM PDT 24
Finished Aug 17 06:29:20 PM PDT 24
Peak memory 215704 kb
Host smart-cc14a6e0-ef73-44c4-9aa1-1e698c0c6423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987665547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2987665547
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1224424911
Short name T931
Test name
Test status
Simulation time 25168903 ps
CPU time 1.03 seconds
Started Aug 17 06:29:29 PM PDT 24
Finished Aug 17 06:29:30 PM PDT 24
Peak memory 206944 kb
Host smart-7182b943-69e8-42ed-b56a-c0350bba974f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224424911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1224424911
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.591599428
Short name T27
Test name
Test status
Simulation time 13379129 ps
CPU time 0.9 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 215572 kb
Host smart-018e5df6-0a8b-4ec2-bc3c-168a88defdc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591599428 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.591599428
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3313025759
Short name T120
Test name
Test status
Simulation time 72263776 ps
CPU time 1.02 seconds
Started Aug 17 06:29:21 PM PDT 24
Finished Aug 17 06:29:22 PM PDT 24
Peak memory 216800 kb
Host smart-d6de2099-b4b2-4406-a91c-33a7b0ed31e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313025759 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3313025759
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2428885312
Short name T544
Test name
Test status
Simulation time 20932607 ps
CPU time 1.15 seconds
Started Aug 17 06:29:23 PM PDT 24
Finished Aug 17 06:29:24 PM PDT 24
Peak memory 219620 kb
Host smart-dc35f003-9c8b-46f8-99f3-c4c1dbc709c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428885312 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2428885312
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3309866437
Short name T222
Test name
Test status
Simulation time 364039739 ps
CPU time 3.93 seconds
Started Aug 17 06:29:29 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 220684 kb
Host smart-223b5513-580a-41b6-b2e4-f96206d8d06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309866437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3309866437
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1939554412
Short name T973
Test name
Test status
Simulation time 27838115 ps
CPU time 1.11 seconds
Started Aug 17 06:29:18 PM PDT 24
Finished Aug 17 06:29:19 PM PDT 24
Peak memory 224248 kb
Host smart-e09fb586-0492-4f28-8680-6e2ed47b05bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939554412 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1939554412
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1346767537
Short name T955
Test name
Test status
Simulation time 43612337 ps
CPU time 0.91 seconds
Started Aug 17 06:29:16 PM PDT 24
Finished Aug 17 06:29:17 PM PDT 24
Peak memory 207156 kb
Host smart-7c74b5e7-037d-4a53-b010-dbcb73df1276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346767537 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1346767537
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.4261687692
Short name T530
Test name
Test status
Simulation time 30178580 ps
CPU time 0.99 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 215376 kb
Host smart-74505639-c462-4989-ad90-2f08b7ff25fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261687692 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.4261687692
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1008193041
Short name T785
Test name
Test status
Simulation time 44001190 ps
CPU time 0.98 seconds
Started Aug 17 06:29:14 PM PDT 24
Finished Aug 17 06:29:15 PM PDT 24
Peak memory 206540 kb
Host smart-c9b30bba-8c40-41d5-ae39-ba05aec484a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008193041 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1008193041
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.991287305
Short name T219
Test name
Test status
Simulation time 7602901387 ps
CPU time 85.52 seconds
Started Aug 17 06:29:21 PM PDT 24
Finished Aug 17 06:30:47 PM PDT 24
Peak memory 217728 kb
Host smart-3905ec01-de60-4075-bfdc-9ed179643577
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991287305 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.991287305
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4205041056
Short name T758
Test name
Test status
Simulation time 210871236 ps
CPU time 1.25 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 219408 kb
Host smart-6202ab21-7165-4590-a977-d6486a55db79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205041056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4205041056
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.4026219500
Short name T515
Test name
Test status
Simulation time 13922708 ps
CPU time 0.87 seconds
Started Aug 17 06:29:48 PM PDT 24
Finished Aug 17 06:29:49 PM PDT 24
Peak memory 206988 kb
Host smart-7f911cda-4a16-4f35-98e5-1b5a2074fe39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026219500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.4026219500
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1094054456
Short name T201
Test name
Test status
Simulation time 20049660 ps
CPU time 0.84 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 215344 kb
Host smart-1c4649ed-2289-42f8-b841-0e6201a84bf5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094054456 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1094054456
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.3596478499
Short name T5
Test name
Test status
Simulation time 25785393 ps
CPU time 1.15 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 220548 kb
Host smart-e75e5e59-d9e0-4933-a33c-a6e8915511b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596478499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3596478499
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1026169204
Short name T730
Test name
Test status
Simulation time 25063879 ps
CPU time 1.16 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 217448 kb
Host smart-dbcd2657-b2e8-47e3-af76-8f7042f39396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026169204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1026169204
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3132005362
Short name T520
Test name
Test status
Simulation time 33667154 ps
CPU time 0.87 seconds
Started Aug 17 06:29:47 PM PDT 24
Finished Aug 17 06:29:48 PM PDT 24
Peak memory 215568 kb
Host smart-42e6a8b4-c37d-4aa0-9b1d-4fb732b06a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132005362 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3132005362
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.3217521014
Short name T240
Test name
Test status
Simulation time 54309311 ps
CPU time 0.93 seconds
Started Aug 17 06:30:02 PM PDT 24
Finished Aug 17 06:30:03 PM PDT 24
Peak memory 215304 kb
Host smart-1eca4d6b-f95d-4191-ad12-16e39c8e5745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217521014 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3217521014
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.28861963
Short name T234
Test name
Test status
Simulation time 24388030 ps
CPU time 1.06 seconds
Started Aug 17 06:29:48 PM PDT 24
Finished Aug 17 06:29:49 PM PDT 24
Peak memory 206512 kb
Host smart-4551bd29-5f79-4600-a150-4071cfc7e494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28861963 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.28861963
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1158549152
Short name T577
Test name
Test status
Simulation time 46229147378 ps
CPU time 85.3 seconds
Started Aug 17 06:29:48 PM PDT 24
Finished Aug 17 06:31:13 PM PDT 24
Peak memory 217668 kb
Host smart-72b8fc4e-3269-4df1-8e6d-e6173ecefb13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158549152 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1158549152
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3153786116
Short name T453
Test name
Test status
Simulation time 256754859 ps
CPU time 1.6 seconds
Started Aug 17 06:31:18 PM PDT 24
Finished Aug 17 06:31:19 PM PDT 24
Peak memory 218728 kb
Host smart-8f1d1657-ebfe-433e-973c-128c0f84a478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153786116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3153786116
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1009974966
Short name T317
Test name
Test status
Simulation time 125006908 ps
CPU time 2.57 seconds
Started Aug 17 06:31:20 PM PDT 24
Finished Aug 17 06:31:22 PM PDT 24
Peak memory 218956 kb
Host smart-ed4c5e19-ecda-404f-a4a9-617a9393e190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009974966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1009974966
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.519048643
Short name T70
Test name
Test status
Simulation time 49036255 ps
CPU time 1.77 seconds
Started Aug 17 06:31:22 PM PDT 24
Finished Aug 17 06:31:24 PM PDT 24
Peak memory 220564 kb
Host smart-2e99fd69-ab63-4da6-be0c-1676a86efb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519048643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.519048643
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1504016352
Short name T940
Test name
Test status
Simulation time 147863664 ps
CPU time 1.72 seconds
Started Aug 17 06:31:21 PM PDT 24
Finished Aug 17 06:31:23 PM PDT 24
Peak memory 218836 kb
Host smart-3670f03e-85a1-476e-aa0c-bf4af6d539c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504016352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1504016352
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2211177784
Short name T418
Test name
Test status
Simulation time 39046390 ps
CPU time 1.23 seconds
Started Aug 17 06:31:22 PM PDT 24
Finished Aug 17 06:31:24 PM PDT 24
Peak memory 218524 kb
Host smart-c50a4d14-b5a1-400d-952b-2678d3eebb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211177784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2211177784
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1495776590
Short name T379
Test name
Test status
Simulation time 34740234 ps
CPU time 1.36 seconds
Started Aug 17 06:31:27 PM PDT 24
Finished Aug 17 06:31:29 PM PDT 24
Peak memory 217364 kb
Host smart-db5498e3-ba61-4e99-a637-634ca98d4a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495776590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1495776590
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2190367089
Short name T304
Test name
Test status
Simulation time 54527049 ps
CPU time 1.13 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:26 PM PDT 24
Peak memory 217408 kb
Host smart-46e96b4f-d83f-4759-8005-4170d8f0016e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190367089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2190367089
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.922366492
Short name T591
Test name
Test status
Simulation time 87638037 ps
CPU time 1.61 seconds
Started Aug 17 06:31:24 PM PDT 24
Finished Aug 17 06:31:27 PM PDT 24
Peak memory 217472 kb
Host smart-c124c5f2-1c6b-496d-a6fb-7fe190890bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922366492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.922366492
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2431716032
Short name T462
Test name
Test status
Simulation time 57789942 ps
CPU time 1.68 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:26 PM PDT 24
Peak memory 218696 kb
Host smart-9333139a-38d2-42b3-a3b3-fbdb8c3dcc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431716032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2431716032
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3946088483
Short name T710
Test name
Test status
Simulation time 64964448 ps
CPU time 1.44 seconds
Started Aug 17 06:31:21 PM PDT 24
Finished Aug 17 06:31:23 PM PDT 24
Peak memory 215344 kb
Host smart-dc00b8c0-9084-4dad-b5f0-2f5b76aef945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946088483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3946088483
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.4216943404
Short name T478
Test name
Test status
Simulation time 95558215 ps
CPU time 1.04 seconds
Started Aug 17 06:29:43 PM PDT 24
Finished Aug 17 06:29:44 PM PDT 24
Peak memory 220408 kb
Host smart-72f3a5c8-012e-42ce-8cf2-58994e8a1fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216943404 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.4216943404
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1227839022
Short name T633
Test name
Test status
Simulation time 18087077 ps
CPU time 1.14 seconds
Started Aug 17 06:30:14 PM PDT 24
Finished Aug 17 06:30:15 PM PDT 24
Peak memory 206876 kb
Host smart-cd5f2ff8-e810-41ef-8177-b3ef4df51a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227839022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1227839022
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2273405334
Short name T840
Test name
Test status
Simulation time 22996245 ps
CPU time 0.93 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 215300 kb
Host smart-50239394-1be9-4e83-be59-39ff73541569
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273405334 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2273405334
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3484969797
Short name T781
Test name
Test status
Simulation time 36909417 ps
CPU time 1.13 seconds
Started Aug 17 06:29:47 PM PDT 24
Finished Aug 17 06:29:49 PM PDT 24
Peak memory 216916 kb
Host smart-2059ea60-d579-4630-89c0-7853689bc7f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484969797 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3484969797
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.40923914
Short name T740
Test name
Test status
Simulation time 25148045 ps
CPU time 0.94 seconds
Started Aug 17 06:29:46 PM PDT 24
Finished Aug 17 06:29:47 PM PDT 24
Peak memory 218728 kb
Host smart-581215e5-5a77-4494-8435-286cdb5ea349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40923914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.40923914
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.4197433308
Short name T901
Test name
Test status
Simulation time 77422830 ps
CPU time 1.07 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 217448 kb
Host smart-3e9963a3-ec66-4e83-84ae-23dd51476a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197433308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.4197433308
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.896318458
Short name T377
Test name
Test status
Simulation time 20658121 ps
CPU time 1.18 seconds
Started Aug 17 06:29:50 PM PDT 24
Finished Aug 17 06:29:51 PM PDT 24
Peak memory 224200 kb
Host smart-18bedb22-0aa3-47ec-8d8e-051d8b4c94d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896318458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.896318458
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.523090813
Short name T456
Test name
Test status
Simulation time 46818637 ps
CPU time 0.88 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 215364 kb
Host smart-d3c8c552-cd66-4156-8ff8-a1dd4d890c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523090813 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.523090813
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1430470204
Short name T721
Test name
Test status
Simulation time 104309428 ps
CPU time 1.82 seconds
Started Aug 17 06:29:47 PM PDT 24
Finished Aug 17 06:29:49 PM PDT 24
Peak memory 217220 kb
Host smart-fe24c37b-0b34-4e67-a0a5-ac75b7173308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430470204 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1430470204
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3030105414
Short name T212
Test name
Test status
Simulation time 9343330891 ps
CPU time 82.65 seconds
Started Aug 17 06:29:36 PM PDT 24
Finished Aug 17 06:30:59 PM PDT 24
Peak memory 221800 kb
Host smart-3a395641-85da-446c-8901-e155dca302ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030105414 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3030105414
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3210291655
Short name T366
Test name
Test status
Simulation time 58314995 ps
CPU time 2.33 seconds
Started Aug 17 06:31:22 PM PDT 24
Finished Aug 17 06:31:25 PM PDT 24
Peak memory 218640 kb
Host smart-63f84b45-5ec5-42df-98fe-78b4a9ecdbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210291655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3210291655
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3939881861
Short name T893
Test name
Test status
Simulation time 62834201 ps
CPU time 1.34 seconds
Started Aug 17 06:31:33 PM PDT 24
Finished Aug 17 06:31:35 PM PDT 24
Peak memory 220084 kb
Host smart-5d61dc77-8d96-4e5d-b8b4-f6737ce6f5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939881861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3939881861
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1303999780
Short name T677
Test name
Test status
Simulation time 72309570 ps
CPU time 1.55 seconds
Started Aug 17 06:31:21 PM PDT 24
Finished Aug 17 06:31:23 PM PDT 24
Peak memory 219164 kb
Host smart-ae62d8ba-6ce0-47e3-ac65-4e9ab30fc7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303999780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1303999780
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3201898427
Short name T624
Test name
Test status
Simulation time 209595733 ps
CPU time 2.81 seconds
Started Aug 17 06:31:08 PM PDT 24
Finished Aug 17 06:31:11 PM PDT 24
Peak memory 219456 kb
Host smart-df33e2fa-9980-4132-8fda-873ab33beda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201898427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3201898427
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3694112064
Short name T975
Test name
Test status
Simulation time 38451654 ps
CPU time 1.17 seconds
Started Aug 17 06:31:21 PM PDT 24
Finished Aug 17 06:31:22 PM PDT 24
Peak memory 218640 kb
Host smart-dbebd8a3-8360-456c-aba7-e9f0b6e878cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694112064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3694112064
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3645824365
Short name T727
Test name
Test status
Simulation time 48123314 ps
CPU time 1.13 seconds
Started Aug 17 06:31:36 PM PDT 24
Finished Aug 17 06:31:37 PM PDT 24
Peak memory 218660 kb
Host smart-c1bbd507-c4ae-4312-b9a4-95b5716d6862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645824365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3645824365
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1787058694
Short name T408
Test name
Test status
Simulation time 103164820 ps
CPU time 2.21 seconds
Started Aug 17 06:31:18 PM PDT 24
Finished Aug 17 06:31:20 PM PDT 24
Peak memory 217544 kb
Host smart-6b297326-2132-46e5-a8b7-7be401932685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787058694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1787058694
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.533514346
Short name T493
Test name
Test status
Simulation time 101120116 ps
CPU time 1.14 seconds
Started Aug 17 06:31:22 PM PDT 24
Finished Aug 17 06:31:24 PM PDT 24
Peak memory 217384 kb
Host smart-c1102308-4ad4-4756-98b3-a11706d49d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533514346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.533514346
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.4227663072
Short name T404
Test name
Test status
Simulation time 80459642 ps
CPU time 1.33 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:25 PM PDT 24
Peak memory 220524 kb
Host smart-d776ae40-4ab1-4497-b4ad-8b16c8059eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227663072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4227663072
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1238969713
Short name T736
Test name
Test status
Simulation time 50465210 ps
CPU time 1.16 seconds
Started Aug 17 06:29:46 PM PDT 24
Finished Aug 17 06:29:47 PM PDT 24
Peak memory 219880 kb
Host smart-a8b8802b-6b9f-44e9-a540-b9c5a2f83b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238969713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1238969713
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1551827657
Short name T324
Test name
Test status
Simulation time 29202665 ps
CPU time 0.94 seconds
Started Aug 17 06:30:06 PM PDT 24
Finished Aug 17 06:30:07 PM PDT 24
Peak memory 206796 kb
Host smart-e46ab436-ae08-4023-99be-3cbb1d162219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551827657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1551827657
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2975559825
Short name T609
Test name
Test status
Simulation time 55427514 ps
CPU time 0.85 seconds
Started Aug 17 06:29:40 PM PDT 24
Finished Aug 17 06:29:41 PM PDT 24
Peak memory 215444 kb
Host smart-192198b9-f1b6-4d77-9c69-31a39f251daa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975559825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2975559825
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1286404591
Short name T121
Test name
Test status
Simulation time 54606594 ps
CPU time 1.21 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 216792 kb
Host smart-a1968fbc-6fc2-4cc1-8550-315a40cc6680
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286404591 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1286404591
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1551329345
Short name T199
Test name
Test status
Simulation time 27299703 ps
CPU time 0.88 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 218628 kb
Host smart-702e91c7-f8e5-4210-a308-205ec5225a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551329345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1551329345
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3938502499
Short name T676
Test name
Test status
Simulation time 44022871 ps
CPU time 1.09 seconds
Started Aug 17 06:29:40 PM PDT 24
Finished Aug 17 06:29:41 PM PDT 24
Peak memory 217368 kb
Host smart-598ee92b-833b-4d37-ad50-bf8a1e4089dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938502499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3938502499
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2684796938
Short name T732
Test name
Test status
Simulation time 76627239 ps
CPU time 0.92 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 223660 kb
Host smart-b33385fc-a66d-4b80-b72b-a0d4a6143f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684796938 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2684796938
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2109702106
Short name T490
Test name
Test status
Simulation time 38571291 ps
CPU time 0.91 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 207080 kb
Host smart-f9b2dda0-8eff-437e-b4ed-a5c682432780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109702106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2109702106
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.618137457
Short name T765
Test name
Test status
Simulation time 116234364 ps
CPU time 2.79 seconds
Started Aug 17 06:30:12 PM PDT 24
Finished Aug 17 06:30:15 PM PDT 24
Peak memory 215384 kb
Host smart-091c1b5a-27a7-4e86-98ec-36bcba44d6d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618137457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.618137457
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/220.edn_genbits.385053717
Short name T385
Test name
Test status
Simulation time 42100043 ps
CPU time 1.47 seconds
Started Aug 17 06:31:17 PM PDT 24
Finished Aug 17 06:31:19 PM PDT 24
Peak memory 218468 kb
Host smart-a12bd8aa-18a3-429c-95a1-46ec488e9030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385053717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.385053717
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3256209653
Short name T788
Test name
Test status
Simulation time 39558224 ps
CPU time 1.14 seconds
Started Aug 17 06:31:22 PM PDT 24
Finished Aug 17 06:31:24 PM PDT 24
Peak memory 217276 kb
Host smart-3465ba7b-6a04-41a2-bce9-3379e2db014d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256209653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3256209653
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1189323772
Short name T483
Test name
Test status
Simulation time 54627888 ps
CPU time 1.84 seconds
Started Aug 17 06:31:24 PM PDT 24
Finished Aug 17 06:31:27 PM PDT 24
Peak memory 220680 kb
Host smart-a0ff4fd2-5966-4889-b215-a2800f7fb5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189323772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1189323772
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3802646832
Short name T956
Test name
Test status
Simulation time 38077090 ps
CPU time 1.48 seconds
Started Aug 17 06:31:10 PM PDT 24
Finished Aug 17 06:31:12 PM PDT 24
Peak memory 219888 kb
Host smart-cadec659-0b9b-4c5d-8821-34441e41f9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802646832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3802646832
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3314681000
Short name T639
Test name
Test status
Simulation time 36259070 ps
CPU time 1.51 seconds
Started Aug 17 06:31:08 PM PDT 24
Finished Aug 17 06:31:10 PM PDT 24
Peak memory 218552 kb
Host smart-62d2b34d-d66a-4529-86b1-8c428d2f25bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314681000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3314681000
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1426152157
Short name T307
Test name
Test status
Simulation time 27287685 ps
CPU time 1.18 seconds
Started Aug 17 06:31:21 PM PDT 24
Finished Aug 17 06:31:22 PM PDT 24
Peak memory 219448 kb
Host smart-2e3a2c63-2f62-445b-a47a-4c0401e13dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426152157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1426152157
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.475764380
Short name T602
Test name
Test status
Simulation time 48856601 ps
CPU time 1.61 seconds
Started Aug 17 06:31:01 PM PDT 24
Finished Aug 17 06:31:02 PM PDT 24
Peak memory 218592 kb
Host smart-631b7ef0-5323-4da4-abb7-ea2d70b1363a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475764380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.475764380
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.880953876
Short name T615
Test name
Test status
Simulation time 36046048 ps
CPU time 1.12 seconds
Started Aug 17 06:31:13 PM PDT 24
Finished Aug 17 06:31:14 PM PDT 24
Peak memory 218512 kb
Host smart-7cc91614-bf7c-425c-b037-74cae90103e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880953876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.880953876
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1645310085
Short name T550
Test name
Test status
Simulation time 42706328 ps
CPU time 1.41 seconds
Started Aug 17 06:31:27 PM PDT 24
Finished Aug 17 06:31:29 PM PDT 24
Peak memory 215300 kb
Host smart-100c940a-4452-4e92-acc2-724e6dff7817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645310085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1645310085
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3174420464
Short name T761
Test name
Test status
Simulation time 43548521 ps
CPU time 1.5 seconds
Started Aug 17 06:31:22 PM PDT 24
Finished Aug 17 06:31:24 PM PDT 24
Peak memory 218632 kb
Host smart-f87cb032-7895-4745-b8fe-ded2d0045d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174420464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3174420464
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1388982693
Short name T495
Test name
Test status
Simulation time 182212958 ps
CPU time 1.22 seconds
Started Aug 17 06:29:43 PM PDT 24
Finished Aug 17 06:29:45 PM PDT 24
Peak memory 219652 kb
Host smart-897749f6-e638-4481-a06b-3465651ec4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388982693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1388982693
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.228606336
Short name T954
Test name
Test status
Simulation time 171297999 ps
CPU time 0.88 seconds
Started Aug 17 06:29:43 PM PDT 24
Finished Aug 17 06:29:44 PM PDT 24
Peak memory 214932 kb
Host smart-af644c63-b3de-4c3a-82e8-69e775da0260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228606336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.228606336
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3561146909
Short name T888
Test name
Test status
Simulation time 14418035 ps
CPU time 0.86 seconds
Started Aug 17 06:29:40 PM PDT 24
Finished Aug 17 06:29:41 PM PDT 24
Peak memory 207248 kb
Host smart-a63273be-6a81-45e2-b562-d17482979da4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561146909 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3561146909
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3718178534
Short name T649
Test name
Test status
Simulation time 51843121 ps
CPU time 1.56 seconds
Started Aug 17 06:29:51 PM PDT 24
Finished Aug 17 06:29:53 PM PDT 24
Peak memory 219088 kb
Host smart-74a3ba10-555b-4407-8513-ca12eae0fc4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718178534 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3718178534
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.179382608
Short name T942
Test name
Test status
Simulation time 95334330 ps
CPU time 0.98 seconds
Started Aug 17 06:29:36 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 223884 kb
Host smart-3f5ce24c-f49f-41c8-b534-a9be4c67fda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179382608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.179382608
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.722024166
Short name T672
Test name
Test status
Simulation time 71792999 ps
CPU time 1.13 seconds
Started Aug 17 06:29:47 PM PDT 24
Finished Aug 17 06:29:48 PM PDT 24
Peak memory 219100 kb
Host smart-ef4639f3-59ba-465e-876a-181019477dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722024166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.722024166
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.3213436498
Short name T666
Test name
Test status
Simulation time 18870335 ps
CPU time 1 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 215364 kb
Host smart-91f3d803-186b-4104-ab8d-ea60b9fd65dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213436498 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3213436498
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3342541594
Short name T391
Test name
Test status
Simulation time 202649823 ps
CPU time 2.37 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:41 PM PDT 24
Peak memory 217184 kb
Host smart-2bbaa1f3-fb2f-4f58-8aa8-cf97b003f8fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342541594 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3342541594
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2160152861
Short name T592
Test name
Test status
Simulation time 1288586874 ps
CPU time 38.14 seconds
Started Aug 17 06:29:42 PM PDT 24
Finished Aug 17 06:30:20 PM PDT 24
Peak memory 217952 kb
Host smart-68171d5f-e5b3-40d8-904b-dc60e7873a6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160152861 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2160152861
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2780857249
Short name T791
Test name
Test status
Simulation time 50474888 ps
CPU time 1.74 seconds
Started Aug 17 06:31:18 PM PDT 24
Finished Aug 17 06:31:20 PM PDT 24
Peak memory 218656 kb
Host smart-0ca0a035-8bde-49c9-a4e5-7a2de9ee160d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780857249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2780857249
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2234739198
Short name T786
Test name
Test status
Simulation time 132908056 ps
CPU time 2.72 seconds
Started Aug 17 06:31:01 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 218688 kb
Host smart-a559d987-b156-4f7b-8c75-30428c8db734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234739198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2234739198
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3653855277
Short name T576
Test name
Test status
Simulation time 33611916 ps
CPU time 1.6 seconds
Started Aug 17 06:31:17 PM PDT 24
Finished Aug 17 06:31:18 PM PDT 24
Peak memory 218784 kb
Host smart-d0ea1afd-161b-41aa-97a3-fb37d3b671b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653855277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3653855277
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2032717783
Short name T606
Test name
Test status
Simulation time 74708911 ps
CPU time 1.52 seconds
Started Aug 17 06:31:26 PM PDT 24
Finished Aug 17 06:31:29 PM PDT 24
Peak memory 218788 kb
Host smart-79837a3a-4327-4df1-a7ec-ece11f8d64a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032717783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2032717783
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.914423294
Short name T372
Test name
Test status
Simulation time 39129447 ps
CPU time 1.15 seconds
Started Aug 17 06:31:14 PM PDT 24
Finished Aug 17 06:31:15 PM PDT 24
Peak memory 218816 kb
Host smart-bda170a3-2962-4f67-85d1-34eaaba48b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914423294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.914423294
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.425679044
Short name T871
Test name
Test status
Simulation time 88251790 ps
CPU time 1.09 seconds
Started Aug 17 06:31:20 PM PDT 24
Finished Aug 17 06:31:21 PM PDT 24
Peak memory 218364 kb
Host smart-261b6c92-5654-4012-a6ed-1c548a8b05f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425679044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.425679044
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3612772911
Short name T679
Test name
Test status
Simulation time 54111377 ps
CPU time 1.26 seconds
Started Aug 17 06:31:26 PM PDT 24
Finished Aug 17 06:31:28 PM PDT 24
Peak memory 218576 kb
Host smart-8b6c2e42-ebf3-4f97-822d-c7e16e093df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612772911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3612772911
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3680889484
Short name T675
Test name
Test status
Simulation time 90667432 ps
CPU time 3.04 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:27 PM PDT 24
Peak memory 220608 kb
Host smart-665a92b1-def3-483a-81d6-7860d7809cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680889484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3680889484
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2601850073
Short name T503
Test name
Test status
Simulation time 39677070 ps
CPU time 1.64 seconds
Started Aug 17 06:31:46 PM PDT 24
Finished Aug 17 06:31:47 PM PDT 24
Peak memory 218460 kb
Host smart-397efed6-300c-4b29-b81f-41dc3c5614d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601850073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2601850073
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.388604474
Short name T685
Test name
Test status
Simulation time 181401931 ps
CPU time 1.44 seconds
Started Aug 17 06:31:20 PM PDT 24
Finished Aug 17 06:31:21 PM PDT 24
Peak memory 219352 kb
Host smart-fec4668b-7e0d-46e7-84eb-40a5c1358797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388604474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.388604474
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4239349914
Short name T970
Test name
Test status
Simulation time 53386205 ps
CPU time 1.25 seconds
Started Aug 17 06:30:06 PM PDT 24
Finished Aug 17 06:30:08 PM PDT 24
Peak memory 218676 kb
Host smart-dd548015-31f9-4102-9a57-c61647a29d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239349914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4239349914
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3897831370
Short name T443
Test name
Test status
Simulation time 16542868 ps
CPU time 0.9 seconds
Started Aug 17 06:29:44 PM PDT 24
Finished Aug 17 06:29:45 PM PDT 24
Peak memory 214904 kb
Host smart-a89d7b6e-67d8-469f-910c-37f9681862a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897831370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3897831370
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.932725840
Short name T930
Test name
Test status
Simulation time 40911190 ps
CPU time 0.86 seconds
Started Aug 17 06:29:43 PM PDT 24
Finished Aug 17 06:29:44 PM PDT 24
Peak memory 207232 kb
Host smart-25180c7a-448c-42d4-b779-44d18ea0b591
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932725840 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.932725840
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.389646742
Short name T805
Test name
Test status
Simulation time 32069420 ps
CPU time 1.04 seconds
Started Aug 17 06:30:10 PM PDT 24
Finished Aug 17 06:30:11 PM PDT 24
Peak memory 216968 kb
Host smart-9457c984-78da-44d5-bf67-07a745398d3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389646742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.389646742
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.437632265
Short name T611
Test name
Test status
Simulation time 38728569 ps
CPU time 0.92 seconds
Started Aug 17 06:29:52 PM PDT 24
Finished Aug 17 06:29:53 PM PDT 24
Peak memory 218308 kb
Host smart-ac024364-60ad-4547-b15f-d98fe824293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437632265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.437632265
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2943818139
Short name T291
Test name
Test status
Simulation time 44536189 ps
CPU time 1.25 seconds
Started Aug 17 06:29:42 PM PDT 24
Finished Aug 17 06:29:43 PM PDT 24
Peak memory 218736 kb
Host smart-76ab71ba-52dc-418e-8ebd-c77a8213b5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943818139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2943818139
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.43549646
Short name T895
Test name
Test status
Simulation time 24490496 ps
CPU time 0.97 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 216056 kb
Host smart-1fc5eccd-10fc-415c-92fe-fa1705d47de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43549646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.43549646
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4067062519
Short name T845
Test name
Test status
Simulation time 29346621 ps
CPU time 0.89 seconds
Started Aug 17 06:29:40 PM PDT 24
Finished Aug 17 06:29:41 PM PDT 24
Peak memory 215272 kb
Host smart-86886d4a-7f63-4e63-9367-6f5d3f5e848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067062519 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4067062519
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/240.edn_genbits.3746489244
Short name T742
Test name
Test status
Simulation time 64904423 ps
CPU time 1.57 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:24 PM PDT 24
Peak memory 218588 kb
Host smart-9ec73079-57b7-4b8c-ae6f-bb2b5cbfe3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746489244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3746489244
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.589470024
Short name T759
Test name
Test status
Simulation time 89417561 ps
CPU time 1.5 seconds
Started Aug 17 06:31:39 PM PDT 24
Finished Aug 17 06:31:40 PM PDT 24
Peak memory 219136 kb
Host smart-e41cfa70-df3e-4008-9a30-47f601115545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589470024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.589470024
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2637874812
Short name T397
Test name
Test status
Simulation time 127501922 ps
CPU time 1.62 seconds
Started Aug 17 06:31:32 PM PDT 24
Finished Aug 17 06:31:34 PM PDT 24
Peak memory 218920 kb
Host smart-485a2e46-0f15-407a-a4a1-b273151476cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637874812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2637874812
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2999564402
Short name T581
Test name
Test status
Simulation time 41708719 ps
CPU time 1.31 seconds
Started Aug 17 06:31:25 PM PDT 24
Finished Aug 17 06:31:28 PM PDT 24
Peak memory 217292 kb
Host smart-517de935-c4d7-4920-b1f4-9f3f153f8b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999564402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2999564402
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.687345868
Short name T332
Test name
Test status
Simulation time 76008381 ps
CPU time 1.16 seconds
Started Aug 17 06:31:15 PM PDT 24
Finished Aug 17 06:31:17 PM PDT 24
Peak memory 220316 kb
Host smart-9a52f01f-2f1a-491b-899a-7d2608fe09fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687345868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.687345868
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2426199036
Short name T44
Test name
Test status
Simulation time 65797985 ps
CPU time 1.42 seconds
Started Aug 17 06:31:03 PM PDT 24
Finished Aug 17 06:31:05 PM PDT 24
Peak memory 218556 kb
Host smart-bce1fe4c-9175-4060-b3ae-3081b780d22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426199036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2426199036
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1756822993
Short name T451
Test name
Test status
Simulation time 42978187 ps
CPU time 1.61 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:26 PM PDT 24
Peak memory 218348 kb
Host smart-1bb765bf-9a3e-4e90-b3cb-c3d661950722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756822993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1756822993
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.269406856
Short name T671
Test name
Test status
Simulation time 44722434 ps
CPU time 1.41 seconds
Started Aug 17 06:31:26 PM PDT 24
Finished Aug 17 06:31:29 PM PDT 24
Peak memory 219772 kb
Host smart-aa13b673-805d-42bd-b133-2e3b7cec3917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269406856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.269406856
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3790160862
Short name T299
Test name
Test status
Simulation time 34861226 ps
CPU time 1.37 seconds
Started Aug 17 06:31:28 PM PDT 24
Finished Aug 17 06:31:30 PM PDT 24
Peak memory 218556 kb
Host smart-7e32a432-ada9-401e-82cd-d5ca97f22153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790160862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3790160862
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1134571390
Short name T855
Test name
Test status
Simulation time 89151614 ps
CPU time 1.21 seconds
Started Aug 17 06:29:46 PM PDT 24
Finished Aug 17 06:29:47 PM PDT 24
Peak memory 218600 kb
Host smart-8d9c4ac8-c2e9-460b-b0f3-88d39f8866f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134571390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1134571390
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1195268906
Short name T864
Test name
Test status
Simulation time 48565381 ps
CPU time 0.9 seconds
Started Aug 17 06:29:51 PM PDT 24
Finished Aug 17 06:29:52 PM PDT 24
Peak memory 206696 kb
Host smart-e2a4b833-f8d5-40d2-a80e-52769a6cd628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195268906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1195268906
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2602413721
Short name T668
Test name
Test status
Simulation time 10997953 ps
CPU time 0.83 seconds
Started Aug 17 06:30:21 PM PDT 24
Finished Aug 17 06:30:27 PM PDT 24
Peak memory 215360 kb
Host smart-8d5ddb4b-0e4c-4050-870a-56355baa1fe2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602413721 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2602413721
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3786238994
Short name T612
Test name
Test status
Simulation time 109451023 ps
CPU time 1.06 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:44 PM PDT 24
Peak memory 216920 kb
Host smart-e81921bf-6ef4-4342-b72a-2998d8c2181b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786238994 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3786238994
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.4140544494
Short name T681
Test name
Test status
Simulation time 80442002 ps
CPU time 0.83 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 218224 kb
Host smart-a181d3c6-8e59-4122-9b58-09c81999a63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140544494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.4140544494
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1401099625
Short name T801
Test name
Test status
Simulation time 43771150 ps
CPU time 1.11 seconds
Started Aug 17 06:29:40 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 217480 kb
Host smart-87d1efe4-9f04-4cc3-b156-1dd311bead8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401099625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1401099625
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1294005751
Short name T85
Test name
Test status
Simulation time 39607619 ps
CPU time 0.86 seconds
Started Aug 17 06:30:13 PM PDT 24
Finished Aug 17 06:30:14 PM PDT 24
Peak memory 215600 kb
Host smart-ca6f2a82-6519-4715-9e53-5fb422321e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294005751 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1294005751
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.852207325
Short name T334
Test name
Test status
Simulation time 25652381 ps
CPU time 0.93 seconds
Started Aug 17 06:29:50 PM PDT 24
Finished Aug 17 06:29:51 PM PDT 24
Peak memory 207160 kb
Host smart-9b41cd16-d51f-4619-815e-2112a202fb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852207325 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.852207325
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2940312991
Short name T699
Test name
Test status
Simulation time 590816548 ps
CPU time 6.23 seconds
Started Aug 17 06:29:43 PM PDT 24
Finished Aug 17 06:29:49 PM PDT 24
Peak memory 217336 kb
Host smart-b72eb210-83fc-48e0-be59-840c71dd12e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940312991 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2940312991
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3634315288
Short name T465
Test name
Test status
Simulation time 30535121313 ps
CPU time 96.14 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:31:11 PM PDT 24
Peak memory 219856 kb
Host smart-6d30126f-6350-4fa1-8652-e9f8c9fa5b0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634315288 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3634315288
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3712786856
Short name T913
Test name
Test status
Simulation time 46945165 ps
CPU time 1.37 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:24 PM PDT 24
Peak memory 217072 kb
Host smart-715fe6b7-85bb-4043-82a6-a60cdc5076ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712786856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3712786856
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.500886397
Short name T629
Test name
Test status
Simulation time 106528821 ps
CPU time 1.54 seconds
Started Aug 17 06:31:21 PM PDT 24
Finished Aug 17 06:31:22 PM PDT 24
Peak memory 218824 kb
Host smart-f76034dc-726e-4a7f-9231-dfb62d6ff4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500886397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.500886397
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2610525071
Short name T466
Test name
Test status
Simulation time 45134611 ps
CPU time 1.64 seconds
Started Aug 17 06:31:26 PM PDT 24
Finished Aug 17 06:31:29 PM PDT 24
Peak memory 218592 kb
Host smart-d141cbea-cad2-4bc4-821b-9b294cdf7f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610525071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2610525071
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3154735429
Short name T241
Test name
Test status
Simulation time 34026542 ps
CPU time 1.11 seconds
Started Aug 17 06:31:12 PM PDT 24
Finished Aug 17 06:31:13 PM PDT 24
Peak memory 217420 kb
Host smart-52a7dd08-0de2-4d84-8a79-fa2e55491c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154735429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3154735429
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2624674217
Short name T325
Test name
Test status
Simulation time 30346795 ps
CPU time 1.2 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:26 PM PDT 24
Peak memory 217376 kb
Host smart-b76f16bb-4d1a-44a7-8ae3-dd638feb9642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624674217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2624674217
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2200731510
Short name T538
Test name
Test status
Simulation time 33625613 ps
CPU time 1.45 seconds
Started Aug 17 06:31:24 PM PDT 24
Finished Aug 17 06:31:28 PM PDT 24
Peak memory 218536 kb
Host smart-b6ab3dd6-d8fb-4c27-a8c2-8c4096283680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200731510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2200731510
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1694366075
Short name T766
Test name
Test status
Simulation time 71120907 ps
CPU time 1.07 seconds
Started Aug 17 06:31:19 PM PDT 24
Finished Aug 17 06:31:20 PM PDT 24
Peak memory 220228 kb
Host smart-961ed77a-ccf3-42ea-8c32-a8ba3542ed10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694366075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1694366075
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2989588005
Short name T837
Test name
Test status
Simulation time 48051594 ps
CPU time 1.34 seconds
Started Aug 17 06:31:21 PM PDT 24
Finished Aug 17 06:31:23 PM PDT 24
Peak memory 218848 kb
Host smart-aba6c50a-e6af-49fb-9f35-b1d83f7984e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989588005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2989588005
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.116930472
Short name T583
Test name
Test status
Simulation time 243104984 ps
CPU time 1.26 seconds
Started Aug 17 06:31:35 PM PDT 24
Finished Aug 17 06:31:37 PM PDT 24
Peak memory 217464 kb
Host smart-59da64d1-99bc-4b19-8526-baed146f30f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116930472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.116930472
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.52936389
Short name T726
Test name
Test status
Simulation time 90022834 ps
CPU time 1.31 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:25 PM PDT 24
Peak memory 220148 kb
Host smart-32070516-b682-4cc0-9c2e-0600bbbfcbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52936389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.52936389
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.218959856
Short name T697
Test name
Test status
Simulation time 165582574 ps
CPU time 1.2 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 215792 kb
Host smart-fdc6347a-0ef1-4c0b-872f-e6da5961e3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218959856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.218959856
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1823698829
Short name T338
Test name
Test status
Simulation time 58357347 ps
CPU time 0.94 seconds
Started Aug 17 06:29:45 PM PDT 24
Finished Aug 17 06:29:46 PM PDT 24
Peak memory 206804 kb
Host smart-2281909d-616c-419f-8dba-67ab167de7b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823698829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1823698829
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.327320165
Short name T196
Test name
Test status
Simulation time 37393543 ps
CPU time 0.85 seconds
Started Aug 17 06:29:44 PM PDT 24
Finished Aug 17 06:29:44 PM PDT 24
Peak memory 215440 kb
Host smart-2c9c2b4b-f929-4a87-a638-885ab0fe2354
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327320165 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.327320165
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.560793430
Short name T141
Test name
Test status
Simulation time 71321591 ps
CPU time 1.3 seconds
Started Aug 17 06:29:48 PM PDT 24
Finished Aug 17 06:29:50 PM PDT 24
Peak memory 217048 kb
Host smart-625765eb-2d70-4e51-ab5f-80704721e43f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560793430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.560793430
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.947784012
Short name T873
Test name
Test status
Simulation time 48027767 ps
CPU time 1.21 seconds
Started Aug 17 06:30:01 PM PDT 24
Finished Aug 17 06:30:03 PM PDT 24
Peak memory 225728 kb
Host smart-4b1821f1-e5b8-419b-a625-5725861626ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947784012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.947784012
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.4151650012
Short name T479
Test name
Test status
Simulation time 27342425 ps
CPU time 1.18 seconds
Started Aug 17 06:30:00 PM PDT 24
Finished Aug 17 06:30:02 PM PDT 24
Peak memory 218392 kb
Host smart-56853ab8-3473-49c6-8f04-afa6df504995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151650012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.4151650012
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2381074234
Short name T354
Test name
Test status
Simulation time 26034968 ps
CPU time 0.94 seconds
Started Aug 17 06:29:48 PM PDT 24
Finished Aug 17 06:29:49 PM PDT 24
Peak memory 215464 kb
Host smart-532f6d7c-665a-4860-9d6c-1258964158b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381074234 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2381074234
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3878738832
Short name T814
Test name
Test status
Simulation time 104098898 ps
CPU time 0.89 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 215344 kb
Host smart-c5b8f153-8ef8-4ddd-a669-622b570f874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878738832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3878738832
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3603786106
Short name T363
Test name
Test status
Simulation time 304580411 ps
CPU time 6.25 seconds
Started Aug 17 06:30:15 PM PDT 24
Finished Aug 17 06:30:21 PM PDT 24
Peak memory 215328 kb
Host smart-c01ece22-bd4a-4b98-a23c-9939a6090791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603786106 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3603786106
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/260.edn_genbits.413848647
Short name T843
Test name
Test status
Simulation time 38632788 ps
CPU time 1.16 seconds
Started Aug 17 06:31:17 PM PDT 24
Finished Aug 17 06:31:19 PM PDT 24
Peak memory 219284 kb
Host smart-5bca2f2e-d1fc-4f48-8b62-f494c7ebb94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413848647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.413848647
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.4265065794
Short name T703
Test name
Test status
Simulation time 64635114 ps
CPU time 1.17 seconds
Started Aug 17 06:31:21 PM PDT 24
Finished Aug 17 06:31:22 PM PDT 24
Peak memory 217496 kb
Host smart-306b7fe2-2fff-4bef-82ef-d581f3c3c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265065794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.4265065794
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3888199332
Short name T105
Test name
Test status
Simulation time 131137675 ps
CPU time 1.54 seconds
Started Aug 17 06:31:12 PM PDT 24
Finished Aug 17 06:31:13 PM PDT 24
Peak memory 219200 kb
Host smart-9384fd28-ee76-4a0c-b614-b58cd7649ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888199332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3888199332
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1094722935
Short name T661
Test name
Test status
Simulation time 127260726 ps
CPU time 2.87 seconds
Started Aug 17 06:31:19 PM PDT 24
Finished Aug 17 06:31:22 PM PDT 24
Peak memory 218628 kb
Host smart-c4f918a2-49ec-4d77-becb-bfc396468bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094722935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1094722935
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.4153058391
Short name T906
Test name
Test status
Simulation time 23675892 ps
CPU time 1.18 seconds
Started Aug 17 06:31:14 PM PDT 24
Finished Aug 17 06:31:16 PM PDT 24
Peak memory 219612 kb
Host smart-fe4099df-735f-47a3-b954-ea7f244dc86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153058391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.4153058391
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2039714621
Short name T897
Test name
Test status
Simulation time 58855828 ps
CPU time 1.15 seconds
Started Aug 17 06:31:39 PM PDT 24
Finished Aug 17 06:31:41 PM PDT 24
Peak memory 215364 kb
Host smart-cbb8ab8c-e2d0-459b-a572-f406b72b8edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039714621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2039714621
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3810311557
Short name T436
Test name
Test status
Simulation time 193549180 ps
CPU time 1.09 seconds
Started Aug 17 06:31:19 PM PDT 24
Finished Aug 17 06:31:21 PM PDT 24
Peak memory 217432 kb
Host smart-adc29e4d-ef0b-40f0-9640-9825bd7542b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810311557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3810311557
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.805116094
Short name T444
Test name
Test status
Simulation time 202646101 ps
CPU time 3.54 seconds
Started Aug 17 06:31:18 PM PDT 24
Finished Aug 17 06:31:21 PM PDT 24
Peak memory 218656 kb
Host smart-0664c08c-cda7-4179-8fcc-e8149f9fd53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805116094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.805116094
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1331719425
Short name T920
Test name
Test status
Simulation time 67784454 ps
CPU time 1.14 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:26 PM PDT 24
Peak memory 220420 kb
Host smart-ff7f79ca-dc4f-4197-ab3c-367eb6ab3489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331719425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1331719425
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3508748615
Short name T597
Test name
Test status
Simulation time 102029972 ps
CPU time 1.06 seconds
Started Aug 17 06:31:31 PM PDT 24
Finished Aug 17 06:31:32 PM PDT 24
Peak memory 218584 kb
Host smart-10d69b02-5dd9-4ee1-ad55-7bc2f4adacb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508748615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3508748615
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1341716764
Short name T448
Test name
Test status
Simulation time 33305373 ps
CPU time 1.16 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 220240 kb
Host smart-4354aa33-d60a-4803-ba6d-93552106236d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341716764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1341716764
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.785460757
Short name T659
Test name
Test status
Simulation time 30412612 ps
CPU time 1.01 seconds
Started Aug 17 06:30:14 PM PDT 24
Finished Aug 17 06:30:15 PM PDT 24
Peak memory 214960 kb
Host smart-94e40c48-6605-4a84-9037-1e0406612551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785460757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.785460757
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2566007524
Short name T891
Test name
Test status
Simulation time 14945744 ps
CPU time 0.92 seconds
Started Aug 17 06:29:51 PM PDT 24
Finished Aug 17 06:29:52 PM PDT 24
Peak memory 207408 kb
Host smart-aedae21e-45f8-4375-8b93-c0eec7800383
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566007524 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2566007524
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1466862877
Short name T274
Test name
Test status
Simulation time 36515628 ps
CPU time 1.29 seconds
Started Aug 17 06:29:54 PM PDT 24
Finished Aug 17 06:29:55 PM PDT 24
Peak memory 217012 kb
Host smart-cff9f5f3-b392-40c3-8d42-0192a5420c89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466862877 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1466862877
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1178389210
Short name T144
Test name
Test status
Simulation time 44402716 ps
CPU time 1.03 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 229828 kb
Host smart-8f77347a-368b-42e5-8007-3bb9fed6e3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178389210 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1178389210
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.675702581
Short name T547
Test name
Test status
Simulation time 93711260 ps
CPU time 1.15 seconds
Started Aug 17 06:30:00 PM PDT 24
Finished Aug 17 06:30:02 PM PDT 24
Peak memory 217364 kb
Host smart-2b2e7038-81a8-4454-a5d9-44d130170495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675702581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.675702581
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.770705934
Short name T832
Test name
Test status
Simulation time 43448171 ps
CPU time 0.99 seconds
Started Aug 17 06:29:52 PM PDT 24
Finished Aug 17 06:29:53 PM PDT 24
Peak memory 224088 kb
Host smart-148d8890-c93e-4fe2-9ab6-caea4379bce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770705934 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.770705934
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.944578388
Short name T457
Test name
Test status
Simulation time 76022449 ps
CPU time 0.97 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 215380 kb
Host smart-038ba196-9a26-4e8f-a19a-bea6280e28d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944578388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.944578388
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2190243742
Short name T914
Test name
Test status
Simulation time 398819275 ps
CPU time 7.27 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:45 PM PDT 24
Peak memory 217144 kb
Host smart-a42a7b57-75d2-4457-b774-5b46648d6c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190243742 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2190243742
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/270.edn_genbits.2052005802
Short name T293
Test name
Test status
Simulation time 53963715 ps
CPU time 1.61 seconds
Started Aug 17 06:31:26 PM PDT 24
Finished Aug 17 06:31:29 PM PDT 24
Peak memory 218800 kb
Host smart-cf9c9788-5c6f-47b5-a301-551bc06395cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052005802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2052005802
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1932054047
Short name T594
Test name
Test status
Simulation time 29409648 ps
CPU time 1.07 seconds
Started Aug 17 06:31:21 PM PDT 24
Finished Aug 17 06:31:22 PM PDT 24
Peak memory 217240 kb
Host smart-fe1b8520-31d6-42fc-9096-95d90c9107f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932054047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1932054047
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1259115360
Short name T415
Test name
Test status
Simulation time 48267014 ps
CPU time 1.67 seconds
Started Aug 17 06:31:25 PM PDT 24
Finished Aug 17 06:31:28 PM PDT 24
Peak memory 218484 kb
Host smart-9122f40e-f0a3-4fe6-b072-64de70342b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259115360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1259115360
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3797119108
Short name T521
Test name
Test status
Simulation time 43515974 ps
CPU time 1.16 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:26 PM PDT 24
Peak memory 218876 kb
Host smart-5a24ae1a-7401-4323-9c00-61d1d782a40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797119108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3797119108
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2145023349
Short name T929
Test name
Test status
Simulation time 76998549 ps
CPU time 2.59 seconds
Started Aug 17 06:31:21 PM PDT 24
Finished Aug 17 06:31:23 PM PDT 24
Peak memory 219228 kb
Host smart-95c454b4-7273-449d-8b65-e7c6f6c0427d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145023349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2145023349
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2985564513
Short name T452
Test name
Test status
Simulation time 89107200 ps
CPU time 1.94 seconds
Started Aug 17 06:31:26 PM PDT 24
Finished Aug 17 06:31:29 PM PDT 24
Peak memory 220448 kb
Host smart-d876fc56-0b56-4760-9d2f-80f04d715235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985564513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2985564513
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3565110611
Short name T510
Test name
Test status
Simulation time 34733883 ps
CPU time 1.06 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:26 PM PDT 24
Peak memory 217320 kb
Host smart-4819d19e-b179-4c23-a220-6ce2b5c55e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565110611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3565110611
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2375867358
Short name T369
Test name
Test status
Simulation time 69681686 ps
CPU time 1.31 seconds
Started Aug 17 06:31:24 PM PDT 24
Finished Aug 17 06:31:28 PM PDT 24
Peak memory 218608 kb
Host smart-744d476e-e727-4694-9a5b-b04ddacf655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375867358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2375867358
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3855640272
Short name T966
Test name
Test status
Simulation time 76661212 ps
CPU time 1.64 seconds
Started Aug 17 06:31:24 PM PDT 24
Finished Aug 17 06:31:27 PM PDT 24
Peak memory 217656 kb
Host smart-e9261809-9385-42df-8fef-fceebfe821b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855640272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3855640272
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.64965377
Short name T471
Test name
Test status
Simulation time 77972638 ps
CPU time 2.23 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:26 PM PDT 24
Peak memory 219648 kb
Host smart-2bbbea7f-e3a5-4d6e-8c18-565d2d926f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64965377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.64965377
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1367162567
Short name T804
Test name
Test status
Simulation time 85935924 ps
CPU time 1.14 seconds
Started Aug 17 06:30:01 PM PDT 24
Finished Aug 17 06:30:03 PM PDT 24
Peak memory 219864 kb
Host smart-3c756522-6d40-465e-87c0-896911ed054a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367162567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1367162567
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.452003904
Short name T665
Test name
Test status
Simulation time 52497448 ps
CPU time 0.9 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 206756 kb
Host smart-c3c41b59-2668-4b39-92b8-0a1640dbd3fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452003904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.452003904
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1846855182
Short name T156
Test name
Test status
Simulation time 117873604 ps
CPU time 0.82 seconds
Started Aug 17 06:30:04 PM PDT 24
Finished Aug 17 06:30:05 PM PDT 24
Peak memory 215444 kb
Host smart-4732f999-762a-46a4-ba39-fc398783c7e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846855182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1846855182
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3605210340
Short name T470
Test name
Test status
Simulation time 101514283 ps
CPU time 1.06 seconds
Started Aug 17 06:29:49 PM PDT 24
Finished Aug 17 06:29:50 PM PDT 24
Peak memory 218700 kb
Host smart-b6b1c95a-9dc9-4cc8-8be7-32c45f221953
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605210340 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3605210340
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3696071157
Short name T110
Test name
Test status
Simulation time 32197616 ps
CPU time 1.16 seconds
Started Aug 17 06:30:08 PM PDT 24
Finished Aug 17 06:30:09 PM PDT 24
Peak memory 219460 kb
Host smart-27103d95-052c-4b4e-803e-dbd26e1a3104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696071157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3696071157
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.80016805
Short name T41
Test name
Test status
Simulation time 51840293 ps
CPU time 1.31 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 217452 kb
Host smart-a20e1c7d-9146-4afa-b5ab-c231c531b9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80016805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.80016805
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3387692664
Short name T429
Test name
Test status
Simulation time 51120489 ps
CPU time 0.89 seconds
Started Aug 17 06:29:55 PM PDT 24
Finished Aug 17 06:29:56 PM PDT 24
Peak memory 215740 kb
Host smart-6754834d-ebbb-4264-a27c-a9424904465a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387692664 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3387692664
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2803623557
Short name T748
Test name
Test status
Simulation time 16245858 ps
CPU time 1.03 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 215340 kb
Host smart-0d7ea7f7-b19f-4977-a76b-fe2b62c6912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803623557 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2803623557
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3056343114
Short name T822
Test name
Test status
Simulation time 127916732 ps
CPU time 1.64 seconds
Started Aug 17 06:29:42 PM PDT 24
Finished Aug 17 06:29:44 PM PDT 24
Peak memory 215432 kb
Host smart-ad73a321-8538-407d-a4dd-d468e6023c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056343114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3056343114
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2763007382
Short name T211
Test name
Test status
Simulation time 14019073199 ps
CPU time 31.13 seconds
Started Aug 17 06:29:52 PM PDT 24
Finished Aug 17 06:30:23 PM PDT 24
Peak memory 218976 kb
Host smart-10fc18ea-89b0-49ee-afc2-d99d8e8260a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763007382 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2763007382
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3626105288
Short name T402
Test name
Test status
Simulation time 37828217 ps
CPU time 1.41 seconds
Started Aug 17 06:31:22 PM PDT 24
Finished Aug 17 06:31:23 PM PDT 24
Peak memory 218632 kb
Host smart-8d974da5-54b5-4a58-90bd-f87a19403b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626105288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3626105288
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1938240529
Short name T322
Test name
Test status
Simulation time 43720826 ps
CPU time 1.14 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:25 PM PDT 24
Peak memory 220236 kb
Host smart-6721e76e-773f-4000-915c-8a0889453113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938240529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1938240529
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.991354090
Short name T887
Test name
Test status
Simulation time 240009488 ps
CPU time 1.67 seconds
Started Aug 17 06:31:16 PM PDT 24
Finished Aug 17 06:31:18 PM PDT 24
Peak memory 220560 kb
Host smart-ae996f9c-50cf-44bf-97ac-6943bf865c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991354090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.991354090
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2232780203
Short name T604
Test name
Test status
Simulation time 91995042 ps
CPU time 1.29 seconds
Started Aug 17 06:31:20 PM PDT 24
Finished Aug 17 06:31:22 PM PDT 24
Peak memory 220320 kb
Host smart-efde54fd-9ddf-4f22-a0dc-b96ab8e67606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232780203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2232780203
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.546252360
Short name T375
Test name
Test status
Simulation time 110478837 ps
CPU time 1.21 seconds
Started Aug 17 06:31:20 PM PDT 24
Finished Aug 17 06:31:21 PM PDT 24
Peak memory 217528 kb
Host smart-081620f7-8033-48bc-804e-1d6f48634e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546252360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.546252360
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2122306407
Short name T949
Test name
Test status
Simulation time 58732025 ps
CPU time 1.34 seconds
Started Aug 17 06:31:22 PM PDT 24
Finished Aug 17 06:31:23 PM PDT 24
Peak memory 218556 kb
Host smart-c2624804-f9ee-4d17-bbc4-d9c481315948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122306407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2122306407
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.364363360
Short name T556
Test name
Test status
Simulation time 46052226 ps
CPU time 1.45 seconds
Started Aug 17 06:31:24 PM PDT 24
Finished Aug 17 06:31:28 PM PDT 24
Peak memory 217456 kb
Host smart-63c7f54f-6207-4fed-a743-84964931587f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364363360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.364363360
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1021114917
Short name T793
Test name
Test status
Simulation time 23320671 ps
CPU time 1.09 seconds
Started Aug 17 06:31:26 PM PDT 24
Finished Aug 17 06:31:29 PM PDT 24
Peak memory 217448 kb
Host smart-1a005045-cc16-48b1-b428-31d1923386e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021114917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1021114917
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.249156113
Short name T406
Test name
Test status
Simulation time 84005733 ps
CPU time 1.18 seconds
Started Aug 17 06:31:26 PM PDT 24
Finished Aug 17 06:31:28 PM PDT 24
Peak memory 217404 kb
Host smart-35469b34-1190-41c9-b6b9-c0fc4a707c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249156113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.249156113
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2343716772
Short name T527
Test name
Test status
Simulation time 50223526 ps
CPU time 1.66 seconds
Started Aug 17 06:31:23 PM PDT 24
Finished Aug 17 06:31:24 PM PDT 24
Peak memory 218668 kb
Host smart-4167f521-e8ed-48a5-b251-7a2ba901e3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343716772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2343716772
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.643652893
Short name T707
Test name
Test status
Simulation time 280927628 ps
CPU time 1.16 seconds
Started Aug 17 06:29:41 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 220916 kb
Host smart-4507ede2-13e2-47ca-9576-742c4e9b70f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643652893 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.643652893
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1991653424
Short name T764
Test name
Test status
Simulation time 13167267 ps
CPU time 0.93 seconds
Started Aug 17 06:30:12 PM PDT 24
Finished Aug 17 06:30:13 PM PDT 24
Peak memory 214948 kb
Host smart-9831a729-9e0b-49b4-8bfb-4996301289f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991653424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1991653424
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3830119712
Short name T154
Test name
Test status
Simulation time 13579227 ps
CPU time 0.91 seconds
Started Aug 17 06:30:01 PM PDT 24
Finished Aug 17 06:30:03 PM PDT 24
Peak memory 215620 kb
Host smart-1e4e2f0b-fb1c-4618-8e51-d663ea4b2b95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830119712 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3830119712
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.4133673415
Short name T596
Test name
Test status
Simulation time 37387998 ps
CPU time 1.2 seconds
Started Aug 17 06:30:17 PM PDT 24
Finished Aug 17 06:30:19 PM PDT 24
Peak memory 216908 kb
Host smart-e41bdcd6-0a22-475a-8128-bb2d604b03c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133673415 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.4133673415
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3550038993
Short name T94
Test name
Test status
Simulation time 24935129 ps
CPU time 0.97 seconds
Started Aug 17 06:29:44 PM PDT 24
Finished Aug 17 06:29:45 PM PDT 24
Peak memory 220040 kb
Host smart-15e4933c-7f97-49b4-b097-6484d39d2a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550038993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3550038993
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3666154849
Short name T474
Test name
Test status
Simulation time 178472021 ps
CPU time 1.44 seconds
Started Aug 17 06:29:55 PM PDT 24
Finished Aug 17 06:29:56 PM PDT 24
Peak memory 220692 kb
Host smart-fc0797f8-9cf9-4380-8464-b4e8e8e58a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666154849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3666154849
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2005632551
Short name T35
Test name
Test status
Simulation time 26178941 ps
CPU time 1.05 seconds
Started Aug 17 06:30:14 PM PDT 24
Finished Aug 17 06:30:15 PM PDT 24
Peak memory 215968 kb
Host smart-cb50bccc-4da9-417e-8fda-54f09023096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005632551 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2005632551
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.948181640
Short name T357
Test name
Test status
Simulation time 19177883 ps
CPU time 0.98 seconds
Started Aug 17 06:29:55 PM PDT 24
Finished Aug 17 06:29:56 PM PDT 24
Peak memory 215328 kb
Host smart-cbdcbc7a-d8aa-4f9b-935a-df77d6b366c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948181640 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.948181640
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3005356224
Short name T648
Test name
Test status
Simulation time 352036952 ps
CPU time 2.15 seconds
Started Aug 17 06:30:08 PM PDT 24
Finished Aug 17 06:30:10 PM PDT 24
Peak memory 217204 kb
Host smart-bddbf5b6-8521-459b-9096-6051c3a6ba45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005356224 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3005356224
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1994031525
Short name T678
Test name
Test status
Simulation time 3741515494 ps
CPU time 101.08 seconds
Started Aug 17 06:30:10 PM PDT 24
Finished Aug 17 06:31:51 PM PDT 24
Peak memory 218788 kb
Host smart-48d73d8d-5eac-4673-b75b-454cc70f4d91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994031525 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1994031525
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.60035547
Short name T568
Test name
Test status
Simulation time 52576891 ps
CPU time 1.2 seconds
Started Aug 17 06:31:25 PM PDT 24
Finished Aug 17 06:31:27 PM PDT 24
Peak memory 219524 kb
Host smart-506a5123-b8ff-45e1-8893-9da40d87d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60035547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.60035547
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3069465358
Short name T636
Test name
Test status
Simulation time 96604303 ps
CPU time 1.6 seconds
Started Aug 17 06:31:22 PM PDT 24
Finished Aug 17 06:31:24 PM PDT 24
Peak memory 219080 kb
Host smart-23fe7224-c98b-4686-8bbf-809de505739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069465358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3069465358
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3749335416
Short name T553
Test name
Test status
Simulation time 45005724 ps
CPU time 1.56 seconds
Started Aug 17 06:31:50 PM PDT 24
Finished Aug 17 06:31:52 PM PDT 24
Peak memory 217428 kb
Host smart-521f11a2-dfa3-4c2a-8b64-7e38c1874044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749335416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3749335416
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2368745559
Short name T646
Test name
Test status
Simulation time 69904669 ps
CPU time 1.15 seconds
Started Aug 17 06:31:17 PM PDT 24
Finished Aug 17 06:31:19 PM PDT 24
Peak memory 217476 kb
Host smart-a159aad6-b762-4a99-bdcf-fda13354d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368745559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2368745559
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.993458819
Short name T19
Test name
Test status
Simulation time 36063322 ps
CPU time 1.19 seconds
Started Aug 17 06:31:19 PM PDT 24
Finished Aug 17 06:31:20 PM PDT 24
Peak memory 220412 kb
Host smart-32320b2b-cdd8-4eab-80cc-8373aa599d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993458819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.993458819
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2898354029
Short name T838
Test name
Test status
Simulation time 230033429 ps
CPU time 2.1 seconds
Started Aug 17 06:31:16 PM PDT 24
Finished Aug 17 06:31:18 PM PDT 24
Peak memory 219432 kb
Host smart-077b0738-fe83-453d-8353-50aed84f206c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898354029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2898354029
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3666773043
Short name T651
Test name
Test status
Simulation time 49597435 ps
CPU time 1.26 seconds
Started Aug 17 06:31:29 PM PDT 24
Finished Aug 17 06:31:30 PM PDT 24
Peak memory 218520 kb
Host smart-9ac97f1a-c407-4fc2-8370-18abca72e37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666773043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3666773043
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2447039417
Short name T461
Test name
Test status
Simulation time 39299835 ps
CPU time 1.53 seconds
Started Aug 17 06:31:34 PM PDT 24
Finished Aug 17 06:31:35 PM PDT 24
Peak memory 218612 kb
Host smart-244457b3-73b9-4c15-a65f-e56b284940e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447039417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2447039417
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.32139237
Short name T867
Test name
Test status
Simulation time 33572709 ps
CPU time 0.97 seconds
Started Aug 17 06:31:21 PM PDT 24
Finished Aug 17 06:31:22 PM PDT 24
Peak memory 217420 kb
Host smart-191c8c4e-27bb-477c-8526-649b518d623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32139237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.32139237
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.4236470522
Short name T226
Test name
Test status
Simulation time 43066290 ps
CPU time 1.54 seconds
Started Aug 17 06:31:18 PM PDT 24
Finished Aug 17 06:31:20 PM PDT 24
Peak memory 218628 kb
Host smart-981fd026-caa4-4ee2-96f4-f53d898dead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236470522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.4236470522
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.833596445
Short name T177
Test name
Test status
Simulation time 24914868 ps
CPU time 1.22 seconds
Started Aug 17 06:29:21 PM PDT 24
Finished Aug 17 06:29:23 PM PDT 24
Peak memory 219788 kb
Host smart-923b05f1-4f02-4802-b208-f92073ce9e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833596445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.833596445
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2488833111
Short name T719
Test name
Test status
Simulation time 46819427 ps
CPU time 0.93 seconds
Started Aug 17 06:29:14 PM PDT 24
Finished Aug 17 06:29:15 PM PDT 24
Peak memory 206796 kb
Host smart-01ebc72a-d0a7-48dc-80fb-255c529432f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488833111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2488833111
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2085694873
Short name T773
Test name
Test status
Simulation time 31455335 ps
CPU time 0.83 seconds
Started Aug 17 06:29:29 PM PDT 24
Finished Aug 17 06:29:30 PM PDT 24
Peak memory 207152 kb
Host smart-03e9240a-5016-4b56-9161-0106ab1d9e57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085694873 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2085694873
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.1067126447
Short name T961
Test name
Test status
Simulation time 63581522 ps
CPU time 1.34 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 218100 kb
Host smart-00ec76a3-822f-4d87-8e63-608bd1006268
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067126447 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.1067126447
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1250150420
Short name T202
Test name
Test status
Simulation time 22218117 ps
CPU time 1.19 seconds
Started Aug 17 06:29:15 PM PDT 24
Finished Aug 17 06:29:16 PM PDT 24
Peak memory 218604 kb
Host smart-d4abcf97-4a31-4af3-88bc-0ec11b196aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250150420 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1250150420
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.206661112
Short name T841
Test name
Test status
Simulation time 65425833 ps
CPU time 1.25 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:32 PM PDT 24
Peak memory 218556 kb
Host smart-17f997ef-6191-4476-9699-1d4d9d5ded6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206661112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.206661112
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.4293226098
Short name T48
Test name
Test status
Simulation time 42710294 ps
CPU time 1.04 seconds
Started Aug 17 06:29:16 PM PDT 24
Finished Aug 17 06:29:17 PM PDT 24
Peak memory 224236 kb
Host smart-c1d6fa16-d192-4cd0-8a5b-c97e4914a62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293226098 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.4293226098
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.4194204791
Short name T922
Test name
Test status
Simulation time 65370697 ps
CPU time 0.9 seconds
Started Aug 17 06:29:36 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 207128 kb
Host smart-4abfd376-d29a-415f-86f9-f1e5ebc469fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194204791 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4194204791
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1774872276
Short name T16
Test name
Test status
Simulation time 1037000823 ps
CPU time 4.95 seconds
Started Aug 17 06:29:30 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 236156 kb
Host smart-ad08ea22-9e6b-4906-a0c2-c86057374c88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774872276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1774872276
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1160749895
Short name T858
Test name
Test status
Simulation time 28144200 ps
CPU time 0.92 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 215356 kb
Host smart-a2668908-b9b3-46d5-8888-5e9e0b61ba2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160749895 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1160749895
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3830239259
Short name T839
Test name
Test status
Simulation time 1068235182 ps
CPU time 5.41 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 217244 kb
Host smart-b7196448-6582-4a8c-a422-d303e3eeb4ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830239259 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3830239259
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.315392665
Short name T213
Test name
Test status
Simulation time 12813590863 ps
CPU time 89.77 seconds
Started Aug 17 06:29:21 PM PDT 24
Finished Aug 17 06:30:50 PM PDT 24
Peak memory 217956 kb
Host smart-03a60f58-0d55-4026-86a1-64484c545456
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315392665 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.315392665
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1688176165
Short name T877
Test name
Test status
Simulation time 25780167 ps
CPU time 1.23 seconds
Started Aug 17 06:29:55 PM PDT 24
Finished Aug 17 06:29:56 PM PDT 24
Peak memory 219612 kb
Host smart-9fa6e534-5c7b-4f79-8407-39fba9883fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688176165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1688176165
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.182924617
Short name T499
Test name
Test status
Simulation time 25442881 ps
CPU time 0.86 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:32 PM PDT 24
Peak memory 215012 kb
Host smart-1e67786b-a436-4d0b-92fe-f09d5fd09b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182924617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.182924617
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.415039969
Short name T200
Test name
Test status
Simulation time 33034892 ps
CPU time 0.85 seconds
Started Aug 17 06:29:42 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 215376 kb
Host smart-31e85521-f757-47c5-a0a6-a52d438499d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415039969 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.415039969
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1115097513
Short name T56
Test name
Test status
Simulation time 63188049 ps
CPU time 0.99 seconds
Started Aug 17 06:29:40 PM PDT 24
Finished Aug 17 06:29:41 PM PDT 24
Peak memory 216944 kb
Host smart-61f0b737-b644-42c7-a06f-da5cbf3649b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115097513 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1115097513
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1251022895
Short name T851
Test name
Test status
Simulation time 20330822 ps
CPU time 1.12 seconds
Started Aug 17 06:29:48 PM PDT 24
Finished Aug 17 06:29:49 PM PDT 24
Peak memory 219656 kb
Host smart-0acfaeb4-3bf3-46c1-bc8a-48d09d2c64e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251022895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1251022895
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1976168831
Short name T652
Test name
Test status
Simulation time 70385715 ps
CPU time 1.28 seconds
Started Aug 17 06:30:06 PM PDT 24
Finished Aug 17 06:30:07 PM PDT 24
Peak memory 218968 kb
Host smart-e9edd6eb-e86a-4100-adc0-3ee51036a352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976168831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1976168831
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3583811453
Short name T381
Test name
Test status
Simulation time 20942925 ps
CPU time 1.06 seconds
Started Aug 17 06:30:06 PM PDT 24
Finished Aug 17 06:30:07 PM PDT 24
Peak memory 216064 kb
Host smart-a9983e82-3621-4851-8794-51ad6e715f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583811453 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3583811453
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2076428416
Short name T321
Test name
Test status
Simulation time 18139962 ps
CPU time 1.07 seconds
Started Aug 17 06:30:16 PM PDT 24
Finished Aug 17 06:30:17 PM PDT 24
Peak memory 215560 kb
Host smart-5503a581-516a-4701-804c-0176971848f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076428416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2076428416
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4265300620
Short name T370
Test name
Test status
Simulation time 178020380 ps
CPU time 1.49 seconds
Started Aug 17 06:30:21 PM PDT 24
Finished Aug 17 06:30:23 PM PDT 24
Peak memory 215360 kb
Host smart-6691799d-5108-4305-852f-104797848c2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265300620 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4265300620
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1083979572
Short name T217
Test name
Test status
Simulation time 2262640365 ps
CPU time 54.56 seconds
Started Aug 17 06:30:05 PM PDT 24
Finished Aug 17 06:30:59 PM PDT 24
Peak memory 219684 kb
Host smart-b1fd40f6-c3e9-41e1-bea4-ab02abda3c2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083979572 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1083979572
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.926894759
Short name T468
Test name
Test status
Simulation time 100428660 ps
CPU time 1.1 seconds
Started Aug 17 06:29:49 PM PDT 24
Finished Aug 17 06:29:51 PM PDT 24
Peak memory 218540 kb
Host smart-5b33807c-9f3b-45a9-9467-af9f42d91a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926894759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.926894759
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2729648721
Short name T944
Test name
Test status
Simulation time 15957340 ps
CPU time 0.92 seconds
Started Aug 17 06:29:54 PM PDT 24
Finished Aug 17 06:29:55 PM PDT 24
Peak memory 214908 kb
Host smart-75761845-cb32-4005-8822-7ec6749929c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729648721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2729648721
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.4108278965
Short name T433
Test name
Test status
Simulation time 20706309 ps
CPU time 0.87 seconds
Started Aug 17 06:29:36 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 207004 kb
Host smart-36786ea1-10d3-47e3-b543-e3b701af6b0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108278965 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.4108278965
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3201675051
Short name T656
Test name
Test status
Simulation time 62523531 ps
CPU time 1.21 seconds
Started Aug 17 06:29:52 PM PDT 24
Finished Aug 17 06:29:54 PM PDT 24
Peak memory 216852 kb
Host smart-77bbfa52-08fd-47af-97ca-b410ef67aa29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201675051 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3201675051
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.28023019
Short name T134
Test name
Test status
Simulation time 29725095 ps
CPU time 1.04 seconds
Started Aug 17 06:29:59 PM PDT 24
Finished Aug 17 06:30:01 PM PDT 24
Peak memory 218520 kb
Host smart-919bbdec-6454-4c68-8e46-6a17884313ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28023019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.28023019
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.594644970
Short name T306
Test name
Test status
Simulation time 37817206 ps
CPU time 1.48 seconds
Started Aug 17 06:29:44 PM PDT 24
Finished Aug 17 06:29:46 PM PDT 24
Peak memory 218972 kb
Host smart-a1a75bb8-44b7-4404-9ea6-ca72f8437e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594644970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.594644970
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3636203440
Short name T543
Test name
Test status
Simulation time 21633352 ps
CPU time 1.13 seconds
Started Aug 17 06:29:47 PM PDT 24
Finished Aug 17 06:29:48 PM PDT 24
Peak memory 215768 kb
Host smart-2cc071f5-007e-49ea-919f-b03efdf5899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636203440 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3636203440
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1854788819
Short name T932
Test name
Test status
Simulation time 56197468 ps
CPU time 0.98 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 215304 kb
Host smart-0ee98553-de01-4c5e-b8e0-366bc4cda0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854788819 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1854788819
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.604195075
Short name T88
Test name
Test status
Simulation time 243687842 ps
CPU time 5.08 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:44 PM PDT 24
Peak memory 217524 kb
Host smart-33514225-bb8a-45d6-a13a-6632ad03813d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604195075 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.604195075
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.784294979
Short name T533
Test name
Test status
Simulation time 7152895045 ps
CPU time 74.05 seconds
Started Aug 17 06:30:03 PM PDT 24
Finished Aug 17 06:31:17 PM PDT 24
Peak memory 218508 kb
Host smart-cc38b652-532b-45d3-8ce4-17fae010e3e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784294979 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.784294979
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.81888006
Short name T717
Test name
Test status
Simulation time 25409498 ps
CPU time 1.19 seconds
Started Aug 17 06:30:21 PM PDT 24
Finished Aug 17 06:30:22 PM PDT 24
Peak memory 221028 kb
Host smart-4239b242-cf12-4d2a-ba2f-65de4d471f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81888006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.81888006
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.961558032
Short name T923
Test name
Test status
Simulation time 69313169 ps
CPU time 1.09 seconds
Started Aug 17 06:30:17 PM PDT 24
Finished Aug 17 06:30:18 PM PDT 24
Peak memory 206824 kb
Host smart-cafc9d97-580d-4373-8360-8e296af4f4c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961558032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.961558032
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1822991472
Short name T751
Test name
Test status
Simulation time 40087942 ps
CPU time 0.89 seconds
Started Aug 17 06:30:02 PM PDT 24
Finished Aug 17 06:30:04 PM PDT 24
Peak memory 215332 kb
Host smart-0d9ab90f-6764-411d-93bf-3a7895ab975e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822991472 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1822991472
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3624865895
Short name T767
Test name
Test status
Simulation time 306959595 ps
CPU time 1.03 seconds
Started Aug 17 06:30:02 PM PDT 24
Finished Aug 17 06:30:04 PM PDT 24
Peak memory 216768 kb
Host smart-0cfd400e-3efc-428e-8dc6-82d10686f3f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624865895 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3624865895
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.796273875
Short name T738
Test name
Test status
Simulation time 42030615 ps
CPU time 1.07 seconds
Started Aug 17 06:30:08 PM PDT 24
Finished Aug 17 06:30:09 PM PDT 24
Peak memory 218568 kb
Host smart-f462a779-67f3-4316-b38e-fceb5f83999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796273875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.796273875
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2701371740
Short name T294
Test name
Test status
Simulation time 210675868 ps
CPU time 2.7 seconds
Started Aug 17 06:30:06 PM PDT 24
Finished Aug 17 06:30:09 PM PDT 24
Peak memory 220324 kb
Host smart-0d2c9d7b-3331-434d-ac8b-8e7543e539db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701371740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2701371740
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2383182126
Short name T517
Test name
Test status
Simulation time 83024334 ps
CPU time 0.84 seconds
Started Aug 17 06:29:53 PM PDT 24
Finished Aug 17 06:29:54 PM PDT 24
Peak memory 215408 kb
Host smart-37d162aa-174f-472d-829b-3b9c44d5a919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383182126 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2383182126
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2079638170
Short name T333
Test name
Test status
Simulation time 37177479 ps
CPU time 0.93 seconds
Started Aug 17 06:30:10 PM PDT 24
Finished Aug 17 06:30:11 PM PDT 24
Peak memory 215396 kb
Host smart-8f0c993c-da4c-49c5-a770-727654b00164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079638170 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2079638170
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2942140356
Short name T632
Test name
Test status
Simulation time 205254290 ps
CPU time 4.27 seconds
Started Aug 17 06:29:52 PM PDT 24
Finished Aug 17 06:29:57 PM PDT 24
Peak memory 215372 kb
Host smart-8722497e-6be9-4d5e-9511-3e683ed2a775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942140356 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2942140356
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1223156171
Short name T2
Test name
Test status
Simulation time 1037082688 ps
CPU time 29.38 seconds
Started Aug 17 06:30:09 PM PDT 24
Finished Aug 17 06:30:38 PM PDT 24
Peak memory 220076 kb
Host smart-d0917f05-30bb-4a8f-b851-874f7582f1d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223156171 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1223156171
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.399322622
Short name T802
Test name
Test status
Simulation time 28412043 ps
CPU time 1.29 seconds
Started Aug 17 06:29:56 PM PDT 24
Finished Aug 17 06:29:58 PM PDT 24
Peak memory 219572 kb
Host smart-b0d3a858-d611-4fc8-a0c1-56a1796b2f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399322622 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.399322622
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3302853123
Short name T387
Test name
Test status
Simulation time 13412859 ps
CPU time 0.9 seconds
Started Aug 17 06:30:16 PM PDT 24
Finished Aug 17 06:30:17 PM PDT 24
Peak memory 207036 kb
Host smart-2c090e5b-ec60-4ce1-958d-93acfa080df0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302853123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3302853123
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2882028354
Short name T191
Test name
Test status
Simulation time 13074769 ps
CPU time 0.95 seconds
Started Aug 17 06:30:03 PM PDT 24
Finished Aug 17 06:30:04 PM PDT 24
Peak memory 215564 kb
Host smart-71098af8-8c40-499d-8cac-c475d6c1e5aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882028354 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2882028354
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3721717086
Short name T743
Test name
Test status
Simulation time 62301196 ps
CPU time 1.23 seconds
Started Aug 17 06:29:59 PM PDT 24
Finished Aug 17 06:30:01 PM PDT 24
Peak memory 216784 kb
Host smart-d43080d9-ac29-48b9-8471-799c263bc90c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721717086 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3721717086
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2106199812
Short name T150
Test name
Test status
Simulation time 54661105 ps
CPU time 1.27 seconds
Started Aug 17 06:30:09 PM PDT 24
Finished Aug 17 06:30:11 PM PDT 24
Peak memory 225892 kb
Host smart-d7c39de6-a0de-4916-91c5-286aa0ffa3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106199812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2106199812
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2558958993
Short name T344
Test name
Test status
Simulation time 94412781 ps
CPU time 3.03 seconds
Started Aug 17 06:29:47 PM PDT 24
Finished Aug 17 06:29:50 PM PDT 24
Peak memory 220660 kb
Host smart-7445a93a-af21-4868-89fb-9bbea87de65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558958993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2558958993
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.251976417
Short name T684
Test name
Test status
Simulation time 25419497 ps
CPU time 0.92 seconds
Started Aug 17 06:30:22 PM PDT 24
Finished Aug 17 06:30:23 PM PDT 24
Peak memory 215820 kb
Host smart-739d18af-96b4-4491-becb-c9d9d2762eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251976417 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.251976417
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.936121810
Short name T439
Test name
Test status
Simulation time 19712738 ps
CPU time 0.93 seconds
Started Aug 17 06:30:02 PM PDT 24
Finished Aug 17 06:30:03 PM PDT 24
Peak memory 215320 kb
Host smart-84dc7e9e-b6d2-4970-b1a0-b7cc4fc6fca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936121810 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.936121810
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3881155814
Short name T876
Test name
Test status
Simulation time 504363587 ps
CPU time 3.24 seconds
Started Aug 17 06:29:54 PM PDT 24
Finished Aug 17 06:29:57 PM PDT 24
Peak memory 215356 kb
Host smart-0e92539b-4e05-439e-a4a7-52c4659f7bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881155814 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3881155814
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.2452354346
Short name T718
Test name
Test status
Simulation time 32639647 ps
CPU time 1.33 seconds
Started Aug 17 06:29:50 PM PDT 24
Finished Aug 17 06:29:51 PM PDT 24
Peak memory 220032 kb
Host smart-5497facd-f400-41c6-b837-792cf4937ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452354346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2452354346
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.753747594
Short name T386
Test name
Test status
Simulation time 18075380 ps
CPU time 0.89 seconds
Started Aug 17 06:30:03 PM PDT 24
Finished Aug 17 06:30:04 PM PDT 24
Peak memory 214804 kb
Host smart-a8604d44-d07f-4e3d-8d46-6a9e6adf8b00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753747594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.753747594
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2378817925
Short name T974
Test name
Test status
Simulation time 42919181 ps
CPU time 0.84 seconds
Started Aug 17 06:29:44 PM PDT 24
Finished Aug 17 06:29:50 PM PDT 24
Peak memory 206980 kb
Host smart-564e3ffc-f142-47c8-9d45-078e1ee714d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378817925 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2378817925
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2460465135
Short name T60
Test name
Test status
Simulation time 45272089 ps
CPU time 1.22 seconds
Started Aug 17 06:29:51 PM PDT 24
Finished Aug 17 06:29:53 PM PDT 24
Peak memory 216980 kb
Host smart-0a368ae7-7d63-486b-9fe2-01d5e9853e0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460465135 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2460465135
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4084868180
Short name T197
Test name
Test status
Simulation time 41890241 ps
CPU time 0.91 seconds
Started Aug 17 06:30:09 PM PDT 24
Finished Aug 17 06:30:10 PM PDT 24
Peak memory 218368 kb
Host smart-2ee0e1ff-5152-4575-a104-086b3f23e1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084868180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4084868180
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3624439445
Short name T968
Test name
Test status
Simulation time 86838736 ps
CPU time 1.09 seconds
Started Aug 17 06:30:17 PM PDT 24
Finished Aug 17 06:30:18 PM PDT 24
Peak memory 217292 kb
Host smart-f6fd5e5b-e9b2-4254-a105-181d458b763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624439445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3624439445
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3243846052
Short name T753
Test name
Test status
Simulation time 29286086 ps
CPU time 1 seconds
Started Aug 17 06:30:06 PM PDT 24
Finished Aug 17 06:30:07 PM PDT 24
Peak memory 215556 kb
Host smart-752d6326-2889-49a6-bc6c-f89da2c84e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243846052 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3243846052
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2402482249
Short name T862
Test name
Test status
Simulation time 40845084 ps
CPU time 0.92 seconds
Started Aug 17 06:29:58 PM PDT 24
Finished Aug 17 06:29:59 PM PDT 24
Peak memory 215388 kb
Host smart-c9ce7ebf-f08f-41a7-8303-66f818f0a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402482249 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2402482249
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3078520266
Short name T879
Test name
Test status
Simulation time 277811450 ps
CPU time 5.54 seconds
Started Aug 17 06:29:55 PM PDT 24
Finished Aug 17 06:30:00 PM PDT 24
Peak memory 217228 kb
Host smart-bca339f6-bc49-4eca-bc90-fc8b676a0cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078520266 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3078520266
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.2147278217
Short name T870
Test name
Test status
Simulation time 70088922 ps
CPU time 1.09 seconds
Started Aug 17 06:30:22 PM PDT 24
Finished Aug 17 06:30:24 PM PDT 24
Peak memory 218528 kb
Host smart-ed7f1264-1a90-4bec-aa10-d63a8fa6c40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147278217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2147278217
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1597092221
Short name T394
Test name
Test status
Simulation time 44435085 ps
CPU time 1.12 seconds
Started Aug 17 06:29:55 PM PDT 24
Finished Aug 17 06:29:57 PM PDT 24
Peak memory 215160 kb
Host smart-14de99e4-74de-40bd-902e-cb363aca786a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597092221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1597092221
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3618436527
Short name T878
Test name
Test status
Simulation time 29584956 ps
CPU time 0.81 seconds
Started Aug 17 06:30:01 PM PDT 24
Finished Aug 17 06:30:02 PM PDT 24
Peak memory 207172 kb
Host smart-6e5d3e37-b5fc-4d4c-9d09-82ff8d26b3ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618436527 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3618436527
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.726612964
Short name T909
Test name
Test status
Simulation time 26967549 ps
CPU time 1.16 seconds
Started Aug 17 06:30:17 PM PDT 24
Finished Aug 17 06:30:19 PM PDT 24
Peak memory 218124 kb
Host smart-859d5d49-e113-4c19-a593-3b0fce11e9e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726612964 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.726612964
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2808660185
Short name T760
Test name
Test status
Simulation time 18207204 ps
CPU time 1.1 seconds
Started Aug 17 06:30:06 PM PDT 24
Finished Aug 17 06:30:08 PM PDT 24
Peak memory 218712 kb
Host smart-d6dfebe7-7cc2-408e-ab85-53c3a5a1684c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808660185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2808660185
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3346589813
Short name T925
Test name
Test status
Simulation time 67983115 ps
CPU time 2.6 seconds
Started Aug 17 06:29:54 PM PDT 24
Finished Aug 17 06:30:02 PM PDT 24
Peak memory 219904 kb
Host smart-ddd9173b-558b-4bf8-bad9-2c53a284693a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346589813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3346589813
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2311832118
Short name T393
Test name
Test status
Simulation time 23485525 ps
CPU time 0.93 seconds
Started Aug 17 06:29:57 PM PDT 24
Finished Aug 17 06:29:58 PM PDT 24
Peak memory 215628 kb
Host smart-ec6c2332-f4cb-4d6f-b9e7-7170c6481511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311832118 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2311832118
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1659530484
Short name T722
Test name
Test status
Simulation time 31460785 ps
CPU time 0.88 seconds
Started Aug 17 06:30:14 PM PDT 24
Finished Aug 17 06:30:15 PM PDT 24
Peak memory 215340 kb
Host smart-40485961-748b-4410-b702-3e87b89e30f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659530484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1659530484
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2478734387
Short name T98
Test name
Test status
Simulation time 320341581 ps
CPU time 2.64 seconds
Started Aug 17 06:30:06 PM PDT 24
Finished Aug 17 06:30:09 PM PDT 24
Peak memory 215368 kb
Host smart-8b2b2797-7f9e-4d85-a56e-212eccab5ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478734387 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2478734387
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_alert.1348873359
Short name T501
Test name
Test status
Simulation time 103165669 ps
CPU time 1.14 seconds
Started Aug 17 06:30:09 PM PDT 24
Finished Aug 17 06:30:10 PM PDT 24
Peak memory 220308 kb
Host smart-284529ac-791e-4d7d-80e4-ea8d0dcc386c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348873359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1348873359
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1503626931
Short name T272
Test name
Test status
Simulation time 20485555 ps
CPU time 0.88 seconds
Started Aug 17 06:30:13 PM PDT 24
Finished Aug 17 06:30:14 PM PDT 24
Peak memory 206528 kb
Host smart-2f35f2ea-3f91-409a-bdc9-575cc51e5053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503626931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1503626931
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.349100389
Short name T112
Test name
Test status
Simulation time 59312581 ps
CPU time 1.43 seconds
Started Aug 17 06:30:20 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 216796 kb
Host smart-ccec9881-cc1c-4996-ae77-63f518efdce4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349100389 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.349100389
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.323534155
Short name T874
Test name
Test status
Simulation time 26286112 ps
CPU time 0.92 seconds
Started Aug 17 06:30:04 PM PDT 24
Finished Aug 17 06:30:05 PM PDT 24
Peak memory 218240 kb
Host smart-9381bdb7-fab4-43aa-9fd5-14d86dc567ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323534155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.323534155
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_intr.1618462179
Short name T63
Test name
Test status
Simulation time 22815340 ps
CPU time 0.98 seconds
Started Aug 17 06:30:05 PM PDT 24
Finished Aug 17 06:30:06 PM PDT 24
Peak memory 216028 kb
Host smart-c4e2b3f3-47d6-4777-a75d-7e515562e88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618462179 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1618462179
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.937261574
Short name T708
Test name
Test status
Simulation time 16751780 ps
CPU time 1.01 seconds
Started Aug 17 06:30:01 PM PDT 24
Finished Aug 17 06:30:02 PM PDT 24
Peak memory 215336 kb
Host smart-636bf71a-8fff-4ab2-b404-eeea612b0beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937261574 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.937261574
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2761467421
Short name T664
Test name
Test status
Simulation time 37581107 ps
CPU time 1.3 seconds
Started Aug 17 06:30:08 PM PDT 24
Finished Aug 17 06:30:09 PM PDT 24
Peak memory 215316 kb
Host smart-c03a0b21-a164-4540-9f47-41c145602c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761467421 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2761467421
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2126908345
Short name T635
Test name
Test status
Simulation time 9690703252 ps
CPU time 80.12 seconds
Started Aug 17 06:30:14 PM PDT 24
Finished Aug 17 06:31:34 PM PDT 24
Peak memory 218708 kb
Host smart-fb3b67b5-cfbb-4c0a-849b-7bca88572dca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126908345 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2126908345
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert_test.2033211121
Short name T55
Test name
Test status
Simulation time 56406612 ps
CPU time 0.94 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:27 PM PDT 24
Peak memory 206784 kb
Host smart-884f5fd9-7601-418d-aa51-244002bbcb39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033211121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2033211121
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.4158950694
Short name T735
Test name
Test status
Simulation time 10652663 ps
CPU time 0.87 seconds
Started Aug 17 06:30:11 PM PDT 24
Finished Aug 17 06:30:12 PM PDT 24
Peak memory 215428 kb
Host smart-0e8263ea-5eb5-40c7-b592-b04fb632dc59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158950694 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.4158950694
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.4208275358
Short name T849
Test name
Test status
Simulation time 37856322 ps
CPU time 1.25 seconds
Started Aug 17 06:30:13 PM PDT 24
Finished Aug 17 06:30:15 PM PDT 24
Peak memory 216884 kb
Host smart-192adb3f-5eeb-4c45-b8e8-fdc6427b524c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208275358 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.4208275358
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.204275225
Short name T125
Test name
Test status
Simulation time 25965467 ps
CPU time 1.22 seconds
Started Aug 17 06:30:07 PM PDT 24
Finished Aug 17 06:30:08 PM PDT 24
Peak memory 220712 kb
Host smart-ad70f836-1102-4088-bb6a-53dc811ff76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204275225 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.204275225
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.123423210
Short name T380
Test name
Test status
Simulation time 44827360 ps
CPU time 1.11 seconds
Started Aug 17 06:30:13 PM PDT 24
Finished Aug 17 06:30:15 PM PDT 24
Peak memory 217240 kb
Host smart-1c7f5ab5-a06a-477b-a0a8-0eab2091331e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123423210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.123423210
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1326893709
Short name T948
Test name
Test status
Simulation time 25950153 ps
CPU time 0.96 seconds
Started Aug 17 06:30:15 PM PDT 24
Finished Aug 17 06:30:16 PM PDT 24
Peak memory 215584 kb
Host smart-d1992ffe-dce1-4b55-8f0a-05798e59ace7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326893709 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1326893709
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3806890044
Short name T419
Test name
Test status
Simulation time 42796766 ps
CPU time 0.93 seconds
Started Aug 17 06:30:17 PM PDT 24
Finished Aug 17 06:30:18 PM PDT 24
Peak memory 215360 kb
Host smart-1db4338f-5902-438f-b119-dd95eaab3540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806890044 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3806890044
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2608048369
Short name T857
Test name
Test status
Simulation time 43866503 ps
CPU time 1.31 seconds
Started Aug 17 06:30:07 PM PDT 24
Finished Aug 17 06:30:08 PM PDT 24
Peak memory 206768 kb
Host smart-a60c97a3-f736-4898-859f-af361b4f74c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608048369 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2608048369
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2403476616
Short name T595
Test name
Test status
Simulation time 4867777213 ps
CPU time 65.01 seconds
Started Aug 17 06:29:55 PM PDT 24
Finished Aug 17 06:31:01 PM PDT 24
Peak memory 217612 kb
Host smart-7302d3d7-32e6-464e-8fe9-13ae545ca25b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403476616 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2403476616
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.52106325
Short name T548
Test name
Test status
Simulation time 26180644 ps
CPU time 1.2 seconds
Started Aug 17 06:30:03 PM PDT 24
Finished Aug 17 06:30:04 PM PDT 24
Peak memory 220532 kb
Host smart-59fe460a-b9f5-4603-bf0a-620a3ace045c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52106325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.52106325
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3468095462
Short name T368
Test name
Test status
Simulation time 60142728 ps
CPU time 0.86 seconds
Started Aug 17 06:30:15 PM PDT 24
Finished Aug 17 06:30:16 PM PDT 24
Peak memory 206756 kb
Host smart-a0419718-8fa7-4b06-b84b-59f995e49007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468095462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3468095462
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2275504012
Short name T407
Test name
Test status
Simulation time 150922791 ps
CPU time 0.92 seconds
Started Aug 17 06:30:12 PM PDT 24
Finished Aug 17 06:30:13 PM PDT 24
Peak memory 215104 kb
Host smart-36d02940-723a-4cb3-88d3-336ee3d41a23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275504012 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2275504012
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.7927842
Short name T601
Test name
Test status
Simulation time 34825625 ps
CPU time 1.19 seconds
Started Aug 17 06:30:05 PM PDT 24
Finished Aug 17 06:30:06 PM PDT 24
Peak memory 219752 kb
Host smart-5d12849a-562e-4609-b04f-08851d8557a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7927842 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disab
le_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disa
ble_auto_req_mode.7927842
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1495054396
Short name T135
Test name
Test status
Simulation time 32745786 ps
CPU time 1.18 seconds
Started Aug 17 06:29:59 PM PDT 24
Finished Aug 17 06:30:01 PM PDT 24
Peak memory 224112 kb
Host smart-6205287e-5922-420c-b3bc-52ac723f4d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495054396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1495054396
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.877038558
Short name T389
Test name
Test status
Simulation time 107254800 ps
CPU time 1.47 seconds
Started Aug 17 06:30:16 PM PDT 24
Finished Aug 17 06:30:17 PM PDT 24
Peak memory 218968 kb
Host smart-7a44f5a8-a00d-497e-9475-da4a74ee8482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877038558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.877038558
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2709450609
Short name T33
Test name
Test status
Simulation time 25566808 ps
CPU time 0.99 seconds
Started Aug 17 06:30:13 PM PDT 24
Finished Aug 17 06:30:14 PM PDT 24
Peak memory 215992 kb
Host smart-57898896-b7bf-4650-b0d0-ea973c2d7512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709450609 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2709450609
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.96600722
Short name T554
Test name
Test status
Simulation time 48379741 ps
CPU time 0.94 seconds
Started Aug 17 06:30:22 PM PDT 24
Finished Aug 17 06:30:23 PM PDT 24
Peak memory 215380 kb
Host smart-1d7ab7e9-53b6-4f78-95c2-af7ee4142484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96600722 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.96600722
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3550033113
Short name T449
Test name
Test status
Simulation time 69573838 ps
CPU time 1.06 seconds
Started Aug 17 06:30:10 PM PDT 24
Finished Aug 17 06:30:11 PM PDT 24
Peak memory 206940 kb
Host smart-1e3eda5a-a6fd-4454-838e-4a37d79a8b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550033113 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3550033113
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_alert.1556984025
Short name T823
Test name
Test status
Simulation time 85033601 ps
CPU time 1.22 seconds
Started Aug 17 06:30:12 PM PDT 24
Finished Aug 17 06:30:13 PM PDT 24
Peak memory 215764 kb
Host smart-57fe59c9-a09a-439e-8c87-e79405675b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556984025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1556984025
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2821568194
Short name T496
Test name
Test status
Simulation time 24041952 ps
CPU time 0.91 seconds
Started Aug 17 06:30:16 PM PDT 24
Finished Aug 17 06:30:17 PM PDT 24
Peak memory 206804 kb
Host smart-a9be021e-e022-4268-ac6b-9a7a0d21e505
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821568194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2821568194
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.425160980
Short name T353
Test name
Test status
Simulation time 66589279 ps
CPU time 0.88 seconds
Started Aug 17 06:30:09 PM PDT 24
Finished Aug 17 06:30:10 PM PDT 24
Peak memory 215464 kb
Host smart-ae84115b-2f7d-4633-9b45-481046e3ff94
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425160980 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.425160980
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2716125513
Short name T539
Test name
Test status
Simulation time 87099614 ps
CPU time 1.14 seconds
Started Aug 17 06:30:03 PM PDT 24
Finished Aug 17 06:30:04 PM PDT 24
Peak memory 217024 kb
Host smart-a70d3ebd-9c72-4981-b15b-5bc9ee8c89a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716125513 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2716125513
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3099765343
Short name T129
Test name
Test status
Simulation time 22462273 ps
CPU time 1.15 seconds
Started Aug 17 06:30:19 PM PDT 24
Finished Aug 17 06:30:20 PM PDT 24
Peak memory 219640 kb
Host smart-f8e76901-b2ab-4b05-899c-d63d2c8c6b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099765343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3099765343
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1070078793
Short name T420
Test name
Test status
Simulation time 114241469 ps
CPU time 1.02 seconds
Started Aug 17 06:30:22 PM PDT 24
Finished Aug 17 06:30:23 PM PDT 24
Peak memory 217256 kb
Host smart-04811537-d02d-4d11-aed9-a24ffeb0194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070078793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1070078793
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.762464305
Short name T669
Test name
Test status
Simulation time 21750612 ps
CPU time 1.08 seconds
Started Aug 17 06:30:08 PM PDT 24
Finished Aug 17 06:30:09 PM PDT 24
Peak memory 215892 kb
Host smart-a477f8e5-d0fb-4450-b814-32ea5b066939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762464305 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.762464305
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1721127113
Short name T880
Test name
Test status
Simulation time 18374629 ps
CPU time 0.98 seconds
Started Aug 17 06:30:07 PM PDT 24
Finished Aug 17 06:30:08 PM PDT 24
Peak memory 215352 kb
Host smart-b8134ff8-0d02-4e29-b71c-08d0fd9583b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721127113 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1721127113
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.293340756
Short name T432
Test name
Test status
Simulation time 252273794 ps
CPU time 3.26 seconds
Started Aug 17 06:30:09 PM PDT 24
Finished Aug 17 06:30:12 PM PDT 24
Peak memory 217156 kb
Host smart-a0a3c06e-b8b7-4b45-9199-e05b0af99711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293340756 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.293340756
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.552282564
Short name T724
Test name
Test status
Simulation time 10172335146 ps
CPU time 74.59 seconds
Started Aug 17 06:30:19 PM PDT 24
Finished Aug 17 06:31:34 PM PDT 24
Peak memory 221720 kb
Host smart-95b9dc22-4862-4c63-825f-7ec9ac530d0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552282564 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.552282564
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3152549754
Short name T614
Test name
Test status
Simulation time 81844242 ps
CPU time 1.16 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 219884 kb
Host smart-40dfdf13-7085-407c-87b2-3bb022d931a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152549754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3152549754
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3440936184
Short name T557
Test name
Test status
Simulation time 19881947 ps
CPU time 1.05 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 215176 kb
Host smart-3ec3bf52-9512-465d-9bec-e775746fd8ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440936184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3440936184
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3890589060
Short name T796
Test name
Test status
Simulation time 12622810 ps
CPU time 0.91 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 215604 kb
Host smart-4749642d-f50d-40bc-ad2c-b9b391aa994b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890589060 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3890589060
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.135468858
Short name T417
Test name
Test status
Simulation time 47442221 ps
CPU time 0.97 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 218260 kb
Host smart-a775ebe9-dbec-4c76-b7cf-7183f16c53a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135468858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.135468858
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2710879126
Short name T117
Test name
Test status
Simulation time 21147169 ps
CPU time 1.24 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 229776 kb
Host smart-fa996639-9e4f-4765-8d6a-2bb807562679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710879126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2710879126
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1967329447
Short name T329
Test name
Test status
Simulation time 48295182 ps
CPU time 1.26 seconds
Started Aug 17 06:29:30 PM PDT 24
Finished Aug 17 06:29:31 PM PDT 24
Peak memory 218764 kb
Host smart-e050af34-242f-4138-877c-8b0385d206d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967329447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1967329447
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2319413403
Short name T86
Test name
Test status
Simulation time 21930313 ps
CPU time 1.05 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 215804 kb
Host smart-64412c5b-5e35-48de-9a49-fb7ce0db5d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319413403 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2319413403
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1481102557
Short name T227
Test name
Test status
Simulation time 48532411 ps
CPU time 0.91 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 207148 kb
Host smart-eea91356-c4d2-4fba-ae39-5f73f50634ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481102557 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1481102557
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.525258721
Short name T17
Test name
Test status
Simulation time 1106550290 ps
CPU time 5.24 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 236188 kb
Host smart-0ec189d7-1895-4415-934c-0eac402c40f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525258721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.525258721
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.4002314567
Short name T412
Test name
Test status
Simulation time 39158589 ps
CPU time 0.94 seconds
Started Aug 17 06:29:21 PM PDT 24
Finished Aug 17 06:29:22 PM PDT 24
Peak memory 207180 kb
Host smart-a6856a44-3f97-4307-913c-16076f0c5c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002314567 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.4002314567
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4157765846
Short name T641
Test name
Test status
Simulation time 1293439008 ps
CPU time 3.12 seconds
Started Aug 17 06:29:16 PM PDT 24
Finished Aug 17 06:29:19 PM PDT 24
Peak memory 215284 kb
Host smart-7fa8538d-3c62-4df7-a964-2848de9c445f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157765846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4157765846
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1960698197
Short name T92
Test name
Test status
Simulation time 5416817813 ps
CPU time 36.19 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:30:15 PM PDT 24
Peak memory 217900 kb
Host smart-b364417c-f32a-4a34-b3e2-a4490426ea1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960698197 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1960698197
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.4212667757
Short name T104
Test name
Test status
Simulation time 53240986 ps
CPU time 1.33 seconds
Started Aug 17 06:30:12 PM PDT 24
Finished Aug 17 06:30:13 PM PDT 24
Peak memory 218688 kb
Host smart-ff95c8fc-403b-4819-be8a-9817d522dd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212667757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.4212667757
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2464066718
Short name T392
Test name
Test status
Simulation time 16814653 ps
CPU time 0.94 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 206656 kb
Host smart-e7b78336-fdc6-4057-b903-5aaf59659c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464066718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2464066718
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3674026733
Short name T174
Test name
Test status
Simulation time 22029450 ps
CPU time 0.9 seconds
Started Aug 17 06:30:13 PM PDT 24
Finished Aug 17 06:30:14 PM PDT 24
Peak memory 215376 kb
Host smart-ebb13974-5867-44e5-8102-ff6dd1095077
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674026733 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3674026733
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3988821340
Short name T131
Test name
Test status
Simulation time 38047163 ps
CPU time 1.24 seconds
Started Aug 17 06:30:22 PM PDT 24
Finished Aug 17 06:30:23 PM PDT 24
Peak memory 217056 kb
Host smart-eb475724-edfc-4dc9-9648-b9a62a102367
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988821340 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3988821340
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2807042036
Short name T84
Test name
Test status
Simulation time 25849485 ps
CPU time 1.04 seconds
Started Aug 17 06:30:20 PM PDT 24
Finished Aug 17 06:30:21 PM PDT 24
Peak memory 219916 kb
Host smart-a0e60b90-ef79-4599-8990-a5c718fb3275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807042036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2807042036
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2129407076
Short name T229
Test name
Test status
Simulation time 257262914 ps
CPU time 1.17 seconds
Started Aug 17 06:30:10 PM PDT 24
Finished Aug 17 06:30:11 PM PDT 24
Peak memory 215320 kb
Host smart-22078f9b-97c1-4bd3-bd79-b3b4e70848d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129407076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2129407076
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.4067429639
Short name T928
Test name
Test status
Simulation time 21739149 ps
CPU time 1.11 seconds
Started Aug 17 06:30:10 PM PDT 24
Finished Aug 17 06:30:11 PM PDT 24
Peak memory 215512 kb
Host smart-6495c2e6-cedc-4aa2-b3d1-764514cd37ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067429639 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.4067429639
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.977793445
Short name T599
Test name
Test status
Simulation time 19449891 ps
CPU time 0.91 seconds
Started Aug 17 06:30:19 PM PDT 24
Finished Aug 17 06:30:21 PM PDT 24
Peak memory 215384 kb
Host smart-0323f2b7-639e-4888-bd46-5860736b76f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977793445 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.977793445
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2746103704
Short name T232
Test name
Test status
Simulation time 255831266 ps
CPU time 2.93 seconds
Started Aug 17 06:30:18 PM PDT 24
Finished Aug 17 06:30:21 PM PDT 24
Peak memory 215164 kb
Host smart-e2c4a3ff-1317-49bf-b616-cbe8720de4df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746103704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2746103704
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1775339488
Short name T209
Test name
Test status
Simulation time 1646439586 ps
CPU time 22.37 seconds
Started Aug 17 06:30:20 PM PDT 24
Finished Aug 17 06:30:43 PM PDT 24
Peak memory 219944 kb
Host smart-a8b3a82e-c2fe-4b0a-a60b-975bd34713cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775339488 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1775339488
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1380332094
Short name T711
Test name
Test status
Simulation time 40266590 ps
CPU time 1.19 seconds
Started Aug 17 06:30:10 PM PDT 24
Finished Aug 17 06:30:11 PM PDT 24
Peak memory 219664 kb
Host smart-cf6494d2-9fec-45ee-8790-95832b862671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380332094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1380332094
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.72742802
Short name T555
Test name
Test status
Simulation time 34591275 ps
CPU time 0.98 seconds
Started Aug 17 06:30:15 PM PDT 24
Finished Aug 17 06:30:16 PM PDT 24
Peak memory 206700 kb
Host smart-874141f2-cbd3-4899-9a7a-9796fb4b2ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72742802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.72742802
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2352634006
Short name T834
Test name
Test status
Simulation time 27619882 ps
CPU time 0.91 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 215420 kb
Host smart-5c75e46e-e079-4ef6-ab39-e3aaa8db3dbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352634006 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2352634006
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.4250667400
Short name T469
Test name
Test status
Simulation time 42175731 ps
CPU time 1.3 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 218408 kb
Host smart-630ab9e5-8885-4de2-bb97-2b5ae4dfb85e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250667400 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.4250667400
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2872712923
Short name T571
Test name
Test status
Simulation time 23990871 ps
CPU time 1.07 seconds
Started Aug 17 06:30:19 PM PDT 24
Finished Aug 17 06:30:20 PM PDT 24
Peak memory 220052 kb
Host smart-6e5652eb-7a1b-4fb9-b8f1-0a686da3bf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872712923 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2872712923
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1972156875
Short name T757
Test name
Test status
Simulation time 71212622 ps
CPU time 1.17 seconds
Started Aug 17 06:30:19 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 217400 kb
Host smart-5aa9b226-68e2-407e-84a5-6d97388cdf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972156875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1972156875
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2292114234
Short name T95
Test name
Test status
Simulation time 51722344 ps
CPU time 0.9 seconds
Started Aug 17 06:30:21 PM PDT 24
Finished Aug 17 06:30:22 PM PDT 24
Peak memory 215368 kb
Host smart-4f8be1bf-823f-464c-88de-ea4ea0a6cbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292114234 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2292114234
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.4025972700
Short name T498
Test name
Test status
Simulation time 16946065 ps
CPU time 0.94 seconds
Started Aug 17 06:30:23 PM PDT 24
Finished Aug 17 06:30:24 PM PDT 24
Peak memory 215288 kb
Host smart-e7ef6480-de80-449a-ac93-bae1886bac53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025972700 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.4025972700
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.462002293
Short name T356
Test name
Test status
Simulation time 737334668 ps
CPU time 4.17 seconds
Started Aug 17 06:30:15 PM PDT 24
Finished Aug 17 06:30:20 PM PDT 24
Peak memory 217340 kb
Host smart-6780b344-2151-4dc0-8a5f-f95b3626a428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462002293 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.462002293
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert.1215010300
Short name T566
Test name
Test status
Simulation time 26639222 ps
CPU time 1.18 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 219992 kb
Host smart-87c51355-e663-447a-89c3-4cb57e4ee4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215010300 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1215010300
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.254598740
Short name T585
Test name
Test status
Simulation time 144971052 ps
CPU time 0.86 seconds
Started Aug 17 06:30:09 PM PDT 24
Finished Aug 17 06:30:10 PM PDT 24
Peak memory 206580 kb
Host smart-2a00c07d-99e9-45a3-9c15-d335e83fc100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254598740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.254598740
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.150321142
Short name T207
Test name
Test status
Simulation time 11408491 ps
CPU time 0.88 seconds
Started Aug 17 06:30:14 PM PDT 24
Finished Aug 17 06:30:15 PM PDT 24
Peak memory 215436 kb
Host smart-2a00f6f2-44f2-4b2e-b1b9-ea604d36898c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150321142 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.150321142
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.4183885514
Short name T365
Test name
Test status
Simulation time 23719215 ps
CPU time 1.08 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:25 PM PDT 24
Peak memory 224128 kb
Host smart-fb23b995-203d-4789-9daf-c425cb8d72d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183885514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.4183885514
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2222558668
Short name T723
Test name
Test status
Simulation time 77180725 ps
CPU time 1.23 seconds
Started Aug 17 06:30:17 PM PDT 24
Finished Aug 17 06:30:19 PM PDT 24
Peak memory 218472 kb
Host smart-8121fb1d-b7a4-4975-9bf7-ca3bb2c276cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222558668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2222558668
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1071035795
Short name T477
Test name
Test status
Simulation time 31434998 ps
CPU time 0.9 seconds
Started Aug 17 06:30:20 PM PDT 24
Finished Aug 17 06:30:21 PM PDT 24
Peak memory 215548 kb
Host smart-08aac063-009e-4722-a16d-e14f24aa7f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071035795 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1071035795
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2753813151
Short name T382
Test name
Test status
Simulation time 16817214 ps
CPU time 0.95 seconds
Started Aug 17 06:30:23 PM PDT 24
Finished Aug 17 06:30:24 PM PDT 24
Peak memory 215396 kb
Host smart-88c57246-982f-4448-8f24-47437142f8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753813151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2753813151
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3080557455
Short name T937
Test name
Test status
Simulation time 619835995 ps
CPU time 3.92 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:33 PM PDT 24
Peak memory 217368 kb
Host smart-715aa401-528b-4e35-b032-0625dcc5aad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080557455 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3080557455
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert.207237853
Short name T73
Test name
Test status
Simulation time 25817398 ps
CPU time 1.24 seconds
Started Aug 17 06:30:15 PM PDT 24
Finished Aug 17 06:30:16 PM PDT 24
Peak memory 219576 kb
Host smart-228c97a9-4a5a-4c59-ac67-a2d4d3dcdb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207237853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.207237853
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.339532097
Short name T21
Test name
Test status
Simulation time 28675124 ps
CPU time 0.88 seconds
Started Aug 17 06:30:16 PM PDT 24
Finished Aug 17 06:30:17 PM PDT 24
Peak memory 214924 kb
Host smart-decb5810-300c-416e-a197-31a9bb811fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339532097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.339532097
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.82813815
Short name T64
Test name
Test status
Simulation time 12446577 ps
CPU time 0.9 seconds
Started Aug 17 06:30:22 PM PDT 24
Finished Aug 17 06:30:23 PM PDT 24
Peak memory 215620 kb
Host smart-8f81e613-2db2-4006-aa87-3fb3f12046e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82813815 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.82813815
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1939070862
Short name T655
Test name
Test status
Simulation time 56875073 ps
CPU time 1.15 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:27 PM PDT 24
Peak memory 217072 kb
Host smart-ae118ba2-9b40-494d-ae9e-5c5e9d515652
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939070862 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1939070862
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.4075766118
Short name T130
Test name
Test status
Simulation time 33897638 ps
CPU time 0.92 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:27 PM PDT 24
Peak memory 219656 kb
Host smart-8a7c8af4-10db-44ba-9233-6a588d4bbab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075766118 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4075766118
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.4040364995
Short name T561
Test name
Test status
Simulation time 62602705 ps
CPU time 1.26 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 217372 kb
Host smart-83afd943-9cb0-4e10-8704-7ea2ca8e6aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040364995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4040364995
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3105782458
Short name T763
Test name
Test status
Simulation time 28990620 ps
CPU time 0.95 seconds
Started Aug 17 06:30:19 PM PDT 24
Finished Aug 17 06:30:20 PM PDT 24
Peak memory 215628 kb
Host smart-eb6838bd-05b2-4c66-b5f1-b31045664d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105782458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3105782458
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1082652583
Short name T388
Test name
Test status
Simulation time 24604262 ps
CPU time 0.93 seconds
Started Aug 17 06:30:14 PM PDT 24
Finished Aug 17 06:30:15 PM PDT 24
Peak memory 215392 kb
Host smart-cc88bee9-b41e-449d-9cc1-3304142fc915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082652583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1082652583
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2159605394
Short name T754
Test name
Test status
Simulation time 83124307 ps
CPU time 1.51 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:25 PM PDT 24
Peak memory 215316 kb
Host smart-e8bfb725-aa3b-45f1-87c2-68dc06299f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159605394 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2159605394
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.416124079
Short name T463
Test name
Test status
Simulation time 7244712901 ps
CPU time 82.82 seconds
Started Aug 17 06:30:17 PM PDT 24
Finished Aug 17 06:31:40 PM PDT 24
Peak memory 221612 kb
Host smart-ce0f79ad-68a6-4f8c-9069-af668b713eaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416124079 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.416124079
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.1142687527
Short name T762
Test name
Test status
Simulation time 58274088 ps
CPU time 1.19 seconds
Started Aug 17 06:30:20 PM PDT 24
Finished Aug 17 06:30:21 PM PDT 24
Peak memory 220716 kb
Host smart-016f8807-c106-482b-9744-e62220a2c002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142687527 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.1142687527
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1033425052
Short name T430
Test name
Test status
Simulation time 70904347 ps
CPU time 0.96 seconds
Started Aug 17 06:30:17 PM PDT 24
Finished Aug 17 06:30:18 PM PDT 24
Peak memory 206764 kb
Host smart-c56330e7-db55-4e03-b949-85ed7f1f4cac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033425052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1033425052
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3293804816
Short name T580
Test name
Test status
Simulation time 57253896 ps
CPU time 0.91 seconds
Started Aug 17 06:30:13 PM PDT 24
Finished Aug 17 06:30:14 PM PDT 24
Peak memory 206948 kb
Host smart-20977065-f779-479b-b5fc-21547798afd3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293804816 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3293804816
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3006103178
Short name T967
Test name
Test status
Simulation time 90981618 ps
CPU time 1.08 seconds
Started Aug 17 06:30:22 PM PDT 24
Finished Aug 17 06:30:24 PM PDT 24
Peak memory 218484 kb
Host smart-5aa02429-ea50-4484-b3ba-6ef89c5fdcc7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006103178 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3006103178
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2735610790
Short name T921
Test name
Test status
Simulation time 27209188 ps
CPU time 0.92 seconds
Started Aug 17 06:30:20 PM PDT 24
Finished Aug 17 06:30:21 PM PDT 24
Peak memory 219544 kb
Host smart-67c758fa-3c45-4b69-9ba6-b854cc86c20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735610790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2735610790
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1138263718
Short name T514
Test name
Test status
Simulation time 72103900 ps
CPU time 1.05 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:27 PM PDT 24
Peak memory 217336 kb
Host smart-86582842-5536-464d-8be1-37a6b048c787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138263718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1138263718
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.385837615
Short name T690
Test name
Test status
Simulation time 41082748 ps
CPU time 0.9 seconds
Started Aug 17 06:30:16 PM PDT 24
Finished Aug 17 06:30:17 PM PDT 24
Peak memory 215460 kb
Host smart-ea59fb18-5909-4fb2-bb02-b73b8e331e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385837615 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.385837615
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2903494547
Short name T638
Test name
Test status
Simulation time 24426104 ps
CPU time 0.95 seconds
Started Aug 17 06:30:21 PM PDT 24
Finished Aug 17 06:30:22 PM PDT 24
Peak memory 215316 kb
Host smart-d79e5a7d-3588-4d22-8305-0ba8182282f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903494547 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2903494547
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.289758824
Short name T868
Test name
Test status
Simulation time 84850750 ps
CPU time 1.37 seconds
Started Aug 17 06:30:15 PM PDT 24
Finished Aug 17 06:30:17 PM PDT 24
Peak memory 215332 kb
Host smart-bb52d233-7a7c-4ec9-92b7-d28761bf038b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289758824 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.289758824
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1668334325
Short name T831
Test name
Test status
Simulation time 4619609456 ps
CPU time 41.29 seconds
Started Aug 17 06:30:23 PM PDT 24
Finished Aug 17 06:31:14 PM PDT 24
Peak memory 218100 kb
Host smart-a0ab4fd5-6f10-4c9d-989b-7a7ed81cd001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668334325 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1668334325
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2690579127
Short name T850
Test name
Test status
Simulation time 49016894 ps
CPU time 1.21 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 220356 kb
Host smart-502b5b03-7c4c-4ef2-a877-4a7180c2bbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690579127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2690579127
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1114572035
Short name T340
Test name
Test status
Simulation time 42683882 ps
CPU time 1.07 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:33 PM PDT 24
Peak memory 206872 kb
Host smart-cd46f7f1-d83d-45b9-80e4-3775ce0e63e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114572035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1114572035
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1099981447
Short name T190
Test name
Test status
Simulation time 179912855 ps
CPU time 0.88 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:25 PM PDT 24
Peak memory 215448 kb
Host smart-1b613449-a835-44c7-a4d3-feb9c6989b3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099981447 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1099981447
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1853880759
Short name T236
Test name
Test status
Simulation time 40323975 ps
CPU time 1.31 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 219752 kb
Host smart-e67c4f69-508f-43aa-bd1a-c5492ac40cf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853880759 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1853880759
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.571166912
Short name T907
Test name
Test status
Simulation time 32788885 ps
CPU time 1 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 224140 kb
Host smart-e74a7b93-2de6-48b7-a966-210e076cc60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571166912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.571166912
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.248623556
Short name T847
Test name
Test status
Simulation time 36757862 ps
CPU time 1.35 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:25 PM PDT 24
Peak memory 218492 kb
Host smart-b11820f6-6b5d-4a2f-bd5f-85dde2d260bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248623556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.248623556
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.102507908
Short name T522
Test name
Test status
Simulation time 25256797 ps
CPU time 0.96 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 215588 kb
Host smart-da225a11-2d4f-4a02-89c3-f5a0a48d433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102507908 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.102507908
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3528009761
Short name T221
Test name
Test status
Simulation time 51435008 ps
CPU time 0.91 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 215304 kb
Host smart-46ad5e48-dae4-400d-a65b-e8cbacf25f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528009761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3528009761
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1961789602
Short name T504
Test name
Test status
Simulation time 512947174 ps
CPU time 2.76 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 215356 kb
Host smart-71bef79f-544f-43f4-872d-37ac5da1d94e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961789602 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1961789602
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.274951933
Short name T218
Test name
Test status
Simulation time 1656590130 ps
CPU time 39.02 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 218164 kb
Host smart-95ea7e92-f713-4ad2-9911-a94ece1e49dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274951933 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.274951933
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.652859624
Short name T872
Test name
Test status
Simulation time 41713914 ps
CPU time 1.2 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 219184 kb
Host smart-16e82680-3aa0-4b17-9103-91f5de783e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652859624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.652859624
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1000240770
Short name T59
Test name
Test status
Simulation time 42566936 ps
CPU time 0.83 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 214804 kb
Host smart-8f706c33-192f-49f0-8403-a9d4025820e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000240770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1000240770
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2507055631
Short name T1
Test name
Test status
Simulation time 52268245 ps
CPU time 0.86 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 215396 kb
Host smart-abb76391-6ced-4403-8abf-4589438cc35d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507055631 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2507055631
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1591962932
Short name T623
Test name
Test status
Simulation time 33396741 ps
CPU time 1.43 seconds
Started Aug 17 06:30:32 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 218620 kb
Host smart-79e7ee1d-7fa5-4061-ad97-1858ab5a9895
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591962932 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1591962932
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.737160359
Short name T118
Test name
Test status
Simulation time 24745192 ps
CPU time 1.17 seconds
Started Aug 17 06:30:17 PM PDT 24
Finished Aug 17 06:30:19 PM PDT 24
Peak memory 220724 kb
Host smart-325da305-f790-4638-873c-86f9c2bd76ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737160359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.737160359
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1435387087
Short name T854
Test name
Test status
Simulation time 148221475 ps
CPU time 3.23 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 219200 kb
Host smart-5ace38ae-cb28-4ee6-9f12-c7853680efde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435387087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1435387087
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1007941958
Short name T716
Test name
Test status
Simulation time 50292552 ps
CPU time 0.94 seconds
Started Aug 17 06:30:41 PM PDT 24
Finished Aug 17 06:30:42 PM PDT 24
Peak memory 223948 kb
Host smart-693f4cfc-6c57-4b5a-8866-6fded499897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007941958 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1007941958
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.969714111
Short name T491
Test name
Test status
Simulation time 37496432 ps
CPU time 0.86 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 215316 kb
Host smart-5c83ead0-182d-4b9f-b486-445e33ac3dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969714111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.969714111
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2111788456
Short name T811
Test name
Test status
Simulation time 33253011 ps
CPU time 1.34 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 215364 kb
Host smart-877449ac-e0e6-4518-bd2d-f2b9610e2ef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111788456 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2111788456
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1210785304
Short name T590
Test name
Test status
Simulation time 1490325760 ps
CPU time 41.42 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:31:09 PM PDT 24
Peak memory 220224 kb
Host smart-d1e7e3f3-1444-48a0-867c-fd2ecc681831
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210785304 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1210785304
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3089752776
Short name T431
Test name
Test status
Simulation time 153757960 ps
CPU time 1.39 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:27 PM PDT 24
Peak memory 215704 kb
Host smart-0c575845-294b-439b-9ee0-794febbe30a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089752776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3089752776
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1600085119
Short name T346
Test name
Test status
Simulation time 45490923 ps
CPU time 0.82 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 206576 kb
Host smart-909d50bf-af35-4854-a9b8-740f414dbc68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600085119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1600085119
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3679675119
Short name T848
Test name
Test status
Simulation time 11008812 ps
CPU time 0.86 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 215388 kb
Host smart-f27f8c3c-b687-4948-90d7-9bfc5007d54b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679675119 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3679675119
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3298563396
Short name T779
Test name
Test status
Simulation time 123966295 ps
CPU time 1.01 seconds
Started Aug 17 06:30:18 PM PDT 24
Finished Aug 17 06:30:20 PM PDT 24
Peak memory 216856 kb
Host smart-9cc9c7e5-b979-4977-b00f-4da4599c3bd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298563396 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3298563396
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2382878089
Short name T769
Test name
Test status
Simulation time 19328394 ps
CPU time 1.23 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 224120 kb
Host smart-3fe5d4e5-eac5-4eca-922b-0a7132a4b335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382878089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2382878089
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3211824117
Short name T310
Test name
Test status
Simulation time 26899715 ps
CPU time 1.22 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 218480 kb
Host smart-7ed53d97-a4e6-43f2-b66d-036ee552096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211824117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3211824117
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_smoke.3102629133
Short name T749
Test name
Test status
Simulation time 16427850 ps
CPU time 0.93 seconds
Started Aug 17 06:30:22 PM PDT 24
Finished Aug 17 06:30:23 PM PDT 24
Peak memory 215360 kb
Host smart-bae619e9-8454-41a3-9bc5-20e4be47b766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102629133 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3102629133
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2044310142
Short name T784
Test name
Test status
Simulation time 745422041 ps
CPU time 3.96 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 217256 kb
Host smart-92a96333-1aea-403f-ae8a-8f86adecd7a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044310142 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2044310142
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_alert.3959507330
Short name T894
Test name
Test status
Simulation time 135923063 ps
CPU time 1.21 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 219276 kb
Host smart-645b81ed-7b5f-4c44-a9a5-4725202912d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959507330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3959507330
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.786257815
Short name T865
Test name
Test status
Simulation time 15920118 ps
CPU time 0.95 seconds
Started Aug 17 06:30:56 PM PDT 24
Finished Aug 17 06:31:02 PM PDT 24
Peak memory 214916 kb
Host smart-5256a0a1-ec14-4adb-a104-043f32fe97d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786257815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.786257815
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1856334682
Short name T330
Test name
Test status
Simulation time 13511552 ps
CPU time 1.05 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 207120 kb
Host smart-72068097-d671-48a5-963c-e1a17bca6309
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856334682 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1856334682
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3294052795
Short name T866
Test name
Test status
Simulation time 106750818 ps
CPU time 1.11 seconds
Started Aug 17 06:30:18 PM PDT 24
Finished Aug 17 06:30:19 PM PDT 24
Peak memory 216844 kb
Host smart-0ce284ff-3887-4aa2-8eab-e0ab2226e4d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294052795 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3294052795
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1884194947
Short name T188
Test name
Test status
Simulation time 51478981 ps
CPU time 1.02 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 218552 kb
Host smart-8d6e037b-8cac-4432-b7ba-47b048480472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884194947 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1884194947
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.891258314
Short name T367
Test name
Test status
Simulation time 203475297 ps
CPU time 1.09 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 217352 kb
Host smart-5781d3d4-6926-43cf-a8cd-1338e8cc9bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891258314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.891258314
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3304992229
Short name T688
Test name
Test status
Simulation time 23847376 ps
CPU time 1.16 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 224188 kb
Host smart-f879ffbd-1012-47dd-993b-3017690c9cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304992229 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3304992229
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2697971257
Short name T816
Test name
Test status
Simulation time 38723499 ps
CPU time 0.9 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:25 PM PDT 24
Peak memory 215336 kb
Host smart-b568e4fa-be7a-4dc7-9bf9-b32596216d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697971257 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2697971257
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2502590191
Short name T607
Test name
Test status
Simulation time 82105645 ps
CPU time 2.1 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 218556 kb
Host smart-4b8e2bc3-c366-4cd0-83d1-628550b0f948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502590191 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2502590191
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.132406287
Short name T216
Test name
Test status
Simulation time 1822564220 ps
CPU time 22.17 seconds
Started Aug 17 06:30:19 PM PDT 24
Finished Aug 17 06:30:41 PM PDT 24
Peak memory 218272 kb
Host smart-a7514902-bed4-4f67-8914-0883866c1156
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132406287 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.132406287
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3271507792
Short name T830
Test name
Test status
Simulation time 22006465 ps
CPU time 1.11 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 219844 kb
Host smart-6935ad08-f280-433b-a171-4dcad97d0a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271507792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3271507792
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.528863941
Short name T326
Test name
Test status
Simulation time 20857101 ps
CPU time 0.82 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 206596 kb
Host smart-c3fd2ca1-460d-4634-9b28-aae8838c6559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528863941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.528863941
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2037079396
Short name T69
Test name
Test status
Simulation time 19540682 ps
CPU time 0.82 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 215312 kb
Host smart-61cf6471-f420-4fd8-a106-e20ac5472178
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037079396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2037079396
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1106853877
Short name T146
Test name
Test status
Simulation time 65160288 ps
CPU time 1.02 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 217020 kb
Host smart-33a7240c-2e74-413c-bc7f-d09a7829755e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106853877 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1106853877
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_genbits.3359158441
Short name T314
Test name
Test status
Simulation time 55172080 ps
CPU time 1.25 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 218436 kb
Host smart-0f498c14-1a9f-49d5-a8b3-a10508a4d05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359158441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3359158441
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.228678876
Short name T821
Test name
Test status
Simulation time 29488927 ps
CPU time 0.94 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 215564 kb
Host smart-ff7e9431-f215-4637-9ad3-de8560fed8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228678876 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.228678876
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3353032897
Short name T898
Test name
Test status
Simulation time 39393671 ps
CPU time 0.89 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 207124 kb
Host smart-881c5726-37b4-446f-b41f-f13024f85a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353032897 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3353032897
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.838182626
Short name T292
Test name
Test status
Simulation time 224122427 ps
CPU time 4.63 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:33 PM PDT 24
Peak memory 217484 kb
Host smart-01df0d59-b9df-4f95-9a01-cc1f51fe083a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838182626 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.838182626
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_alert.2421021646
Short name T884
Test name
Test status
Simulation time 42012203 ps
CPU time 1.08 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 218688 kb
Host smart-e2eab3b1-1065-49c6-8476-759ce55c62a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421021646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2421021646
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3413527595
Short name T795
Test name
Test status
Simulation time 55207625 ps
CPU time 0.93 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 206804 kb
Host smart-47ba705b-5376-4ff8-a304-2397f57306f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413527595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3413527595
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3826958979
Short name T409
Test name
Test status
Simulation time 86963249 ps
CPU time 0.93 seconds
Started Aug 17 06:29:25 PM PDT 24
Finished Aug 17 06:29:26 PM PDT 24
Peak memory 215196 kb
Host smart-2ce1876d-2b1a-4c5d-954a-ac6422f51318
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826958979 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3826958979
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1856016195
Short name T693
Test name
Test status
Simulation time 28918439 ps
CPU time 1.1 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 215376 kb
Host smart-94754a9f-6d41-417f-a62e-dd932b34bd22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856016195 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1856016195
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1145964068
Short name T15
Test name
Test status
Simulation time 24388211 ps
CPU time 1.07 seconds
Started Aug 17 06:29:30 PM PDT 24
Finished Aug 17 06:29:31 PM PDT 24
Peak memory 224084 kb
Host smart-08c69b8a-79d6-4546-a8e1-8e2dcedead1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145964068 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1145964068
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1796224422
Short name T345
Test name
Test status
Simulation time 28483996 ps
CPU time 1.22 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 218496 kb
Host smart-059a5803-4717-4c01-90a0-fc8f428e1eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796224422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1796224422
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.74540492
Short name T40
Test name
Test status
Simulation time 86728178 ps
CPU time 0.85 seconds
Started Aug 17 06:29:36 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 215344 kb
Host smart-c1c939a6-7dc1-4dac-bdee-75a8b53d2be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74540492 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.74540492
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2981765611
Short name T26
Test name
Test status
Simulation time 45919106 ps
CPU time 0.91 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 207152 kb
Host smart-bd0e3080-32bc-4cf0-a434-ca208ed9454d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981765611 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2981765611
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3473722868
Short name T933
Test name
Test status
Simulation time 26998304 ps
CPU time 0.95 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 215324 kb
Host smart-172330d2-499b-4171-b03a-a0031a665a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473722868 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3473722868
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3584932568
Short name T536
Test name
Test status
Simulation time 1408573041 ps
CPU time 4.54 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 215452 kb
Host smart-035a65fc-c2ac-4566-a2fe-789d33761120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584932568 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3584932568
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1979511173
Short name T38
Test name
Test status
Simulation time 5051742050 ps
CPU time 33.42 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:30:09 PM PDT 24
Peak memory 218096 kb
Host smart-784a2342-a9dc-4672-9ca8-2e91806a6cb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979511173 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1979511173
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_alert.1291414219
Short name T122
Test name
Test status
Simulation time 89584625 ps
CPU time 1.17 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 218568 kb
Host smart-afeac6e1-f3db-4879-bb1e-d955a16f812a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291414219 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_alert.1291414219
Directory /workspace/50.edn_alert/latest

Test location /workspace/coverage/default/50.edn_err.3252975456
Short name T111
Test name
Test status
Simulation time 32512385 ps
CPU time 1.16 seconds
Started Aug 17 06:30:23 PM PDT 24
Finished Aug 17 06:30:25 PM PDT 24
Peak memory 229692 kb
Host smart-ef311628-9ba9-4181-afc5-bdd28e6a119d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252975456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3252975456
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2713383169
Short name T480
Test name
Test status
Simulation time 52341084 ps
CPU time 1.37 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 217548 kb
Host smart-6277c6bd-55d6-4751-9312-6aa652412b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713383169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2713383169
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_alert.1399313741
Short name T593
Test name
Test status
Simulation time 43664830 ps
CPU time 1.27 seconds
Started Aug 17 06:30:15 PM PDT 24
Finished Aug 17 06:30:16 PM PDT 24
Peak memory 218780 kb
Host smart-e0cdbc80-1093-4d73-93e4-c7d5fd65e19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399313741 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_alert.1399313741
Directory /workspace/51.edn_alert/latest

Test location /workspace/coverage/default/51.edn_err.966552169
Short name T782
Test name
Test status
Simulation time 165418730 ps
CPU time 1.01 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 218680 kb
Host smart-5aae8621-09f8-47d8-813c-e423ea8741c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966552169 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.966552169
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.136661054
Short name T301
Test name
Test status
Simulation time 89123814 ps
CPU time 1.55 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 218636 kb
Host smart-e2400f7f-e34d-477a-9884-b6264969634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136661054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.136661054
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_alert.1632543439
Short name T885
Test name
Test status
Simulation time 28060460 ps
CPU time 1.27 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 221252 kb
Host smart-2dc9f79f-2c93-4b3f-adca-f48e51bf5d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632543439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_alert.1632543439
Directory /workspace/52.edn_alert/latest

Test location /workspace/coverage/default/52.edn_err.1870513677
Short name T97
Test name
Test status
Simulation time 34129581 ps
CPU time 0.84 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 218476 kb
Host smart-d3f694c4-620e-46c4-afc5-6a898320d8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870513677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1870513677
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1463442953
Short name T896
Test name
Test status
Simulation time 44085041 ps
CPU time 1.59 seconds
Started Aug 17 06:30:21 PM PDT 24
Finished Aug 17 06:30:23 PM PDT 24
Peak memory 218732 kb
Host smart-b648c9f6-bcb7-4756-89c5-50fa97cb337c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463442953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1463442953
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_alert.1859003677
Short name T903
Test name
Test status
Simulation time 40766762 ps
CPU time 1.11 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 218660 kb
Host smart-e6205221-8ef6-4f9c-8641-1d860be6bd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859003677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_alert.1859003677
Directory /workspace/53.edn_alert/latest

Test location /workspace/coverage/default/53.edn_err.129529954
Short name T152
Test name
Test status
Simulation time 18676722 ps
CPU time 1.05 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:27 PM PDT 24
Peak memory 218424 kb
Host smart-afe2ace2-2ae1-4ab1-a7a5-e02a68cb5b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129529954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.129529954
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.678932925
Short name T243
Test name
Test status
Simulation time 48603422 ps
CPU time 1.81 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:37 PM PDT 24
Peak memory 218656 kb
Host smart-bbef547e-3589-43ec-adda-24bf15bffd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678932925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.678932925
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_alert.3448445077
Short name T139
Test name
Test status
Simulation time 47714590 ps
CPU time 1.18 seconds
Started Aug 17 06:30:37 PM PDT 24
Finished Aug 17 06:30:39 PM PDT 24
Peak memory 220696 kb
Host smart-8c1068ab-8834-4018-a28a-8db44fe263a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448445077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_alert.3448445077
Directory /workspace/54.edn_alert/latest

Test location /workspace/coverage/default/54.edn_err.2431933036
Short name T6
Test name
Test status
Simulation time 20772303 ps
CPU time 1.08 seconds
Started Aug 17 06:30:23 PM PDT 24
Finished Aug 17 06:30:24 PM PDT 24
Peak memory 219556 kb
Host smart-63f28156-c998-4fcd-867e-8ed22b2fa380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431933036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2431933036
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2639009219
Short name T915
Test name
Test status
Simulation time 123429403 ps
CPU time 3.05 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 220532 kb
Host smart-198db01e-8c76-46c0-9be4-bdb310a962e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639009219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2639009219
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_alert.399751980
Short name T626
Test name
Test status
Simulation time 65132053 ps
CPU time 1.05 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:25 PM PDT 24
Peak memory 220844 kb
Host smart-3d3d62a2-7d34-4301-879b-32591396202e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399751980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_alert.399751980
Directory /workspace/55.edn_alert/latest

Test location /workspace/coverage/default/55.edn_err.3908111307
Short name T935
Test name
Test status
Simulation time 21802547 ps
CPU time 1.18 seconds
Started Aug 17 06:30:44 PM PDT 24
Finished Aug 17 06:30:45 PM PDT 24
Peak memory 220024 kb
Host smart-f5a44796-a51f-46c4-b9a3-ada67759809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908111307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3908111307
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2924738179
Short name T45
Test name
Test status
Simulation time 360929593 ps
CPU time 4.06 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 217516 kb
Host smart-bae2f323-4a25-4382-a2ee-ad474a000f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924738179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2924738179
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_alert.523540400
Short name T287
Test name
Test status
Simulation time 260532996 ps
CPU time 1.41 seconds
Started Aug 17 06:30:38 PM PDT 24
Finished Aug 17 06:30:39 PM PDT 24
Peak memory 220564 kb
Host smart-3e8d7834-76fa-49d6-98ad-e90960795d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523540400 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_alert.523540400
Directory /workspace/56.edn_alert/latest

Test location /workspace/coverage/default/56.edn_err.2204872359
Short name T14
Test name
Test status
Simulation time 22245124 ps
CPU time 0.99 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 224288 kb
Host smart-f837ce98-0934-4c49-8261-3a30c2f7e7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204872359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2204872359
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.624269533
Short name T551
Test name
Test status
Simulation time 61880319 ps
CPU time 1.11 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 217476 kb
Host smart-7ca3ef92-95bb-41de-8609-184243a412e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624269533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.624269533
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_alert.2945328429
Short name T799
Test name
Test status
Simulation time 30960045 ps
CPU time 1.32 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 218604 kb
Host smart-b7d7691f-b14d-4b41-a30f-d5e1453c89f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945328429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_alert.2945328429
Directory /workspace/57.edn_alert/latest

Test location /workspace/coverage/default/57.edn_genbits.3762583071
Short name T298
Test name
Test status
Simulation time 196334900 ps
CPU time 1.05 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 217416 kb
Host smart-1e6a49e6-ac2b-43b6-8747-b3b48ec2c9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762583071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3762583071
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_alert.2800842183
Short name T327
Test name
Test status
Simulation time 135966713 ps
CPU time 1.18 seconds
Started Aug 17 06:30:21 PM PDT 24
Finished Aug 17 06:30:22 PM PDT 24
Peak memory 219040 kb
Host smart-fba0e258-0d14-4e61-8f77-eb2956281c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800842183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_alert.2800842183
Directory /workspace/58.edn_alert/latest

Test location /workspace/coverage/default/58.edn_err.3982119491
Short name T464
Test name
Test status
Simulation time 23909866 ps
CPU time 0.93 seconds
Started Aug 17 06:30:22 PM PDT 24
Finished Aug 17 06:30:23 PM PDT 24
Peak memory 218640 kb
Host smart-dd6b4653-3f90-4cf0-8e8d-ae370db3959c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982119491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3982119491
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2588685614
Short name T319
Test name
Test status
Simulation time 66258188 ps
CPU time 1.16 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 220440 kb
Host smart-2013d8aa-8b01-4f21-8f1f-8404757cc8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588685614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2588685614
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_alert.2029271212
Short name T79
Test name
Test status
Simulation time 83979841 ps
CPU time 1.18 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 218408 kb
Host smart-c6f8cbd4-e21a-48c5-a83d-38ec7c5a30d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029271212 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_alert.2029271212
Directory /workspace/59.edn_alert/latest

Test location /workspace/coverage/default/59.edn_err.2617049477
Short name T185
Test name
Test status
Simulation time 21457488 ps
CPU time 1.19 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 229776 kb
Host smart-d7e2dae5-300e-4a75-9376-64c737821bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617049477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2617049477
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3694190529
Short name T509
Test name
Test status
Simulation time 54730980 ps
CPU time 1.35 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 220504 kb
Host smart-11f756dd-269e-473e-b90f-0575198452f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694190529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3694190529
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2016542148
Short name T518
Test name
Test status
Simulation time 24167874 ps
CPU time 1.14 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 218640 kb
Host smart-e3bc4daa-fc05-4b26-8b47-1ea8f200fb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016542148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2016542148
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.722131165
Short name T809
Test name
Test status
Simulation time 19179879 ps
CPU time 0.99 seconds
Started Aug 17 06:29:25 PM PDT 24
Finished Aug 17 06:29:27 PM PDT 24
Peak memory 206820 kb
Host smart-7a03cc23-ba37-42ac-9c67-1acaef0196e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722131165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.722131165
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1729887646
Short name T193
Test name
Test status
Simulation time 12255422 ps
CPU time 0.91 seconds
Started Aug 17 06:29:36 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 215628 kb
Host smart-33e41f5c-f08c-4b56-bb41-f09e712b848f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729887646 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1729887646
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.71633573
Short name T142
Test name
Test status
Simulation time 34775407 ps
CPU time 1.11 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 216840 kb
Host smart-81ff5162-2aa7-4a4a-9000-b5720826d886
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71633573 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disa
ble_auto_req_mode.71633573
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.550190866
Short name T558
Test name
Test status
Simulation time 28874643 ps
CPU time 0.97 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 218540 kb
Host smart-31cfbf5f-d246-4a87-b465-e94e6ff7fbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550190866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.550190866
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.638017379
Short name T359
Test name
Test status
Simulation time 69531306 ps
CPU time 1.08 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 217372 kb
Host smart-0c571d03-319e-41ce-bf5d-121082fdd17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638017379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.638017379
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3551857
Short name T737
Test name
Test status
Simulation time 36054426 ps
CPU time 0.85 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 215292 kb
Host smart-39a31cda-b97a-4a05-91e1-becaffc30de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551857 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3551857
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1875048472
Short name T288
Test name
Test status
Simulation time 18137446 ps
CPU time 1.01 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 207292 kb
Host smart-933372b5-1963-4b21-99cb-8fbfc3a94b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875048472 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1875048472
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1048049499
Short name T964
Test name
Test status
Simulation time 15996434 ps
CPU time 1 seconds
Started Aug 17 06:29:30 PM PDT 24
Finished Aug 17 06:29:31 PM PDT 24
Peak memory 215352 kb
Host smart-65c99685-f975-4b39-ad57-32699b218933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048049499 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1048049499
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.4202912760
Short name T423
Test name
Test status
Simulation time 410743812 ps
CPU time 4.41 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 217352 kb
Host smart-eca13cf9-590f-4c9e-9f9c-99c1290a4907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202912760 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.4202912760
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/60.edn_alert.1895830167
Short name T485
Test name
Test status
Simulation time 215633331 ps
CPU time 1.06 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:25 PM PDT 24
Peak memory 219880 kb
Host smart-32639109-98ba-42e5-b499-dbeca5c85757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895830167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_alert.1895830167
Directory /workspace/60.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.2248920539
Short name T124
Test name
Test status
Simulation time 28995757 ps
CPU time 1.07 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 219764 kb
Host smart-60720997-f5bf-454d-9f8b-013aeb77ce85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248920539 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2248920539
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3737706186
Short name T399
Test name
Test status
Simulation time 64092355 ps
CPU time 1.22 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 217552 kb
Host smart-44d2948e-e309-47cf-b3bd-ac1fb980b280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737706186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3737706186
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3363651056
Short name T165
Test name
Test status
Simulation time 18707332 ps
CPU time 1.08 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 224132 kb
Host smart-38c73dfa-635a-4a86-bd17-fbcee620c9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363651056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3363651056
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2464369816
Short name T438
Test name
Test status
Simulation time 140245257 ps
CPU time 0.99 seconds
Started Aug 17 06:30:38 PM PDT 24
Finished Aug 17 06:30:40 PM PDT 24
Peak memory 217584 kb
Host smart-44cd7d22-45f4-4522-a906-ba56086d0faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464369816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2464369816
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_alert.4089766074
Short name T279
Test name
Test status
Simulation time 336830078 ps
CPU time 1.49 seconds
Started Aug 17 06:31:00 PM PDT 24
Finished Aug 17 06:31:01 PM PDT 24
Peak memory 219756 kb
Host smart-ad1f7e6a-a943-48ef-bbe5-f40e039c239a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089766074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_alert.4089766074
Directory /workspace/62.edn_alert/latest

Test location /workspace/coverage/default/62.edn_err.2089195685
Short name T844
Test name
Test status
Simulation time 49290047 ps
CPU time 0.98 seconds
Started Aug 17 06:31:02 PM PDT 24
Finished Aug 17 06:31:03 PM PDT 24
Peak memory 219824 kb
Host smart-efb9bb0e-2628-406e-8fb9-b490526c9334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089195685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2089195685
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.970218881
Short name T835
Test name
Test status
Simulation time 85213548 ps
CPU time 1.39 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 220288 kb
Host smart-aba068b1-c189-41f9-86b7-a1927a2972a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970218881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.970218881
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_alert.936389281
Short name T817
Test name
Test status
Simulation time 37483315 ps
CPU time 1.15 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 218816 kb
Host smart-0094b0da-90ad-40b8-af13-0da0562c8798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936389281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_alert.936389281
Directory /workspace/63.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.2702106573
Short name T383
Test name
Test status
Simulation time 73059989 ps
CPU time 1.18 seconds
Started Aug 17 06:30:47 PM PDT 24
Finished Aug 17 06:30:48 PM PDT 24
Peak memory 219760 kb
Host smart-986fa807-4d7e-49a8-965e-ed9eae9c5730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702106573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2702106573
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2526132058
Short name T683
Test name
Test status
Simulation time 39509172 ps
CPU time 1.37 seconds
Started Aug 17 06:30:42 PM PDT 24
Finished Aug 17 06:30:43 PM PDT 24
Peak memory 217196 kb
Host smart-45c7c1a7-4682-44a1-b3b9-ec7839eb5ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526132058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2526132058
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_alert.682294992
Short name T204
Test name
Test status
Simulation time 46643275 ps
CPU time 1.25 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 219812 kb
Host smart-8841351e-4a2e-473b-aa48-57c9b6777e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682294992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_alert.682294992
Directory /workspace/64.edn_alert/latest

Test location /workspace/coverage/default/64.edn_err.379259752
Short name T531
Test name
Test status
Simulation time 33402863 ps
CPU time 0.87 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 218136 kb
Host smart-806ea7e6-968b-4f96-800c-dcbee633983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379259752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.379259752
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2531381609
Short name T808
Test name
Test status
Simulation time 72413028 ps
CPU time 1.03 seconds
Started Aug 17 06:30:47 PM PDT 24
Finished Aug 17 06:30:48 PM PDT 24
Peak memory 217272 kb
Host smart-6940f451-cacf-4c0b-b481-55c87629cc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531381609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2531381609
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_alert.3524842433
Short name T768
Test name
Test status
Simulation time 45850578 ps
CPU time 1.11 seconds
Started Aug 17 06:30:41 PM PDT 24
Finished Aug 17 06:30:42 PM PDT 24
Peak memory 218604 kb
Host smart-8a91e5dd-c91a-47f5-9e2f-2c8446f86e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524842433 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_alert.3524842433
Directory /workspace/65.edn_alert/latest

Test location /workspace/coverage/default/65.edn_err.2440455343
Short name T729
Test name
Test status
Simulation time 34661946 ps
CPU time 0.85 seconds
Started Aug 17 06:31:00 PM PDT 24
Finished Aug 17 06:31:01 PM PDT 24
Peak memory 218492 kb
Host smart-46410414-b436-430a-8535-fa4a7d361aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440455343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2440455343
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.699515458
Short name T54
Test name
Test status
Simulation time 72150374 ps
CPU time 1.22 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 218788 kb
Host smart-dcdf502c-71c3-492a-989e-c1c95c609b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699515458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.699515458
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_alert.994095523
Short name T30
Test name
Test status
Simulation time 91311110 ps
CPU time 1.18 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 220168 kb
Host smart-646a1e8b-2298-493a-8bb7-29b577309511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994095523 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_alert.994095523
Directory /workspace/66.edn_alert/latest

Test location /workspace/coverage/default/66.edn_err.2152394268
Short name T731
Test name
Test status
Simulation time 18643462 ps
CPU time 1.06 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 218600 kb
Host smart-829ab70e-abb3-43f5-b7c2-1fa032037f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152394268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2152394268
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3330501935
Short name T900
Test name
Test status
Simulation time 35282984 ps
CPU time 1.37 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 218460 kb
Host smart-e642eede-1bd5-44e2-be5f-d465842c8948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330501935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3330501935
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_alert.1459009800
Short name T792
Test name
Test status
Simulation time 45534298 ps
CPU time 1.16 seconds
Started Aug 17 06:30:31 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 219248 kb
Host smart-139645b5-0819-4a30-9031-b3a830b44773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459009800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_alert.1459009800
Directory /workspace/67.edn_alert/latest

Test location /workspace/coverage/default/67.edn_err.1649199460
Short name T49
Test name
Test status
Simulation time 20854109 ps
CPU time 1.12 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:35 PM PDT 24
Peak memory 224092 kb
Host smart-d428058a-6aee-4d37-b9d5-6b7ee45c66ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649199460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1649199460
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.591463600
Short name T622
Test name
Test status
Simulation time 112163503 ps
CPU time 1.05 seconds
Started Aug 17 06:30:41 PM PDT 24
Finished Aug 17 06:30:42 PM PDT 24
Peak memory 217452 kb
Host smart-d5ca7b16-7c82-401f-851c-76d9a6686964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591463600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.591463600
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_alert.2376581687
Short name T425
Test name
Test status
Simulation time 38434419 ps
CPU time 1.32 seconds
Started Aug 17 06:30:47 PM PDT 24
Finished Aug 17 06:30:48 PM PDT 24
Peak memory 215764 kb
Host smart-30d7be04-790d-4eb6-8478-a15378e5c41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376581687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_alert.2376581687
Directory /workspace/68.edn_alert/latest

Test location /workspace/coverage/default/68.edn_err.191386418
Short name T962
Test name
Test status
Simulation time 20206104 ps
CPU time 1.02 seconds
Started Aug 17 06:30:45 PM PDT 24
Finished Aug 17 06:30:47 PM PDT 24
Peak memory 218540 kb
Host smart-c37f9078-2bbe-47c7-8beb-a197a0e30d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191386418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.191386418
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2418730788
Short name T829
Test name
Test status
Simulation time 49790642 ps
CPU time 1.09 seconds
Started Aug 17 06:30:34 PM PDT 24
Finished Aug 17 06:30:35 PM PDT 24
Peak memory 217368 kb
Host smart-8a06ed17-c871-4de3-8e34-ae4a5f73e0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418730788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2418730788
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.425604380
Short name T337
Test name
Test status
Simulation time 31615561 ps
CPU time 1.19 seconds
Started Aug 17 06:30:34 PM PDT 24
Finished Aug 17 06:30:35 PM PDT 24
Peak memory 220772 kb
Host smart-6b70293b-1372-498c-8342-7d1627b2bb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425604380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.425604380
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1067699053
Short name T952
Test name
Test status
Simulation time 60397043 ps
CPU time 1.3 seconds
Started Aug 17 06:30:58 PM PDT 24
Finished Aug 17 06:31:00 PM PDT 24
Peak memory 217312 kb
Host smart-072ece09-fdcc-47ac-8a09-2225181a2a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067699053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1067699053
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3404317000
Short name T101
Test name
Test status
Simulation time 51869351 ps
CPU time 1.22 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 220508 kb
Host smart-67c498e0-2219-4241-9b89-be5afc357df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404317000 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3404317000
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4163091265
Short name T540
Test name
Test status
Simulation time 13963576 ps
CPU time 0.93 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 206724 kb
Host smart-111cb961-9447-4c15-99b7-82eb1febe241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163091265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4163091265
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1518056769
Short name T378
Test name
Test status
Simulation time 15531347 ps
CPU time 0.95 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 207072 kb
Host smart-f21cf821-c003-4546-9d8a-69a709ef3704
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518056769 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1518056769
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3691987254
Short name T815
Test name
Test status
Simulation time 84465994 ps
CPU time 1.1 seconds
Started Aug 17 06:29:25 PM PDT 24
Finished Aug 17 06:29:26 PM PDT 24
Peak memory 218616 kb
Host smart-21df571e-00e9-4058-853f-4f4a244bbb06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691987254 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3691987254
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.4250846311
Short name T852
Test name
Test status
Simulation time 25119844 ps
CPU time 1.15 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 220696 kb
Host smart-29d09eee-a232-4c68-b7c0-0c9abe32f599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250846311 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4250846311
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.72667664
Short name T43
Test name
Test status
Simulation time 90800161 ps
CPU time 1.01 seconds
Started Aug 17 06:29:26 PM PDT 24
Finished Aug 17 06:29:27 PM PDT 24
Peak memory 215368 kb
Host smart-db6b4e1f-ed47-44b6-bcd9-8dd7f043fd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72667664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.72667664
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2875223473
Short name T621
Test name
Test status
Simulation time 116373365 ps
CPU time 0.86 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 215520 kb
Host smart-49d03074-bc5e-47b8-8052-89f761cb718d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875223473 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2875223473
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3014207405
Short name T733
Test name
Test status
Simulation time 149140043 ps
CPU time 0.88 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 207140 kb
Host smart-d1e488bd-2c09-4320-93b3-934f0012f360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014207405 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3014207405
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.801396568
Short name T882
Test name
Test status
Simulation time 95689767 ps
CPU time 0.82 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 215216 kb
Host smart-583cfa01-7d01-4fc7-b68b-39ec0b01beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801396568 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.801396568
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2615699846
Short name T790
Test name
Test status
Simulation time 1770160938 ps
CPU time 3.7 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 215284 kb
Host smart-239905d4-1a40-4520-94ac-2f905c53a4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615699846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2615699846
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/70.edn_alert.2334055436
Short name T883
Test name
Test status
Simulation time 182037984 ps
CPU time 1.32 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 215748 kb
Host smart-e9a43532-0c25-4054-aa5d-f4103a45e7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334055436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_alert.2334055436
Directory /workspace/70.edn_alert/latest

Test location /workspace/coverage/default/70.edn_err.3265609454
Short name T151
Test name
Test status
Simulation time 34305840 ps
CPU time 0.88 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 217220 kb
Host smart-e225b112-c560-43d1-bfd4-f99dee28e935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265609454 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3265609454
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1317897002
Short name T941
Test name
Test status
Simulation time 44399480 ps
CPU time 1.56 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 218656 kb
Host smart-ba5ec495-b610-43f5-880d-24266e74bec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317897002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1317897002
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_alert.2160134550
Short name T488
Test name
Test status
Simulation time 26251568 ps
CPU time 1.19 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:35 PM PDT 24
Peak memory 221056 kb
Host smart-6846dfee-a7c6-4d00-a181-bfdb66923038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160134550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_alert.2160134550
Directory /workspace/71.edn_alert/latest

Test location /workspace/coverage/default/71.edn_err.2287877515
Short name T486
Test name
Test status
Simulation time 21722295 ps
CPU time 0.93 seconds
Started Aug 17 06:30:38 PM PDT 24
Finished Aug 17 06:30:39 PM PDT 24
Peak memory 218488 kb
Host smart-9b4fd66b-772b-4481-a93d-614e4d6a287f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287877515 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2287877515
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.283177096
Short name T637
Test name
Test status
Simulation time 77534703 ps
CPU time 1.16 seconds
Started Aug 17 06:31:02 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 217464 kb
Host smart-64723790-84b9-4720-b2d1-95eb914a7fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283177096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.283177096
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_alert.854946685
Short name T237
Test name
Test status
Simulation time 68029240 ps
CPU time 1.21 seconds
Started Aug 17 06:31:06 PM PDT 24
Finished Aug 17 06:31:07 PM PDT 24
Peak memory 220824 kb
Host smart-cafb6c81-dbfa-4134-a8df-3abf8660ce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854946685 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_alert.854946685
Directory /workspace/72.edn_alert/latest

Test location /workspace/coverage/default/72.edn_err.3118417633
Short name T960
Test name
Test status
Simulation time 55595664 ps
CPU time 1.02 seconds
Started Aug 17 06:30:36 PM PDT 24
Finished Aug 17 06:30:37 PM PDT 24
Peak memory 220668 kb
Host smart-e7e0e3cd-057b-45cd-8915-c398c1762e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118417633 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3118417633
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2359282845
Short name T863
Test name
Test status
Simulation time 41768408 ps
CPU time 1.06 seconds
Started Aug 17 06:30:32 PM PDT 24
Finished Aug 17 06:30:33 PM PDT 24
Peak memory 217336 kb
Host smart-d3eb5f27-4009-4f01-8e1d-5e8c7497c238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359282845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2359282845
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_alert.1818170333
Short name T938
Test name
Test status
Simulation time 76637587 ps
CPU time 1.07 seconds
Started Aug 17 06:30:58 PM PDT 24
Finished Aug 17 06:30:59 PM PDT 24
Peak memory 219964 kb
Host smart-2d063e6e-f44f-4d64-814e-eb4629ed0cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818170333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_alert.1818170333
Directory /workspace/73.edn_alert/latest

Test location /workspace/coverage/default/73.edn_err.1885361734
Short name T532
Test name
Test status
Simulation time 20645578 ps
CPU time 0.94 seconds
Started Aug 17 06:31:08 PM PDT 24
Finished Aug 17 06:31:09 PM PDT 24
Peak memory 218356 kb
Host smart-1182c50c-8573-4fa6-b592-9a8a0914cdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885361734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1885361734
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/74.edn_alert.1931213590
Short name T803
Test name
Test status
Simulation time 96547182 ps
CPU time 1.08 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 219808 kb
Host smart-74f8c46e-a3fc-4a41-aa54-83c67721a1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931213590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_alert.1931213590
Directory /workspace/74.edn_alert/latest

Test location /workspace/coverage/default/74.edn_err.3685439202
Short name T528
Test name
Test status
Simulation time 28835139 ps
CPU time 0.88 seconds
Started Aug 17 06:30:31 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 218308 kb
Host smart-e72bb81b-ed09-4deb-94e6-21a98b9badf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685439202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3685439202
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.50118010
Short name T640
Test name
Test status
Simulation time 64392162 ps
CPU time 1.02 seconds
Started Aug 17 06:30:56 PM PDT 24
Finished Aug 17 06:30:57 PM PDT 24
Peak memory 217324 kb
Host smart-82b70de6-94f1-4107-bb48-a7935103581c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50118010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.50118010
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_alert.579706608
Short name T630
Test name
Test status
Simulation time 93899827 ps
CPU time 1.17 seconds
Started Aug 17 06:30:36 PM PDT 24
Finished Aug 17 06:30:37 PM PDT 24
Peak memory 219752 kb
Host smart-4af33686-3131-44e9-8cd9-95172a767c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579706608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_alert.579706608
Directory /workspace/75.edn_alert/latest

Test location /workspace/coverage/default/75.edn_err.3957751909
Short name T350
Test name
Test status
Simulation time 20780746 ps
CPU time 0.95 seconds
Started Aug 17 06:30:31 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 218508 kb
Host smart-74043101-2f2a-4ab5-bbd6-61b57fddfbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957751909 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3957751909
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.388199926
Short name T351
Test name
Test status
Simulation time 124774102 ps
CPU time 1.02 seconds
Started Aug 17 06:30:38 PM PDT 24
Finished Aug 17 06:30:40 PM PDT 24
Peak memory 217572 kb
Host smart-484bead5-b5fa-4695-bc46-e7663024b0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388199926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.388199926
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.1329762799
Short name T159
Test name
Test status
Simulation time 29981541 ps
CPU time 0.92 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 223960 kb
Host smart-a84e0c37-92d6-4ef5-b292-fd955880e9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329762799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1329762799
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1881746854
Short name T405
Test name
Test status
Simulation time 55889466 ps
CPU time 2.04 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:27 PM PDT 24
Peak memory 215364 kb
Host smart-0c034d24-9bcd-4634-a651-dbb5f8159911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881746854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1881746854
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_alert.2128676939
Short name T183
Test name
Test status
Simulation time 70853766 ps
CPU time 1.12 seconds
Started Aug 17 06:30:35 PM PDT 24
Finished Aug 17 06:30:37 PM PDT 24
Peak memory 219676 kb
Host smart-11b41615-59a7-4e3c-ae86-76128e49bc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128676939 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_alert.2128676939
Directory /workspace/77.edn_alert/latest

Test location /workspace/coverage/default/77.edn_err.1600351583
Short name T173
Test name
Test status
Simulation time 25320902 ps
CPU time 0.93 seconds
Started Aug 17 06:30:31 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 218484 kb
Host smart-2d7a30da-53e4-43f4-8855-e2d0c6944fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600351583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1600351583
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3310430805
Short name T395
Test name
Test status
Simulation time 32053759 ps
CPU time 1.28 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 218880 kb
Host smart-ace9de73-eb70-47c8-8ad9-d5ed7dc425e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310430805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3310430805
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_alert.4265586633
Short name T541
Test name
Test status
Simulation time 39523024 ps
CPU time 1.13 seconds
Started Aug 17 06:30:48 PM PDT 24
Finished Aug 17 06:30:49 PM PDT 24
Peak memory 219288 kb
Host smart-8c8ca8c5-9879-420a-a032-cd72088a5257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265586633 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_alert.4265586633
Directory /workspace/78.edn_alert/latest

Test location /workspace/coverage/default/78.edn_err.1291734276
Short name T820
Test name
Test status
Simulation time 20642399 ps
CPU time 1.02 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 218444 kb
Host smart-10ad9345-4e9a-420f-81f3-98be2ccec8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291734276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1291734276
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.556196072
Short name T424
Test name
Test status
Simulation time 48276634 ps
CPU time 1.18 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 217340 kb
Host smart-5c4f670f-9b77-47b5-9b33-57944a327f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556196072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.556196072
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_alert.1896337505
Short name T248
Test name
Test status
Simulation time 29493465 ps
CPU time 1.27 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 218664 kb
Host smart-a3bcaefa-f2ab-4eb1-8aef-c12d4688d31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896337505 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_alert.1896337505
Directory /workspace/79.edn_alert/latest

Test location /workspace/coverage/default/79.edn_err.2227749136
Short name T546
Test name
Test status
Simulation time 90682300 ps
CPU time 1 seconds
Started Aug 17 06:30:36 PM PDT 24
Finished Aug 17 06:30:38 PM PDT 24
Peak memory 219832 kb
Host smart-c97bf948-fe50-4a01-8deb-56afcebc6d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227749136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2227749136
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3297161193
Short name T271
Test name
Test status
Simulation time 78475390 ps
CPU time 2.52 seconds
Started Aug 17 06:30:42 PM PDT 24
Finished Aug 17 06:30:45 PM PDT 24
Peak memory 220428 kb
Host smart-81518c08-7a87-4676-8620-e1e0c746244a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297161193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3297161193
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2361901525
Short name T244
Test name
Test status
Simulation time 90463013 ps
CPU time 1.08 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:33 PM PDT 24
Peak memory 220612 kb
Host smart-1b068e89-2fa3-491e-8301-a07382fa6f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361901525 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2361901525
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.734157695
Short name T950
Test name
Test status
Simulation time 36804441 ps
CPU time 0.83 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 206456 kb
Host smart-148c2e4c-e82f-4fb7-84d0-20bd74b90123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734157695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.734157695
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3702850094
Short name T605
Test name
Test status
Simulation time 52866294 ps
CPU time 0.88 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 215184 kb
Host smart-e332cb0a-b724-41fa-98ed-35383602d9aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702850094 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3702850094
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1925026425
Short name T147
Test name
Test status
Simulation time 45185272 ps
CPU time 1.19 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:39 PM PDT 24
Peak memory 216756 kb
Host smart-38bdcf8f-8d04-47d9-bffa-fe6cfd3423d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925026425 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1925026425
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1684379939
Short name T674
Test name
Test status
Simulation time 19580597 ps
CPU time 1.04 seconds
Started Aug 17 06:29:36 PM PDT 24
Finished Aug 17 06:29:37 PM PDT 24
Peak memory 218636 kb
Host smart-2de15a5a-570a-4e3d-b585-18c0f6aff32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684379939 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1684379939
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2477959914
Short name T311
Test name
Test status
Simulation time 36248597 ps
CPU time 1.36 seconds
Started Aug 17 06:29:40 PM PDT 24
Finished Aug 17 06:29:42 PM PDT 24
Peak memory 220040 kb
Host smart-4ff49993-1d04-4e12-97eb-fb674b0adad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477959914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2477959914
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3736754836
Short name T442
Test name
Test status
Simulation time 40939507 ps
CPU time 0.87 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 215384 kb
Host smart-f89f6c13-a132-4832-b2fc-4940a6b47ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736754836 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3736754836
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.231739304
Short name T774
Test name
Test status
Simulation time 19843211 ps
CPU time 0.9 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 207188 kb
Host smart-6a26b42c-e6bc-4f1b-a9d1-2f64509b9f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231739304 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.231739304
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3456534262
Short name T772
Test name
Test status
Simulation time 29090096 ps
CPU time 0.95 seconds
Started Aug 17 06:29:35 PM PDT 24
Finished Aug 17 06:29:36 PM PDT 24
Peak memory 215544 kb
Host smart-daed4f05-1dfa-4af4-ad48-b86374b78ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456534262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3456534262
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.343567286
Short name T908
Test name
Test status
Simulation time 1457764785 ps
CPU time 2.95 seconds
Started Aug 17 06:29:38 PM PDT 24
Finished Aug 17 06:29:41 PM PDT 24
Peak memory 217476 kb
Host smart-496a3437-622b-4962-a7dc-6b427f4a65f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343567286 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.343567286
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/80.edn_err.1707699139
Short name T153
Test name
Test status
Simulation time 44053079 ps
CPU time 1.18 seconds
Started Aug 17 06:30:47 PM PDT 24
Finished Aug 17 06:30:48 PM PDT 24
Peak memory 219756 kb
Host smart-cbd580a0-ecbc-4d86-815e-1014d3dd4a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707699139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1707699139
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1338150781
Short name T702
Test name
Test status
Simulation time 96668242 ps
CPU time 1.19 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 217164 kb
Host smart-652ecc87-1874-46de-9601-9bb3b8676a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338150781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1338150781
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_alert.1898995103
Short name T246
Test name
Test status
Simulation time 29004557 ps
CPU time 1.33 seconds
Started Aug 17 06:30:25 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 219844 kb
Host smart-0a613f9b-6501-4e8a-967f-74161d571299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898995103 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_alert.1898995103
Directory /workspace/81.edn_alert/latest

Test location /workspace/coverage/default/81.edn_err.2908863678
Short name T140
Test name
Test status
Simulation time 25527461 ps
CPU time 1.2 seconds
Started Aug 17 06:30:59 PM PDT 24
Finished Aug 17 06:31:01 PM PDT 24
Peak memory 220720 kb
Host smart-afa687bc-db72-4a3a-b2ae-2c3a8cedcfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908863678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2908863678
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1102524731
Short name T756
Test name
Test status
Simulation time 42666810 ps
CPU time 1.06 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 217328 kb
Host smart-08a6105b-86c8-48a1-9ead-608b85b6bd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102524731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1102524731
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_alert.2643002918
Short name T951
Test name
Test status
Simulation time 23542123 ps
CPU time 1.12 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 218608 kb
Host smart-43efb919-f0ae-45eb-ac85-c17ded32915d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643002918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_alert.2643002918
Directory /workspace/82.edn_alert/latest

Test location /workspace/coverage/default/82.edn_err.1383064693
Short name T155
Test name
Test status
Simulation time 35658861 ps
CPU time 0.98 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 223904 kb
Host smart-17ae6b26-8ec3-4da2-9103-f3c30646dd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383064693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1383064693
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1698540677
Short name T647
Test name
Test status
Simulation time 43054622 ps
CPU time 1.46 seconds
Started Aug 17 06:30:35 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 218616 kb
Host smart-37cb9619-3dac-4f7e-90d1-7514110f9fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698540677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1698540677
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_alert.1881131716
Short name T537
Test name
Test status
Simulation time 273703747 ps
CPU time 1.11 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 218820 kb
Host smart-6eb29a19-14fd-4035-b4de-b76b384ddecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881131716 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_alert.1881131716
Directory /workspace/83.edn_alert/latest

Test location /workspace/coverage/default/83.edn_err.1330715153
Short name T336
Test name
Test status
Simulation time 19065693 ps
CPU time 1.03 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 218372 kb
Host smart-b601ca50-ba06-440e-9e51-af344911fc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330715153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1330715153
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3078348187
Short name T519
Test name
Test status
Simulation time 60952428 ps
CPU time 1.24 seconds
Started Aug 17 06:30:24 PM PDT 24
Finished Aug 17 06:30:25 PM PDT 24
Peak memory 218544 kb
Host smart-9a92dee3-01c7-4dcb-8a0d-09955a4bc720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078348187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3078348187
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_alert.3702101876
Short name T579
Test name
Test status
Simulation time 105333574 ps
CPU time 1.18 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 218696 kb
Host smart-52a04a71-db9a-4c31-be1b-a8fb6ab78706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702101876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_alert.3702101876
Directory /workspace/84.edn_alert/latest

Test location /workspace/coverage/default/84.edn_err.3037140897
Short name T549
Test name
Test status
Simulation time 35588186 ps
CPU time 0.89 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 223908 kb
Host smart-16ac14f6-de49-4209-a26a-9e1b3c7b0dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037140897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3037140897
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3772118921
Short name T410
Test name
Test status
Simulation time 31809674 ps
CPU time 1.23 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:35 PM PDT 24
Peak memory 217152 kb
Host smart-7b4017ac-781b-466a-91ef-4ea95c02aa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772118921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3772118921
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_alert.639992921
Short name T249
Test name
Test status
Simulation time 58448455 ps
CPU time 1.25 seconds
Started Aug 17 06:30:34 PM PDT 24
Finished Aug 17 06:30:40 PM PDT 24
Peak memory 215724 kb
Host smart-88fb031d-75a1-4087-8711-000cc6d0c716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639992921 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_alert.639992921
Directory /workspace/85.edn_alert/latest

Test location /workspace/coverage/default/85.edn_err.3258486842
Short name T667
Test name
Test status
Simulation time 28544926 ps
CPU time 1.34 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 225232 kb
Host smart-edcf0d2d-df97-4631-b0e7-998ea7e3b5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258486842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3258486842
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.816183264
Short name T643
Test name
Test status
Simulation time 33234301 ps
CPU time 1.23 seconds
Started Aug 17 06:30:34 PM PDT 24
Finished Aug 17 06:30:35 PM PDT 24
Peak memory 217392 kb
Host smart-0e627f30-ed8b-4214-8bd0-63d85bcc2e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816183264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.816183264
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_alert.1311925145
Short name T746
Test name
Test status
Simulation time 27815944 ps
CPU time 1.21 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 220740 kb
Host smart-0d97e219-1423-4eb2-bc52-bece3445ece8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311925145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_alert.1311925145
Directory /workspace/86.edn_alert/latest

Test location /workspace/coverage/default/86.edn_err.2804584854
Short name T195
Test name
Test status
Simulation time 18263918 ps
CPU time 1.06 seconds
Started Aug 17 06:30:50 PM PDT 24
Finished Aug 17 06:30:51 PM PDT 24
Peak memory 218580 kb
Host smart-26faca6a-1b07-43b0-8948-9b918311054c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804584854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2804584854
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2192318215
Short name T360
Test name
Test status
Simulation time 107978305 ps
CPU time 1.12 seconds
Started Aug 17 06:30:38 PM PDT 24
Finished Aug 17 06:30:39 PM PDT 24
Peak memory 218816 kb
Host smart-16c65a72-5a1d-4561-b8d3-f882e0cb643a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192318215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2192318215
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_alert.2239915958
Short name T475
Test name
Test status
Simulation time 78362853 ps
CPU time 1.14 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 219744 kb
Host smart-8f43d5ae-08af-4ad0-84e5-f988eb3ffdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239915958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_alert.2239915958
Directory /workspace/87.edn_alert/latest

Test location /workspace/coverage/default/87.edn_err.2841511805
Short name T634
Test name
Test status
Simulation time 74554709 ps
CPU time 1.19 seconds
Started Aug 17 06:30:34 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 225764 kb
Host smart-647231cb-fad6-4a7f-9c6f-6c21e324e57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841511805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2841511805
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.958943587
Short name T542
Test name
Test status
Simulation time 139830157 ps
CPU time 0.99 seconds
Started Aug 17 06:30:58 PM PDT 24
Finished Aug 17 06:30:59 PM PDT 24
Peak memory 217440 kb
Host smart-0e8e86ed-cf72-435a-aaf7-53e9661f7615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958943587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.958943587
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_alert.2013057313
Short name T342
Test name
Test status
Simulation time 49248446 ps
CPU time 1.18 seconds
Started Aug 17 06:30:26 PM PDT 24
Finished Aug 17 06:30:28 PM PDT 24
Peak memory 220632 kb
Host smart-535ae8ff-bbab-4292-ba30-e456e47cd155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013057313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_alert.2013057313
Directory /workspace/88.edn_alert/latest

Test location /workspace/coverage/default/88.edn_err.1291985000
Short name T289
Test name
Test status
Simulation time 131319696 ps
CPU time 0.96 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 219484 kb
Host smart-d4a6c3ba-87ac-4232-b926-17698ce0e7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291985000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1291985000
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3114543908
Short name T441
Test name
Test status
Simulation time 59144014 ps
CPU time 1.39 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 218900 kb
Host smart-3bc76584-9510-478d-b402-a25f169ab531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114543908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3114543908
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_alert.3467706055
Short name T390
Test name
Test status
Simulation time 68997518 ps
CPU time 1.08 seconds
Started Aug 17 06:30:36 PM PDT 24
Finished Aug 17 06:30:38 PM PDT 24
Peak memory 220388 kb
Host smart-8b5abac3-2a21-43c1-9bc2-ba0c1cf2f725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467706055 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_alert.3467706055
Directory /workspace/89.edn_alert/latest

Test location /workspace/coverage/default/89.edn_err.2435978019
Short name T53
Test name
Test status
Simulation time 24918653 ps
CPU time 1.2 seconds
Started Aug 17 06:30:36 PM PDT 24
Finished Aug 17 06:30:38 PM PDT 24
Peak memory 224116 kb
Host smart-dc1cb232-d142-4c6a-ac1b-abaa112f0a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435978019 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2435978019
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2298056065
Short name T339
Test name
Test status
Simulation time 33585030 ps
CPU time 1.33 seconds
Started Aug 17 06:30:37 PM PDT 24
Finished Aug 17 06:30:39 PM PDT 24
Peak memory 217292 kb
Host smart-8b0be81f-1242-47b1-bdf8-577674fe276c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298056065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2298056065
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3910945126
Short name T80
Test name
Test status
Simulation time 58278160 ps
CPU time 1.14 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 219776 kb
Host smart-4d31e868-4933-40c0-bd27-3fa6e562c19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910945126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3910945126
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2011303564
Short name T881
Test name
Test status
Simulation time 55815010 ps
CPU time 0.94 seconds
Started Aug 17 06:29:34 PM PDT 24
Finished Aug 17 06:29:35 PM PDT 24
Peak memory 215220 kb
Host smart-21de0dd6-b356-480f-bd81-dd20d6aa282d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011303564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2011303564
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.379418288
Short name T797
Test name
Test status
Simulation time 13750120 ps
CPU time 0.97 seconds
Started Aug 17 06:29:26 PM PDT 24
Finished Aug 17 06:29:27 PM PDT 24
Peak memory 215356 kb
Host smart-80887810-76ae-4b06-8989-caba6fdcc05a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379418288 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.379418288
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1201127717
Short name T434
Test name
Test status
Simulation time 31295485 ps
CPU time 1.23 seconds
Started Aug 17 06:29:40 PM PDT 24
Finished Aug 17 06:29:41 PM PDT 24
Peak memory 216900 kb
Host smart-ecfc1a40-df8c-4675-962f-ccd4623eed94
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201127717 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1201127717
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2350402692
Short name T52
Test name
Test status
Simulation time 18269691 ps
CPU time 1.11 seconds
Started Aug 17 06:29:31 PM PDT 24
Finished Aug 17 06:29:32 PM PDT 24
Peak memory 224200 kb
Host smart-0429c64a-93ab-4630-a0d3-7ad9d3fa242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350402692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2350402692
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.746562938
Short name T494
Test name
Test status
Simulation time 130429671 ps
CPU time 2.66 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:41 PM PDT 24
Peak memory 219060 kb
Host smart-687cd430-39c4-4bef-9645-690856e98b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746562938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.746562938
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1701906808
Short name T414
Test name
Test status
Simulation time 26487768 ps
CPU time 0.93 seconds
Started Aug 17 06:29:39 PM PDT 24
Finished Aug 17 06:29:40 PM PDT 24
Peak memory 215452 kb
Host smart-3269e0b9-1bc7-4d58-95e6-94f516204dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701906808 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1701906808
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.4243987355
Short name T783
Test name
Test status
Simulation time 17525661 ps
CPU time 1 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 207172 kb
Host smart-bca6acd7-0e1d-409d-92a5-851030a1eba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243987355 -assert nopostproc +UVM_TESTNAME=edn_regwen_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.4243987355
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1627646856
Short name T526
Test name
Test status
Simulation time 24699836 ps
CPU time 0.93 seconds
Started Aug 17 06:29:37 PM PDT 24
Finished Aug 17 06:29:38 PM PDT 24
Peak memory 215360 kb
Host smart-9a186990-e5b9-4846-a819-6b61de4d924f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627646856 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1627646856
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3788432497
Short name T358
Test name
Test status
Simulation time 313124373 ps
CPU time 1.59 seconds
Started Aug 17 06:29:32 PM PDT 24
Finished Aug 17 06:29:34 PM PDT 24
Peak memory 215272 kb
Host smart-b3708b43-318d-4751-a5cb-62c68774e57c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788432497 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3788432497
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1416713297
Short name T945
Test name
Test status
Simulation time 4347497713 ps
CPU time 51.81 seconds
Started Aug 17 06:29:33 PM PDT 24
Finished Aug 17 06:30:25 PM PDT 24
Peak memory 219084 kb
Host smart-4071479f-4fd8-4769-8b2a-6bba9a9762eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416713297 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1416713297
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3159379368
Short name T899
Test name
Test status
Simulation time 31454693 ps
CPU time 1.3 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 225940 kb
Host smart-78e17de2-90e4-4e0a-a001-64e272f73e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159379368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3159379368
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.4016092427
Short name T692
Test name
Test status
Simulation time 60480267 ps
CPU time 1.29 seconds
Started Aug 17 06:30:34 PM PDT 24
Finished Aug 17 06:30:39 PM PDT 24
Peak memory 218424 kb
Host smart-88b0856b-a931-4c8d-884c-72e0ca8d6d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016092427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.4016092427
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_alert.1642878466
Short name T400
Test name
Test status
Simulation time 30232154 ps
CPU time 1.29 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:37 PM PDT 24
Peak memory 215712 kb
Host smart-730d7c09-0cf8-4418-91c5-bfe59e88f60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642878466 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_alert.1642878466
Directory /workspace/91.edn_alert/latest

Test location /workspace/coverage/default/91.edn_err.1669043844
Short name T739
Test name
Test status
Simulation time 35738418 ps
CPU time 0.87 seconds
Started Aug 17 06:30:39 PM PDT 24
Finished Aug 17 06:30:40 PM PDT 24
Peak memory 219500 kb
Host smart-04f0c576-fee3-43ff-a0a7-dd096974686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669043844 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1669043844
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.4064326607
Short name T497
Test name
Test status
Simulation time 39540899 ps
CPU time 1.38 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 217364 kb
Host smart-2f341a0d-75b6-48a2-aa70-996107baa946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064326607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.4064326607
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_alert.349950463
Short name T127
Test name
Test status
Simulation time 63981483 ps
CPU time 1.29 seconds
Started Aug 17 06:31:13 PM PDT 24
Finished Aug 17 06:31:14 PM PDT 24
Peak memory 219772 kb
Host smart-0849983f-b831-4289-9522-5a100a321056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349950463 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_alert.349950463
Directory /workspace/92.edn_alert/latest

Test location /workspace/coverage/default/92.edn_err.819240303
Short name T198
Test name
Test status
Simulation time 28567491 ps
CPU time 1.19 seconds
Started Aug 17 06:30:34 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 219648 kb
Host smart-167674e0-04d1-4527-b16b-98119874a78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819240303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.819240303
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1832744433
Short name T777
Test name
Test status
Simulation time 107461540 ps
CPU time 1.24 seconds
Started Aug 17 06:30:46 PM PDT 24
Finished Aug 17 06:30:47 PM PDT 24
Peak memory 218620 kb
Host smart-d46a004f-df34-4c65-a048-291c107cb99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832744433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1832744433
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_alert.1750791455
Short name T842
Test name
Test status
Simulation time 42315940 ps
CPU time 1.19 seconds
Started Aug 17 06:30:31 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 218516 kb
Host smart-d3ee3058-e8af-4252-9767-c6f08cd26f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750791455 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_alert.1750791455
Directory /workspace/93.edn_alert/latest

Test location /workspace/coverage/default/93.edn_err.1594971262
Short name T472
Test name
Test status
Simulation time 21374354 ps
CPU time 0.97 seconds
Started Aug 17 06:30:48 PM PDT 24
Finished Aug 17 06:30:49 PM PDT 24
Peak memory 218364 kb
Host smart-cb0c1bdf-500d-439c-a2c1-4b65c5934f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594971262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1594971262
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.705601526
Short name T308
Test name
Test status
Simulation time 64262964 ps
CPU time 1.11 seconds
Started Aug 17 06:30:49 PM PDT 24
Finished Aug 17 06:30:50 PM PDT 24
Peak memory 217172 kb
Host smart-d1682ac2-ea64-4934-9b12-a2ca452e16eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705601526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.705601526
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_alert.693337585
Short name T500
Test name
Test status
Simulation time 40088233 ps
CPU time 1.14 seconds
Started Aug 17 06:30:28 PM PDT 24
Finished Aug 17 06:30:30 PM PDT 24
Peak memory 219036 kb
Host smart-95a1a11b-e76f-4691-a8b8-6719c7ac3b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693337585 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_alert.693337585
Directory /workspace/94.edn_alert/latest

Test location /workspace/coverage/default/94.edn_err.1363770102
Short name T126
Test name
Test status
Simulation time 39923217 ps
CPU time 0.9 seconds
Started Aug 17 06:30:36 PM PDT 24
Finished Aug 17 06:30:37 PM PDT 24
Peak memory 219676 kb
Host smart-d346b741-7fb2-4508-a904-77a997dae082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363770102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1363770102
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.4275413789
Short name T902
Test name
Test status
Simulation time 49602483 ps
CPU time 1.26 seconds
Started Aug 17 06:31:02 PM PDT 24
Finished Aug 17 06:31:04 PM PDT 24
Peak memory 218900 kb
Host smart-b84f0800-42f3-4c44-8943-2bf94ae0926a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275413789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.4275413789
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_alert.3636605913
Short name T645
Test name
Test status
Simulation time 120515528 ps
CPU time 1.42 seconds
Started Aug 17 06:30:42 PM PDT 24
Finished Aug 17 06:30:44 PM PDT 24
Peak memory 215668 kb
Host smart-c6623489-62ed-401b-8ceb-b1b0081005af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636605913 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_alert.3636605913
Directory /workspace/95.edn_alert/latest

Test location /workspace/coverage/default/95.edn_err.2538820990
Short name T50
Test name
Test status
Simulation time 27785215 ps
CPU time 0.97 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 223904 kb
Host smart-99ff5dd8-6d98-4e4b-ad81-954f15e55d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538820990 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2538820990
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2904690294
Short name T348
Test name
Test status
Simulation time 50867912 ps
CPU time 1.09 seconds
Started Aug 17 06:30:27 PM PDT 24
Finished Aug 17 06:30:29 PM PDT 24
Peak memory 218568 kb
Host smart-41f324b6-9d67-45db-99e2-64dd2d9e093a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904690294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2904690294
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_alert.1541929972
Short name T713
Test name
Test status
Simulation time 24151177 ps
CPU time 1.18 seconds
Started Aug 17 06:30:34 PM PDT 24
Finished Aug 17 06:30:35 PM PDT 24
Peak memory 220560 kb
Host smart-de9e8648-311d-469b-af5f-694dd148ac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541929972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_alert.1541929972
Directory /workspace/96.edn_alert/latest

Test location /workspace/coverage/default/96.edn_err.2299918624
Short name T523
Test name
Test status
Simulation time 52678597 ps
CPU time 1.02 seconds
Started Aug 17 06:31:10 PM PDT 24
Finished Aug 17 06:31:11 PM PDT 24
Peak memory 219996 kb
Host smart-15f47f78-4525-49b8-87e2-58ccbe9de333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299918624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2299918624
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.903197050
Short name T836
Test name
Test status
Simulation time 141342205 ps
CPU time 3.14 seconds
Started Aug 17 06:30:29 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 219628 kb
Host smart-cd5cb717-c669-44bf-a02d-186792bd58f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903197050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.903197050
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_alert.2224673333
Short name T106
Test name
Test status
Simulation time 30630936 ps
CPU time 1.33 seconds
Started Aug 17 06:30:40 PM PDT 24
Finished Aug 17 06:30:42 PM PDT 24
Peak memory 215760 kb
Host smart-85533062-2f65-4213-8908-9240f16bc30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224673333 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_alert.2224673333
Directory /workspace/97.edn_alert/latest

Test location /workspace/coverage/default/97.edn_err.2515459338
Short name T846
Test name
Test status
Simulation time 20389911 ps
CPU time 1.17 seconds
Started Aug 17 06:30:34 PM PDT 24
Finished Aug 17 06:30:36 PM PDT 24
Peak memory 224124 kb
Host smart-4ef14156-a7d0-4c72-be66-7711c0d171e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515459338 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2515459338
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1647832456
Short name T502
Test name
Test status
Simulation time 39444822 ps
CPU time 1.45 seconds
Started Aug 17 06:31:00 PM PDT 24
Finished Aug 17 06:31:01 PM PDT 24
Peak memory 218720 kb
Host smart-efaaa9af-c97a-4c87-a85c-39a78ce9e8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647832456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1647832456
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_alert.677936160
Short name T794
Test name
Test status
Simulation time 51701625 ps
CPU time 1.32 seconds
Started Aug 17 06:30:45 PM PDT 24
Finished Aug 17 06:30:47 PM PDT 24
Peak memory 218704 kb
Host smart-74718f0c-33c9-47e9-a99f-019262e14dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677936160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_alert.677936160
Directory /workspace/98.edn_alert/latest

Test location /workspace/coverage/default/98.edn_err.365372563
Short name T484
Test name
Test status
Simulation time 22576606 ps
CPU time 1.03 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:31 PM PDT 24
Peak memory 218716 kb
Host smart-7e264d7e-b316-404d-afb4-fbbf7e8fa142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365372563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.365372563
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.226430728
Short name T315
Test name
Test status
Simulation time 78807121 ps
CPU time 1.65 seconds
Started Aug 17 06:30:30 PM PDT 24
Finished Aug 17 06:30:32 PM PDT 24
Peak memory 218732 kb
Host smart-9939895c-614f-497c-b772-3bcb67bf1c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226430728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.226430728
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_alert.4001476926
Short name T286
Test name
Test status
Simulation time 24668792 ps
CPU time 1.15 seconds
Started Aug 17 06:30:33 PM PDT 24
Finished Aug 17 06:30:34 PM PDT 24
Peak memory 218676 kb
Host smart-5d89b462-aa9b-43b5-b8a6-75a83cfac018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001476926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_alert.4001476926
Directory /workspace/99.edn_alert/latest

Test location /workspace/coverage/default/99.edn_genbits.2124668733
Short name T295
Test name
Test status
Simulation time 82517475 ps
CPU time 1.27 seconds
Started Aug 17 06:30:40 PM PDT 24
Finished Aug 17 06:30:42 PM PDT 24
Peak memory 218884 kb
Host smart-e563cb73-34ec-43ce-a36d-2f65dcdc34cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124668733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2124668733
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%