Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	141	1			T3	1		T37	1		T96	1
auto_req_mode	137	1			T2	1		T9	1		T10	1
sw_mode	1991	1			T22	1		T5	6		T74	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

303

1

T2

1

T3

1

T9

1

single

97

1

T88

1

T40

1

T322

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	898	1			T2	1		T3	1		T9	1
auto[2]	184	1			T121	2		T338	1		T257	1
auto[3]	45	1			T281	1		T278	1		T339	1
auto[4]	36	1			T11	1		T132	10		T340	1
auto[5]	176	1			T37	1		T341	1		T31	48
auto[6]	108	1			T44	1		T113	15		T342	1
auto[7]	822	1			T5	6		T10	1		T34	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	80	1			T3	1		T96	1		T84	1
auto[1]	auto_req_mode	91	1			T2	1		T9	1		T19	1
auto[1]	sw_mode	727	1			T22	1		T74	1		T75	1
auto[2]	boot_req_mode	4	1			T338	1		T343	1		T344	1
auto[2]	auto_req_mode	2	1			T345	1		T346	1		-	-
auto[2]	sw_mode	178	1			T121	2		T257	1		T33	108
auto[3]	boot_req_mode	5	1			T278	1		T339	1		T347	1
auto[3]	auto_req_mode	2	1			T281	1		T348	1		-	-
auto[3]	sw_mode	38	1			T335	1		T349	1		T32	32
auto[4]	boot_req_mode	5	1			T340	1		T350	1		T351	1
auto[4]	auto_req_mode	3	1			T11	1		T352	1		T353	1
auto[4]	sw_mode	28	1			T132	10		T354	1		T355	1
auto[5]	boot_req_mode	4	1			T37	1		T356	1		T357	1
auto[5]	auto_req_mode	2	1			T358	1		T359	1		-	-
auto[5]	sw_mode	170	1			T341	1		T31	48		T360	1
auto[6]	boot_req_mode	5	1			T255	1		T361	1		T362	1
auto[6]	auto_req_mode	5	1			T44	1		T363	1		T364	1
auto[6]	sw_mode	98	1			T113	15		T342	1		T259	23
auto[7]	boot_req_mode	38	1			T122	1		T90	1		T99	1
auto[7]	auto_req_mode	32	1			T10	1		T12	1		T38	1
auto[7]	sw_mode	752	1			T5	6		T34	1		T48	9