Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149226	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

314387

1

T1

11

T2

51

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	197249	1			T1	5		T2	42		T3	59
values[0x0]	126013	1			T1	9		T2	25		T3	9
values[0x1]	140351	1			T1	4		T2	27		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	100179	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

363434

1

T1

14

T2

67

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1468	1			T2	1		T15	1		T5	2
valid_sources[0x01]	1353	1			T2	1		T3	3		T5	2
valid_sources[0x02]	2306	1			T5	1		T10	1		T11	7
valid_sources[0x03]	1587	1			T15	1		T10	1		T88	3
valid_sources[0x04]	3286	1			T21	9		T5	1		T10	3
valid_sources[0x05]	2002	1			T3	1		T22	4		T11	1
valid_sources[0x06]	1756	1			T4	1		T5	2		T23	1
valid_sources[0x07]	1482	1			T5	5		T95	3		T369	4
valid_sources[0x08]	1331	1			T37	60		T10	1		T11	3
valid_sources[0x09]	1432	1			T2	2		T23	1		T11	1
valid_sources[0x0a]	2783	1			T2	2		T5	1		T11	1
valid_sources[0x0b]	3138	1			T2	1		T5	1		T10	4
valid_sources[0x0c]	1820	1			T5	1		T23	1		T35	2
valid_sources[0x0d]	1611	1			T15	26		T88	21		T35	1
valid_sources[0x0e]	1907	1			T15	1		T5	1		T11	6
valid_sources[0x0f]	1849	1			T2	1		T5	1		T10	10
valid_sources[0x10]	1855	1			T5	2		T10	5		T94	1
valid_sources[0x11]	1733	1			T5	1		T10	2		T35	1
valid_sources[0x12]	1822	1			T5	2		T49	1		T6	1
valid_sources[0x13]	1414	1			T2	1		T13	1		T11	1
valid_sources[0x14]	2308	1			T15	1		T5	2		T94	2
valid_sources[0x15]	1610	1			T15	1		T5	1		T10	1
valid_sources[0x16]	1714	1			T5	1		T94	1		T95	2
valid_sources[0x17]	1822	1			T2	1		T23	1		T76	2
valid_sources[0x18]	1465	1			T2	1		T3	1		T5	1
valid_sources[0x19]	1882	1			T2	1		T5	1		T23	1
valid_sources[0x1a]	2051	1			T5	1		T23	1		T91	1
valid_sources[0x1b]	1679	1			T15	1		T5	3		T10	5
valid_sources[0x1c]	2643	1			T22	4		T5	2		T10	8
valid_sources[0x1d]	1194	1			T2	1		T3	2		T10	3
valid_sources[0x1e]	1626	1			T5	2		T23	1		T94	1
valid_sources[0x1f]	1651	1			T15	1		T22	8		T5	1
valid_sources[0x20]	2418	1			T2	1		T5	5		T10	4
valid_sources[0x21]	1522	1			T2	1		T5	1		T10	1
valid_sources[0x22]	2516	1			T2	1		T15	1		T5	1
valid_sources[0x23]	2307	1			T2	1		T15	1		T5	1
valid_sources[0x24]	1851	1			T5	3		T11	1		T322	1
valid_sources[0x25]	1860	1			T2	1		T22	7		T5	3
valid_sources[0x26]	1514	1			T5	1		T10	1		T115	1
valid_sources[0x27]	1925	1			T22	2		T10	2		T43	28
valid_sources[0x28]	2355	1			T2	1		T5	1		T38	9
valid_sources[0x29]	1639	1			T5	1		T10	9		T36	1
valid_sources[0x2a]	1906	1			T5	1		T11	1		T95	1
valid_sources[0x2b]	1532	1			T22	10		T5	2		T11	1
valid_sources[0x2c]	1417	1			T5	1		T10	1		T47	1
valid_sources[0x2d]	1465	1			T2	1		T3	2		T115	1
valid_sources[0x2e]	1688	1			T3	6		T5	1		T75	2
valid_sources[0x2f]	1923	1			T4	1		T5	3		T10	2
valid_sources[0x30]	1617	1			T15	1		T10	1		T83	1
valid_sources[0x31]	1283	1			T3	2		T5	1		T11	4
valid_sources[0x32]	1180	1			T10	4		T95	1		T35	1
valid_sources[0x33]	1908	1			T5	1		T10	9		T95	1
valid_sources[0x34]	1545	1			T2	3		T5	1		T10	7
valid_sources[0x35]	2591	1			T2	1		T5	3		T10	2
valid_sources[0x36]	1535	1			T22	1		T23	1		T10	2
valid_sources[0x37]	2462	1			T5	2		T76	2		T82	1
valid_sources[0x38]	1968	1			T2	1		T5	4		T23	1
valid_sources[0x39]	1210	1			T5	1		T10	4		T11	1
valid_sources[0x3a]	1578	1			T10	2		T39	3		T322	1
valid_sources[0x3b]	1528	1			T5	1		T74	33		T13	1
valid_sources[0x3c]	1518	1			T5	1		T10	1		T11	3
valid_sources[0x3d]	2731	1			T2	1		T4	1		T15	1
valid_sources[0x3e]	1730	1			T15	1		T5	1		T11	1
valid_sources[0x3f]	2029	1			T5	2		T23	1		T10	1
valid_sources[0x40]	1905	1			T2	1		T5	1		T11	1
valid_sources[0x41]	1405	1			T5	3		T13	1		T10	5
valid_sources[0x42]	1684	1			T5	1		T88	14		T91	1
valid_sources[0x43]	2064	1			T2	1		T22	6		T5	1
valid_sources[0x44]	1938	1			T5	2		T10	4		T115	1
valid_sources[0x45]	2061	1			T15	1		T22	15		T5	3
valid_sources[0x46]	2122	1			T15	1		T5	1		T11	1
valid_sources[0x47]	2053	1			T10	2		T83	1		T36	1
valid_sources[0x48]	1552	1			T15	1		T22	20		T11	1
valid_sources[0x49]	2417	1			T15	1		T5	1		T13	1
valid_sources[0x4a]	1664	1			T3	3		T4	2		T5	3
valid_sources[0x4b]	1458	1			T5	3		T11	2		T83	3
valid_sources[0x4c]	1442	1			T5	2		T10	3		T79	1
valid_sources[0x4d]	1497	1			T5	1		T10	4		T11	2
valid_sources[0x4e]	2145	1			T2	3		T5	3		T75	10
valid_sources[0x4f]	1685	1			T5	2		T10	1		T94	1
valid_sources[0x50]	1523	1			T5	4		T23	1		T10	8
valid_sources[0x51]	1944	1			T4	1		T13	1		T11	4
valid_sources[0x52]	2644	1			T5	2		T23	1		T76	1
valid_sources[0x53]	1869	1			T5	1		T11	4		T85	1
valid_sources[0x54]	1576	1			T5	1		T10	2		T11	1
valid_sources[0x55]	1184	1			T2	2		T22	5		T5	2
valid_sources[0x56]	1996	1			T10	3		T94	1		T79	3
valid_sources[0x57]	1930	1			T2	1		T15	1		T5	1
valid_sources[0x58]	1844	1			T4	1		T5	2		T12	30
valid_sources[0x59]	1486	1			T22	3		T5	2		T10	1
valid_sources[0x5a]	2043	1			T2	1		T4	2		T5	1
valid_sources[0x5b]	1258	1			T76	1		T11	2		T94	1
valid_sources[0x5c]	1381	1			T4	1		T5	1		T10	2
valid_sources[0x5d]	1260	1			T15	2		T94	1		T39	2
valid_sources[0x5e]	1593	1			T3	1		T5	1		T13	2
valid_sources[0x5f]	1380	1			T15	1		T5	3		T47	4
valid_sources[0x60]	1504	1			T21	42		T15	1		T5	4
valid_sources[0x61]	1793	1			T2	1		T5	3		T10	2
valid_sources[0x62]	1622	1			T2	1		T5	2		T82	1
valid_sources[0x63]	1618	1			T5	2		T10	2		T11	2
valid_sources[0x64]	1882	1			T5	2		T23	1		T76	3
valid_sources[0x65]	1805	1			T22	3		T5	1		T94	1
valid_sources[0x66]	1467	1			T4	1		T23	1		T10	1
valid_sources[0x67]	1943	1			T2	1		T5	2		T11	1
valid_sources[0x68]	1760	1			T5	3		T135	1		T79	1
valid_sources[0x69]	1360	1			T5	1		T10	2		T11	6
valid_sources[0x6a]	1729	1			T5	2		T10	3		T76	1
valid_sources[0x6b]	2042	1			T76	1		T94	2		T82	1
valid_sources[0x6c]	1433	1			T2	1		T5	3		T10	1
valid_sources[0x6d]	1978	1			T15	1		T10	3		T11	2
valid_sources[0x6e]	1918	1			T5	3		T23	1		T10	1
valid_sources[0x6f]	1737	1			T22	1		T5	3		T23	1
valid_sources[0x70]	1837	1			T5	2		T11	1		T83	1
valid_sources[0x71]	1272	1			T5	1		T23	1		T10	2
valid_sources[0x72]	3284	1			T2	1		T5	2		T12	24
valid_sources[0x73]	1671	1			T3	4		T13	3		T82	1
valid_sources[0x74]	1937	1			T5	2		T76	2		T11	1
valid_sources[0x75]	1554	1			T5	1		T70	1		T36	1
valid_sources[0x76]	2227	1			T2	1		T3	2		T9	72
valid_sources[0x77]	1646	1			T2	2		T3	1		T15	1
valid_sources[0x78]	2123	1			T3	1		T121	162		T122	1
valid_sources[0x79]	1577	1			T2	1		T15	1		T5	4
valid_sources[0x7a]	1972	1			T5	2		T10	7		T11	2
valid_sources[0x7b]	1242	1			T5	1		T23	1		T47	1
valid_sources[0x7c]	1427	1			T2	2		T5	1		T23	1
valid_sources[0x7d]	1963	1			T3	2		T5	1		T10	3
valid_sources[0x7e]	1450	1			T5	2		T10	1		T11	2
valid_sources[0x7f]	2185	1			T15	2		T5	2		T91	1
valid_sources[0x80]	1446	1			T4	1		T5	1		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

84964

1

T1

3

T2

3

T3

3

values[0x0]

all_enables

biggest_size

115651

1

T1

6

T2

23

T3

6

values[0x1]

all_enables

biggest_size

113772

1

T1

2

T2

25

T3

7