Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1667	1			T2	5		T3	1		T9	1
non_zero_bins[1]	1269	1			T2	2		T22	2		T5	2
zero	5972	1			T1	3		T2	1		T3	6

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	307	1			T3	1		T5	1		T37	1
uni	2091	1			T2	1		T3	2		T22	2
gen	3054	1			T1	1		T2	4		T3	2
res	643	1			T2	2		T9	1		T5	1
ins	2813	1			T1	2		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5690

1

T1

1

T2

2

T3

5

mubi_true

3218

1

T1

2

T2

6

T3

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

44

1

T76

1

T94

1

T95

1

pass

8864

1

T1

3

T2

8

T3

7

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	66	1			T90	1		T123	1		T119	1
upd	non_zero_bins[0]	pass	mubi_true	69	1			T37	1		T48	1		T317	1
upd	non_zero_bins[1]	pass	mubi_false	60	1			T5	1		T48	1		T99	1
upd	non_zero_bins[1]	pass	mubi_true	60	1			T115	1		T122	1		T123	1
upd	zero	pass	mubi_false	22	1			T79	1		T251	1		T318	1
upd	zero	pass	mubi_true	30	1			T3	1		T48	1		T279	1
uni	zero	pass	mubi_false	1607	1			T2	1		T3	2		T22	2
uni	zero	pass	mubi_true	484	1			T5	4		T75	1		T88	1
gen	non_zero_bins[0]	pass	mubi_false	313	1			T5	2		T37	1		T38	4
gen	non_zero_bins[0]	pass	mubi_true	345	1			T2	3		T9	1		T11	1
gen	non_zero_bins[1]	pass	mubi_false	283	1			T11	5		T48	2		T46	3
gen	non_zero_bins[1]	pass	mubi_true	227	1			T2	1		T10	8		T12	8
gen	zero	fail	mubi_false	39	1			T76	1		T94	1		T95	1
gen	zero	pass	mubi_false	1169	1			T3	2		T4	1		T5	3
gen	zero	pass	mubi_true	678	1			T1	1		T4	1		T21	2
res	non_zero_bins[0]	pass	mubi_false	154	1			T44	2		T171	3		T319	1
res	non_zero_bins[0]	pass	mubi_true	123	1			T2	2		T84	1		T46	2
res	non_zero_bins[1]	pass	mubi_false	113	1			T19	1		T20	1		T48	1
res	non_zero_bins[1]	pass	mubi_true	99	1			T10	2		T11	2		T92	1
res	zero	fail	mubi_false	5	1			T173	1		T174	1		T320	1
res	zero	pass	mubi_false	82	1			T9	1		T5	1		T129	2
res	zero	pass	mubi_true	67	1			T12	2		T38	2		T45	6
ins	non_zero_bins[0]	pass	mubi_false	283	1			T5	1		T88	1		T34	1
ins	non_zero_bins[0]	pass	mubi_true	314	1			T3	1		T5	1		T34	1
ins	non_zero_bins[1]	pass	mubi_false	217	1			T2	1		T22	1		T19	1
ins	non_zero_bins[1]	pass	mubi_true	210	1			T22	1		T5	1		T88	1
ins	zero	pass	mubi_false	1277	1			T1	1		T3	1		T4	3
ins	zero	pass	mubi_true	512	1			T1	1		T9	1		T21	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded