Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.87	100.00	94.44		97.30	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.87	100.00	94.44		97.30	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.89	100.00	94.44		97.30	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		108	108	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	104	104	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
78	1	1
79	1	1
80	1	1
83	1	1
84	1	1
85	1	1
			MISSING_ELSE
89	1	1
90	1	1
93	1	1
94	1	1
			MISSING_ELSE
98	1	1
101	1	1
102	1	1
			MISSING_ELSE
106	1	1
107	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
117	1	1
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
129	1	1
130	1	1
131	1	1
			MISSING_ELSE
135	1	1
136	1	1
137	1	1
138	1	1
140	1	1
141	1	1
143	1	1
148	1	1
149	1	1
150	1	1
153	1	1
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
165	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
172	1	1
175	1	1
178	1	1
186	1	1
188	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
211	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T9
1	0	Covered	T1,T4,T23
1	1	Covered	T1,T3,T4

 LINE       66
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T9,T19,T83
1	1	Covered	T2,T9,T15

 LINE       186
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T15,T23
1	0	Covered	T1,T4,T13

 LINE       188
 EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
             --------1-------

-1-	Status	Tests
0	Covered	T21,T15,T23
1	Covered	T1,T4,T13

 LINE       188
 SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
                 ---------1--------

-1-	Status	Tests
0	Covered	T21,T15,T23
1	Not Covered

 LINE       188
 SUB-EXPRESSION (state_q == Error)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T4,T21
1	Covered	T1,T4,T13

 LINE       201
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T9,T4

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	74	72	97.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	156	Covered	T2,T9,T10
AutoCaptGenCnt	143	Covered	T2,T9,T10
AutoCaptReseedCnt	141	Covered	T2,T9,T10
AutoDispatch	125	Covered	T2,T9,T10
AutoFirstAckWait	119	Covered	T2,T9,T10
AutoLoadIns	69	Covered	T2,T9,T15
AutoSendGenCmd	150	Covered	T2,T9,T10
AutoSendReseedCmd	162	Covered	T2,T9,T10
BootDone	98	Covered	T1,T3,T4
BootGenAckWait	90	Covered	T1,T3,T4
BootInsAckWait	80	Covered	T1,T3,T4
BootLoadGen	85	Covered	T1,T3,T4
BootLoadIns	65	Covered	T1,T3,T4
BootLoadUni	102	Covered	T3,T4,T37
BootPulse	94	Covered	T1,T3,T4
BootUniAckWait	107	Covered	T3,T37,T13
Error	188	Covered	T1,T4,T13
Idle	112	Covered	T1,T2,T3
RejectCsrngEntropy	188	Covered	T21,T15,T23
SWPortMode	74	Covered	T2,T3,T21

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	131	Covered	T2,T9,T10
AutoAckWait->Error	188	Covered	T140
AutoAckWait->Idle	211	Covered	T9,T19,T20
AutoAckWait->RejectCsrngEntropy	188	Covered	T76,T94,T95
AutoCaptGenCnt->AutoSendGenCmd	150	Covered	T2,T9,T10
AutoCaptGenCnt->Error	188	Covered	T64,T141
AutoCaptGenCnt->Idle	211	Covered	T142,T143,T144
AutoCaptGenCnt->RejectCsrngEntropy	188	Covered	T81,T145,T146
AutoCaptReseedCnt->AutoSendReseedCmd	162	Covered	T2,T9,T10
AutoCaptReseedCnt->Error	188	Covered	T147
AutoCaptReseedCnt->Idle	211	Covered	T148,T149,T150
AutoCaptReseedCnt->RejectCsrngEntropy	188	Covered	T85,T151,T127
AutoDispatch->AutoCaptGenCnt	143	Covered	T2,T9,T10
AutoDispatch->AutoCaptReseedCnt	141	Covered	T2,T9,T10
AutoDispatch->Error	188	Covered	T152,T153,T154
AutoDispatch->Idle	138	Covered	T2,T10,T11
AutoDispatch->RejectCsrngEntropy	188	Covered	T155,T156,T157
AutoFirstAckWait->AutoDispatch	125	Covered	T2,T9,T10
AutoFirstAckWait->Error	188	Covered	T55,T158,T159
AutoFirstAckWait->Idle	211	Covered	T9,T160,T161
AutoFirstAckWait->RejectCsrngEntropy	188	Covered	T83,T162,T163
AutoLoadIns->AutoFirstAckWait	119	Covered	T2,T9,T10
AutoLoadIns->Error	188	Covered	T50,T53,T56
AutoLoadIns->Idle	211	Covered	T15,T76,T94
AutoLoadIns->RejectCsrngEntropy	188	Covered	T102,T164,T165
AutoSendGenCmd->AutoAckWait	156	Covered	T2,T9,T10
AutoSendGenCmd->Error	188	Covered	T7,T166
AutoSendGenCmd->Idle	211	Covered	T19,T45,T167
AutoSendGenCmd->RejectCsrngEntropy	188	Covered	T134,T168,T169
AutoSendReseedCmd->AutoAckWait	168	Covered	T2,T9,T10
AutoSendReseedCmd->Error	188	Covered	T6,T170
AutoSendReseedCmd->Idle	211	Covered	T71,T171,T172
AutoSendReseedCmd->RejectCsrngEntropy	188	Covered	T173,T174,T175
BootDone->BootLoadUni	102	Covered	T3,T4,T37
BootDone->Error	188	Covered	T176,T177,T178
BootDone->Idle	211	Covered	T179,T180,T63
BootDone->RejectCsrngEntropy	188	Covered	T23,T87,T181
BootGenAckWait->BootPulse	94	Covered	T1,T3,T4
BootGenAckWait->Error	188	Covered	T182,T183
BootGenAckWait->Idle	211	Covered	T78,T184,T185
BootGenAckWait->RejectCsrngEntropy	188	Covered	T21,T36,T186
BootInsAckWait->BootLoadGen	85	Covered	T1,T3,T4
BootInsAckWait->Error	188	Covered	T1
BootInsAckWait->Idle	211	Covered	T1,T4,T13
BootInsAckWait->RejectCsrngEntropy	188	Covered	T47,T187,T188
BootLoadGen->BootGenAckWait	90	Covered	T1,T3,T4
BootLoadGen->Error	188	Covered	T189
BootLoadGen->Idle	211	Covered	T190,T191,T192
BootLoadGen->RejectCsrngEntropy	188	Covered	T193,T194,T195
BootLoadIns->BootInsAckWait	80	Covered	T1,T3,T4
BootLoadIns->Error	188	Covered	T78,T196,T197
BootLoadIns->Idle	211	Not Covered
BootLoadIns->RejectCsrngEntropy	188	Covered	T15,T198,T199
BootLoadUni->BootUniAckWait	107	Covered	T3,T37,T13
BootLoadUni->Error	188	Covered	T52,T200
BootLoadUni->Idle	211	Not Covered
BootLoadUni->RejectCsrngEntropy	188	Covered	T86,T201,T202
BootPulse->BootDone	98	Covered	T1,T3,T4
BootPulse->Error	188	Covered	T54,T203
BootPulse->Idle	211	Covered	T96,T204,T205
BootPulse->RejectCsrngEntropy	188	Covered	T206,T207,T208
BootUniAckWait->Error	188	Covered	T13,T209
BootUniAckWait->Idle	112	Covered	T3,T37,T47
BootUniAckWait->RejectCsrngEntropy	188	Covered	T35,T135,T116
Idle->AutoLoadIns	69	Covered	T2,T9,T15
Idle->BootLoadIns	65	Covered	T1,T3,T4
Idle->Error	188	Covered	T16,T17,T18
Idle->RejectCsrngEntropy	188	Covered	T15,T23,T85
Idle->SWPortMode	74	Covered	T2,T3,T21
RejectCsrngEntropy->Error	188	Covered	T210,T211,T212
RejectCsrngEntropy->Idle	211	Covered	T21,T15,T23
SWPortMode->Error	188	Covered	T39,T14,T118
SWPortMode->Idle	211	Covered	T21,T5,T23
SWPortMode->RejectCsrngEntropy	188	Covered	T21,T76,T47

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	42	2	2	100.00
CASE	62	35	35	100.00
IF	186	5	4	80.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	case (state_q)
-2-:	64	if ((boot_req_mode_i && edn_enable_i))
-3-:	66	if ((auto_req_mode_i && edn_enable_i))
-4-:	70	if (edn_enable_i)
-5-:	84	if (csrng_cmd_ack_i)
-6-:	93	if (csrng_cmd_ack_i)
-7-:	101	if ((!boot_req_mode_i))
-8-:	110	if (csrng_cmd_ack_i)
-9-:	118	if (sw_cmd_req_load_i)
-10-:	124	if (csrng_cmd_ack_i)
-11-:	130	if (csrng_cmd_ack_i)
-12-:	136	if ((!auto_req_mode_i))
-13-:	140	if (max_reqs_cnt_zero_i)
-14-:	155	if (cmd_sent_i)
-15-:	167	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T15
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T21
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T3,T4,T37
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T4,T23
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T37
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T3,T37,T35
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T37,T13
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T9,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T9,T15
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T9,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T9,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T9,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T9,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T9,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T9,T10
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T9,T10
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T9,T10
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T9,T10
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T21
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T15,T23
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T43,T77

	LineNo.	Expression
-1-:	186	if ((local_escalate_i || csrng_ack_err_i))
-2-:	188	(local_escalate_i) ? 
-3-:	188	((state_q == Error)) ? 
-4-:	201	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Covered	T1,T4,T13
1	0	1	-	Not Covered
1	0	0	-	Covered	T21,T15,T23
0	-	-	1	Covered	T1,T9,T4
0	-	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	10995242	165423	0	0
FpvSecCmErrorStEscalate_A	10995242	166720	0	0
u_state_regs_A	10960138	10766223	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10995242	165423	0	0
T1	1808	1082	0	0
T2	2929	0	0	0
T3	1925	0	0	0
T4	625	184	0	0
T5	9181	0	0	0
T6	0	440	0	0
T9	2279	0	0	0
T13	0	252	0	0
T14	0	1078	0	0
T15	1968	0	0	0
T21	1881	0	0	0
T22	3963	0	0	0
T23	2279	0	0	0
T39	0	608	0	0
T43	0	163	0	0
T77	0	342	0	0
T78	0	425	0	0
T213	0	340	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10995242	166720	0	0
T1	1808	1083	0	0
T2	2929	0	0	0
T3	1925	0	0	0
T4	625	185	0	0
T5	9181	0	0	0
T6	0	441	0	0
T9	2279	0	0	0
T13	0	253	0	0
T14	0	1079	0	0
T15	1968	0	0	0
T21	1881	0	0	0
T22	3963	0	0	0
T23	2279	0	0	0
T39	0	609	0	0
T43	0	164	0	0
T77	0	343	0	0
T78	0	426	0	0
T213	0	341	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10960138	10766223	0	0
T1	1685	1559	0	0
T2	2929	2860	0	0
T3	1925	1835	0	0
T4	401	232	0	0
T5	9181	8774	0	0
T9	2279	2202	0	0
T15	1968	1913	0	0
T21	1881	1799	0	0
T22	3963	3913	0	0
T23	2279	2209	0	0