Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28,T26,T101
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T27,T30
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	21197796	613582	0	0
DepthKnown_A	21990484	21602654	0	0
RvalidKnown_A	21990484	21602654	0	0
WreadyKnown_A	21990484	21602654	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	21544618	696521	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21197796	613582	0	0
T2	5858	2378	0	0
T3	3850	0	0	0
T4	258	0	0	0
T5	18362	0	0	0
T9	4558	2392	0	0
T10	0	1451	0	0
T11	0	1191	0	0
T12	0	2161	0	0
T15	3936	165	0	0
T19	0	2073	0	0
T21	3762	0	0	0
T22	7926	0	0	0
T23	4558	0	0	0
T74	2026	0	0	0
T76	0	600	0	0
T94	0	678	0	0
T95	0	357	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21990484	21602654	0	0
T1	3616	3364	0	0
T2	5858	5720	0	0
T3	3850	3670	0	0
T4	1250	912	0	0
T5	18362	17548	0	0
T9	4558	4404	0	0
T15	3936	3826	0	0
T21	3762	3598	0	0
T22	7926	7826	0	0
T23	4558	4418	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21990484	21602654	0	0
T1	3616	3364	0	0
T2	5858	5720	0	0
T3	3850	3670	0	0
T4	1250	912	0	0
T5	18362	17548	0	0
T9	4558	4404	0	0
T15	3936	3826	0	0
T21	3762	3598	0	0
T22	7926	7826	0	0
T23	4558	4418	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21990484	21602654	0	0
T1	3616	3364	0	0
T2	5858	5720	0	0
T3	3850	3670	0	0
T4	1250	912	0	0
T5	18362	17548	0	0
T9	4558	4404	0	0
T15	3936	3826	0	0
T21	3762	3598	0	0
T22	7926	7826	0	0
T23	4558	4418	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	21544618	696521	0	0
T1	3616	222	0	0
T2	5858	2378	0	0
T3	3850	0	0	0
T4	1250	372	0	0
T5	18362	0	0	0
T9	4558	2392	0	0
T10	0	1451	0	0
T11	0	1191	0	0
T13	0	318	0	0
T15	3936	165	0	0
T19	0	2073	0	0
T21	3762	0	0	0
T22	7926	0	0	0
T23	4558	0	0	0
T76	0	600	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T26,T102
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T26,T101
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T27,T30,T103
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	10598898	300283	0	0
DepthKnown_A	10995242	10801327	0	0
RvalidKnown_A	10995242	10801327	0	0
WreadyKnown_A	10995242	10801327	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	10772309	341437	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10598898	300283	0	0
T2	2929	1128	0	0
T3	1925	0	0	0
T4	129	0	0	0
T5	9181	0	0	0
T9	2279	1177	0	0
T10	0	721	0	0
T11	0	593	0	0
T12	0	1027	0	0
T15	1968	41	0	0
T19	0	1023	0	0
T21	1881	0	0	0
T22	3963	0	0	0
T23	2279	0	0	0
T74	1013	0	0	0
T76	0	292	0	0
T94	0	329	0	0
T95	0	180	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10995242	10801327	0	0
T1	1808	1682	0	0
T2	2929	2860	0	0
T3	1925	1835	0	0
T4	625	456	0	0
T5	9181	8774	0	0
T9	2279	2202	0	0
T15	1968	1913	0	0
T21	1881	1799	0	0
T22	3963	3913	0	0
T23	2279	2209	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10995242	10801327	0	0
T1	1808	1682	0	0
T2	2929	2860	0	0
T3	1925	1835	0	0
T4	625	456	0	0
T5	9181	8774	0	0
T9	2279	2202	0	0
T15	1968	1913	0	0
T21	1881	1799	0	0
T22	3963	3913	0	0
T23	2279	2209	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10995242	10801327	0	0
T1	1808	1682	0	0
T2	2929	2860	0	0
T3	1925	1835	0	0
T4	625	456	0	0
T5	9181	8774	0	0
T9	2279	2202	0	0
T15	1968	1913	0	0
T21	1881	1799	0	0
T22	3963	3913	0	0
T23	2279	2209	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	10772309	341437	0	0
T1	1808	112	0	0
T2	2929	1128	0	0
T3	1925	0	0	0
T4	625	191	0	0
T5	9181	0	0	0
T9	2279	1177	0	0
T10	0	721	0	0
T11	0	593	0	0
T13	0	160	0	0
T15	1968	41	0	0
T19	0	1023	0	0
T21	1881	0	0	0
T22	3963	0	0	0
T23	2279	0	0	0
T76	0	292	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T28
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T104,T105
1	0	1	Covered	T1,T2,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	10598898	313299	0	0
DepthKnown_A	10995242	10801327	0	0
RvalidKnown_A	10995242	10801327	0	0
WreadyKnown_A	10995242	10801327	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	10772309	355084	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10598898	313299	0	0
T2	2929	1250	0	0
T3	1925	0	0	0
T4	129	0	0	0
T5	9181	0	0	0
T9	2279	1215	0	0
T10	0	730	0	0
T11	0	598	0	0
T12	0	1134	0	0
T15	1968	124	0	0
T19	0	1050	0	0
T21	1881	0	0	0
T22	3963	0	0	0
T23	2279	0	0	0
T74	1013	0	0	0
T76	0	308	0	0
T94	0	349	0	0
T95	0	177	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10995242	10801327	0	0
T1	1808	1682	0	0
T2	2929	2860	0	0
T3	1925	1835	0	0
T4	625	456	0	0
T5	9181	8774	0	0
T9	2279	2202	0	0
T15	1968	1913	0	0
T21	1881	1799	0	0
T22	3963	3913	0	0
T23	2279	2209	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10995242	10801327	0	0
T1	1808	1682	0	0
T2	2929	2860	0	0
T3	1925	1835	0	0
T4	625	456	0	0
T5	9181	8774	0	0
T9	2279	2202	0	0
T15	1968	1913	0	0
T21	1881	1799	0	0
T22	3963	3913	0	0
T23	2279	2209	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10995242	10801327	0	0
T1	1808	1682	0	0
T2	2929	2860	0	0
T3	1925	1835	0	0
T4	625	456	0	0
T5	9181	8774	0	0
T9	2279	2202	0	0
T15	1968	1913	0	0
T21	1881	1799	0	0
T22	3963	3913	0	0
T23	2279	2209	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	10772309	355084	0	0
T1	1808	110	0	0
T2	2929	1250	0	0
T3	1925	0	0	0
T4	625	181	0	0
T5	9181	0	0	0
T9	2279	1215	0	0
T10	0	730	0	0
T11	0	598	0	0
T13	0	158	0	0
T15	1968	124	0	0
T19	0	1050	0	0
T21	1881	0	0	0
T22	3963	0	0	0
T23	2279	0	0	0
T76	0	308	0	0