Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	170087	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

387280

1

T1

11

T2

25

T3

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	230430	1			T1	32		T2	31		T3	6
values[0x0]	154650	1			T1	7		T2	16		T3	7
values[0x1]	172287	1			T1	5		T2	8		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	113267	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

444100

1

T1

18

T2

29

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2454	1			T26	7		T11	1		T15	100
valid_sources[0x01]	1768	1			T11	1		T51	4		T36	69
valid_sources[0x02]	1852	1			T4	1		T25	1		T11	3
valid_sources[0x03]	2929	1			T43	1		T51	3		T61	2
valid_sources[0x04]	2828	1			T4	1		T26	12		T51	3
valid_sources[0x05]	2370	1			T3	25		T9	2		T77	1
valid_sources[0x06]	2625	1			T9	1		T77	1		T78	1
valid_sources[0x07]	2110	1			T24	1		T4	1		T25	1
valid_sources[0x08]	2441	1			T4	1		T78	3		T60	1
valid_sources[0x09]	2071	1			T61	2		T36	71		T41	1
valid_sources[0x0a]	2633	1			T25	2		T51	3		T36	50
valid_sources[0x0b]	2156	1			T9	2		T25	1		T36	44
valid_sources[0x0c]	1675	1			T9	1		T25	1		T39	1
valid_sources[0x0d]	2341	1			T11	2		T51	2		T61	2
valid_sources[0x0e]	2210	1			T25	2		T77	2		T43	1
valid_sources[0x0f]	2392	1			T10	4		T51	4		T36	62
valid_sources[0x10]	2099	1			T11	3		T59	1		T51	3
valid_sources[0x11]	1965	1			T11	1		T51	2		T36	114
valid_sources[0x12]	2397	1			T51	4		T36	35		T227	1
valid_sources[0x13]	1953	1			T59	1		T51	7		T36	48
valid_sources[0x14]	2010	1			T2	1		T4	1		T9	3
valid_sources[0x15]	2011	1			T59	1		T51	1		T61	1
valid_sources[0x16]	2917	1			T51	1		T36	99		T37	56
valid_sources[0x17]	2127	1			T25	2		T11	1		T43	1
valid_sources[0x18]	1744	1			T9	1		T51	3		T36	73
valid_sources[0x19]	2051	1			T11	1		T43	1		T61	1
valid_sources[0x1a]	2126	1			T9	2		T11	2		T78	1
valid_sources[0x1b]	2799	1			T43	1		T36	59		T45	3
valid_sources[0x1c]	1782	1			T11	1		T51	5		T36	78
valid_sources[0x1d]	3194	1			T9	1		T51	2		T61	2
valid_sources[0x1e]	2420	1			T39	1		T51	9		T61	1
valid_sources[0x1f]	2970	1			T25	1		T26	4		T51	3
valid_sources[0x20]	2140	1			T2	1		T9	3		T25	2
valid_sources[0x21]	2041	1			T51	2		T61	3		T36	102
valid_sources[0x22]	1650	1			T25	1		T43	2		T60	1
valid_sources[0x23]	1779	1			T43	1		T51	2		T36	53
valid_sources[0x24]	1960	1			T43	1		T59	2		T51	4
valid_sources[0x25]	3017	1			T11	1		T59	1		T51	2
valid_sources[0x26]	2114	1			T39	1		T61	1		T36	65
valid_sources[0x27]	2359	1			T25	1		T51	4		T36	69
valid_sources[0x28]	2238	1			T11	1		T51	1		T36	61
valid_sources[0x29]	2056	1			T4	1		T25	1		T59	1
valid_sources[0x2a]	1643	1			T59	1		T51	2		T61	1
valid_sources[0x2b]	2403	1			T51	10		T36	55		T45	1
valid_sources[0x2c]	2137	1			T39	5		T60	1		T51	4
valid_sources[0x2d]	1717	1			T43	1		T60	1		T51	1
valid_sources[0x2e]	1768	1			T25	2		T59	1		T51	6
valid_sources[0x2f]	1912	1			T2	1		T39	1		T51	6
valid_sources[0x30]	2396	1			T26	1		T11	1		T77	1
valid_sources[0x31]	2170	1			T39	1		T51	6		T36	50
valid_sources[0x32]	2320	1			T51	1		T36	101		T227	1
valid_sources[0x33]	2644	1			T25	1		T51	2		T61	2
valid_sources[0x34]	2820	1			T25	1		T11	3		T16	18
valid_sources[0x35]	2179	1			T39	3		T61	1		T36	125
valid_sources[0x36]	2034	1			T11	1		T39	4		T43	1
valid_sources[0x37]	2099	1			T25	2		T51	1		T36	61
valid_sources[0x38]	2339	1			T2	1		T9	3		T25	3
valid_sources[0x39]	2430	1			T9	1		T25	1		T43	1
valid_sources[0x3a]	2246	1			T2	1		T25	1		T51	7
valid_sources[0x3b]	2318	1			T43	1		T51	2		T61	2
valid_sources[0x3c]	1825	1			T9	1		T25	2		T51	6
valid_sources[0x3d]	2253	1			T4	1		T39	2		T61	1
valid_sources[0x3e]	1814	1			T1	44		T11	1		T51	8
valid_sources[0x3f]	2210	1			T11	5		T51	1		T36	80
valid_sources[0x40]	1845	1			T9	3		T51	3		T36	54
valid_sources[0x41]	1845	1			T34	3		T51	3		T36	95
valid_sources[0x42]	1654	1			T9	1		T51	5		T36	53
valid_sources[0x43]	2170	1			T39	2		T36	70		T227	1
valid_sources[0x44]	2035	1			T2	1		T51	3		T61	1
valid_sources[0x45]	1854	1			T25	1		T51	1		T61	1
valid_sources[0x46]	2255	1			T51	2		T61	1		T36	75
valid_sources[0x47]	2103	1			T25	3		T51	1		T36	83
valid_sources[0x48]	2026	1			T60	1		T51	4		T36	102
valid_sources[0x49]	1911	1			T2	1		T9	1		T25	1
valid_sources[0x4a]	2333	1			T9	1		T25	2		T39	1
valid_sources[0x4b]	2361	1			T59	1		T60	1		T36	80
valid_sources[0x4c]	2052	1			T43	1		T59	2		T51	4
valid_sources[0x4d]	2178	1			T2	5		T59	5		T60	1
valid_sources[0x4e]	2019	1			T5	245		T77	1		T43	1
valid_sources[0x4f]	2095	1			T11	1		T39	1		T51	1
valid_sources[0x50]	1988	1			T9	1		T43	1		T51	4
valid_sources[0x51]	2113	1			T77	2		T51	4		T61	2
valid_sources[0x52]	2994	1			T39	2		T51	4		T61	1
valid_sources[0x53]	2036	1			T9	1		T11	2		T39	1
valid_sources[0x54]	1779	1			T51	3		T61	2		T36	82
valid_sources[0x55]	1603	1			T2	3		T78	1		T51	4
valid_sources[0x56]	2376	1			T39	2		T51	2		T61	1
valid_sources[0x57]	2091	1			T25	1		T51	3		T44	148
valid_sources[0x58]	2151	1			T51	2		T36	91		T37	51
valid_sources[0x59]	1840	1			T9	1		T51	7		T36	67
valid_sources[0x5a]	1982	1			T25	1		T43	1		T51	4
valid_sources[0x5b]	2110	1			T11	1		T51	6		T36	46
valid_sources[0x5c]	2049	1			T34	1		T51	3		T36	97
valid_sources[0x5d]	1987	1			T51	3		T36	34		T37	49
valid_sources[0x5e]	2209	1			T61	2		T36	46		T227	1
valid_sources[0x5f]	2464	1			T9	3		T25	3		T11	4
valid_sources[0x60]	2144	1			T4	1		T59	1		T60	1
valid_sources[0x61]	2185	1			T11	1		T51	1		T61	1
valid_sources[0x62]	1989	1			T59	1		T51	3		T36	61
valid_sources[0x63]	2229	1			T51	8		T36	101		T45	2
valid_sources[0x64]	2525	1			T51	1		T36	58		T227	1
valid_sources[0x65]	2812	1			T78	1		T43	1		T59	3
valid_sources[0x66]	2492	1			T51	1		T36	73		T37	54
valid_sources[0x67]	2354	1			T51	2		T61	2		T36	74
valid_sources[0x68]	1760	1			T43	1		T60	1		T51	1
valid_sources[0x69]	1989	1			T25	1		T11	1		T36	101
valid_sources[0x6a]	2398	1			T36	54		T37	63		T331	1
valid_sources[0x6b]	2160	1			T77	4		T51	3		T36	78
valid_sources[0x6c]	2085	1			T25	5		T77	3		T43	1
valid_sources[0x6d]	1901	1			T9	1		T51	2		T36	34
valid_sources[0x6e]	2026	1			T77	2		T59	5		T51	6
valid_sources[0x6f]	1932	1			T77	2		T59	7		T51	3
valid_sources[0x70]	2393	1			T25	1		T60	1		T51	3
valid_sources[0x71]	2272	1			T9	3		T11	2		T77	1
valid_sources[0x72]	2486	1			T25	1		T51	2		T36	59
valid_sources[0x73]	1889	1			T2	2		T78	1		T59	4
valid_sources[0x74]	2147	1			T25	1		T51	2		T61	2
valid_sources[0x75]	2714	1			T43	1		T51	5		T36	75
valid_sources[0x76]	2250	1			T4	1		T25	1		T51	2
valid_sources[0x77]	2065	1			T2	4		T39	1		T59	1
valid_sources[0x78]	3394	1			T25	1		T77	2		T51	2
valid_sources[0x79]	2171	1			T26	3		T77	3		T51	2
valid_sources[0x7a]	2530	1			T51	4		T61	1		T36	39
valid_sources[0x7b]	2126	1			T78	1		T34	7		T51	1
valid_sources[0x7c]	2107	1			T25	2		T10	3		T51	10
valid_sources[0x7d]	2083	1			T2	5		T39	1		T43	1
valid_sources[0x7e]	2106	1			T77	2		T36	70		T45	1
valid_sources[0x7f]	2339	1			T25	1		T10	1		T61	4
valid_sources[0x80]	2054	1			T39	1		T43	1		T59	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

104425

1

T1

5

T2

13

T3

2

values[0x0]

all_enables

biggest_size

142884

1

T1

3

T2

10

T3

2

values[0x1]

all_enables

biggest_size

139971

1

T1

3

T2

2

T3

9