Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
62.50 62.50 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 62.50 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
62.50 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 52 24 28 53.85


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 24 28 53.85 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
non_zero_bins[0] 1930 1 T5 2 T9 3 T25 1
non_zero_bins[1] 1399 1 T5 1 T9 4 T25 1
zero 6660 1 T1 2 T2 6 T3 4



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd 333 1 T43 1 T40 1 T59 1
uni 2398 1 T2 1 T5 1 T25 3
gen 3438 1 T1 1 T2 3 T3 2
res 676 1 T5 1 T9 3 T15 2
ins 3144 1 T1 1 T2 2 T3 2



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
mubi_false 6390 1 T1 2 T2 1 T3 3
mubi_true 3599 1 T2 5 T3 1 T9 4



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 34 1 T10 1 T124 1 T172 1
pass 9955 1 T1 2 T2 6 T3 4



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 52 24 28 53.85 24
Automatically Generated Cross Bins 52 24 28 53.85 24
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] * [fail] * -- -- 6
[uni] [zero] [fail] * -- -- 2
[gen , res] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 8
[ins] * [fail] * -- -- 6


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[gen , res] [zero] [fail] [mubi_true] -- -- 2


Covered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd non_zero_bins[0] pass mubi_false 71 1 T59 1 T36 2 T45 1
upd non_zero_bins[0] pass mubi_true 75 1 T43 1 T61 1 T36 2
upd non_zero_bins[1] pass mubi_false 50 1 T40 1 T36 1 T281 1
upd non_zero_bins[1] pass mubi_true 61 1 T108 1 T47 1 T50 1
upd zero pass mubi_false 44 1 T36 3 T37 3 T108 1
upd zero pass mubi_true 32 1 T36 2 T46 1 T38 1
uni zero pass mubi_false 1796 1 T2 1 T5 1 T25 3
uni zero pass mubi_true 602 1 T78 1 T60 1 T51 6
gen non_zero_bins[0] pass mubi_false 397 1 T5 1 T9 3 T25 1
gen non_zero_bins[0] pass mubi_true 386 1 T51 1 T36 3 T37 6
gen non_zero_bins[1] pass mubi_false 306 1 T51 1 T36 2 T227 1
gen non_zero_bins[1] pass mubi_true 291 1 T15 4 T59 1 T51 3
gen zero fail mubi_false 32 1 T10 1 T124 1 T172 1
gen zero pass mubi_false 1325 1 T1 1 T3 1 T4 1
gen zero pass mubi_true 701 1 T2 3 T3 1 T10 2
res non_zero_bins[0] pass mubi_false 143 1 T5 1 T51 1 T36 3
res non_zero_bins[0] pass mubi_true 154 1 T15 2 T36 1 T37 2
res non_zero_bins[1] pass mubi_false 110 1 T51 1 T36 2 T37 1
res non_zero_bins[1] pass mubi_true 109 1 T9 3 T44 1 T36 2
res zero fail mubi_false 2 1 T159 1 T68 1 - -
res zero pass mubi_false 100 1 T37 1 T23 1 T108 1
res zero pass mubi_true 58 1 T36 1 T80 2 T214 1
ins non_zero_bins[0] pass mubi_false 352 1 T15 1 T43 1 T40 1
ins non_zero_bins[0] pass mubi_true 352 1 T59 1 T51 4 T36 6
ins non_zero_bins[1] pass mubi_false 232 1 T5 1 T51 2 T61 1
ins non_zero_bins[1] pass mubi_true 240 1 T9 1 T25 1 T44 1
ins zero pass mubi_false 1430 1 T1 1 T3 2 T4 1
ins zero pass mubi_true 538 1 T2 2 T25 1 T10 1


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded

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