Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.28	100.00	90.88			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T35,T94
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T32,T31
1	0	1	Covered	T3,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T15

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	25930584	682220	0	0
DepthKnown_A	26820280	26404896	0	0
RvalidKnown_A	26820280	26404896	0	0
WreadyKnown_A	26820280	26404896	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	26295000	779138	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25930584	682220	0	0
T6	0	418	0	0
T9	6032	3798	0	0
T10	4676	530	0	0
T11	4020	305	0	0
T15	9370	3425	0	0
T23	0	634	0	0
T25	4972	0	0	0
T26	5202	0	0	0
T34	148	0	0	0
T39	3204	501	0	0
T77	4194	404	0	0
T78	3078	0	0	0
T81	0	261	0	0
T95	0	285	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26820280	26404896	0	0
T1	3810	3540	0	0
T2	4104	3944	0	0
T3	3622	3316	0	0
T4	2378	1998	0	0
T5	4558	4358	0	0
T9	6032	5908	0	0
T10	4676	4476	0	0
T24	2522	2356	0	0
T25	4972	4808	0	0
T26	5202	5010	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26820280	26404896	0	0
T1	3810	3540	0	0
T2	4104	3944	0	0
T3	3622	3316	0	0
T4	2378	1998	0	0
T5	4558	4358	0	0
T9	6032	5908	0	0
T10	4676	4476	0	0
T24	2522	2356	0	0
T25	4972	4808	0	0
T26	5202	5010	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26820280	26404896	0	0
T1	3810	3540	0	0
T2	4104	3944	0	0
T3	3622	3316	0	0
T4	2378	1998	0	0
T5	4558	4358	0	0
T9	6032	5908	0	0
T10	4676	4476	0	0
T24	2522	2356	0	0
T25	4972	4808	0	0
T26	5202	5010	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	26295000	779138	0	0
T3	3622	2803	0	0
T4	2378	0	0	0
T5	4558	0	0	0
T9	6032	3798	0	0
T10	4676	530	0	0
T11	4020	305	0	0
T15	9370	3425	0	0
T16	0	220	0	0
T24	2522	0	0	0
T25	4972	0	0	0
T26	5202	0	0	0
T34	0	290	0	0
T39	0	501	0	0
T77	0	404	0	0
T95	0	285	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T96,T35
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35,T94,T97
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T98,T99
1	0	1	Covered	T3,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T15,T39

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	12965292	335337	0	0
DepthKnown_A	13410140	13202448	0	0
RvalidKnown_A	13410140	13202448	0	0
WreadyKnown_A	13410140	13202448	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	13147500	383382	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12965292	335337	0	0
T6	0	139	0	0
T9	3016	1887	0	0
T10	2338	267	0	0
T11	2010	142	0	0
T15	4685	1658	0	0
T23	0	321	0	0
T25	2486	0	0	0
T26	2601	0	0	0
T34	74	0	0	0
T39	1602	252	0	0
T77	2097	288	0	0
T78	1539	0	0	0
T81	0	192	0	0
T95	0	133	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	13147500	383382	0	0
T3	1811	1406	0	0
T4	1189	0	0	0
T5	2279	0	0	0
T9	3016	1887	0	0
T10	2338	267	0	0
T11	2010	142	0	0
T15	4685	1658	0	0
T16	0	111	0	0
T24	1261	0	0	0
T25	2486	0	0	0
T26	2601	0	0	0
T34	0	146	0	0
T39	0	252	0	0
T77	0	288	0	0
T95	0	133	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T100
1	1	0	Not Covered
1	1	1	Covered	T3,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T32,T101
1	0	1	Covered	T3,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	12965292	346883	0	0
DepthKnown_A	13410140	13202448	0	0
RvalidKnown_A	13410140	13202448	0	0
WreadyKnown_A	13410140	13202448	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	13147500	395756	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12965292	346883	0	0
T6	0	279	0	0
T9	3016	1911	0	0
T10	2338	263	0	0
T11	2010	163	0	0
T15	4685	1767	0	0
T23	0	313	0	0
T25	2486	0	0	0
T26	2601	0	0	0
T34	74	0	0	0
T39	1602	249	0	0
T77	2097	116	0	0
T78	1539	0	0	0
T81	0	69	0	0
T95	0	152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13410140	13202448	0	0
T1	1905	1770	0	0
T2	2052	1972	0	0
T3	1811	1658	0	0
T4	1189	999	0	0
T5	2279	2179	0	0
T9	3016	2954	0	0
T10	2338	2238	0	0
T24	1261	1178	0	0
T25	2486	2404	0	0
T26	2601	2505	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	13147500	395756	0	0
T3	1811	1397	0	0
T4	1189	0	0	0
T5	2279	0	0	0
T9	3016	1911	0	0
T10	2338	263	0	0
T11	2010	163	0	0
T15	4685	1767	0	0
T16	0	109	0	0
T24	1261	0	0	0
T25	2486	0	0	0
T26	2601	0	0	0
T34	0	144	0	0
T39	0	249	0	0
T77	0	116	0	0
T95	0	152	0	0