Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg

Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
75.00	75.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_sw_cmd_sts_cg	75.00	1	100	1	64	64

---

Group Instance : edn_sw_cmd_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

---

Summary for Group Instance edn_sw_cmd_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	3	9	75.00

Variables for Group Instance edn_sw_cmd_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_cmd_ack_cg	2	0	2	100.00	100	1	1	0
cp_cmd_rdy_cg	2	0	2	100.00	100	1	1	0
cp_cmd_reg_rdy_cg	2	0	2	100.00	100	1	1	0
cp_cmd_sts_cg	6	3	3	50.00	100	1	1	0

Summary for Variable cp_cmd_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_cmd_ack_cg

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

no_ack

16164

1

T1

1

T2

1

T3

3

ack

12106

1

T1

5

T2

5

T3

9

---

Summary for Variable cp_cmd_rdy_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_cmd_rdy_cg

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_ready

15439

1

T3

2

T6

10

T10

7

ready

12831

1

T1

6

T2

6

T3

10

---

Summary for Variable cp_cmd_reg_rdy_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_cmd_reg_rdy_cg

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_ready

408

1

T10

2

T11

1

T21

1

ready

27862

1

T1

6

T2

6

T3

12

---

Summary for Variable cp_cmd_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	6	3	3	50.00

Automatically Generated Bins for cp_cmd_sts_cg

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[CMD_STS_INVALID_GEN_CMD]	0	1	1
auto[CMD_STS_INVALID_CMD_SEQ]	0	1	1
auto[CMD_STS_UNDRIVEN]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[CMD_STS_SUCCESS]	28268	1			T1	6		T2	6		T3	12
auto[CMD_STS_INVALID_ACMD]	1	1			T88	1		-	-		-	-
auto[CMD_STS_RESEED_CNT_EXCEEDED]	1	1			T256	1		-	-		-	-