Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155099	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

328514

1

T1

9

T2

7

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	204061	1			T1	20		T2	76		T3	37
values[0x0]	132540	1			T1	5		T2	6		T3	9
values[0x1]	147012	1			T1	4		T2	2		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	104588	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

379025

1

T1

16

T2

36

T3

30

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1991	1			T73	1		T59	1		T18	5
valid_sources[0x01]	1889	1			T6	4		T21	3		T59	1
valid_sources[0x02]	2031	1			T59	6		T30	1		T18	13
valid_sources[0x03]	1775	1			T10	1		T7	1		T59	3
valid_sources[0x04]	1646	1			T10	1		T74	67		T59	8
valid_sources[0x05]	1582	1			T6	1		T21	2		T59	1
valid_sources[0x06]	1517	1			T21	2		T59	2		T18	5
valid_sources[0x07]	2046	1			T6	5		T16	1		T18	1
valid_sources[0x08]	2199	1			T23	2		T85	1		T97	1
valid_sources[0x09]	2293	1			T59	3		T18	2		T85	1
valid_sources[0x0a]	1916	1			T2	1		T30	12		T19	6
valid_sources[0x0b]	2744	1			T17	1		T73	1		T21	3
valid_sources[0x0c]	2260	1			T25	2		T73	1		T18	2
valid_sources[0x0d]	1501	1			T29	2		T109	3		T18	8
valid_sources[0x0e]	1622	1			T25	1		T43	4		T355	3
valid_sources[0x0f]	2385	1			T12	2		T7	1		T254	3
valid_sources[0x10]	1797	1			T10	2		T7	1		T18	11
valid_sources[0x11]	1606	1			T18	2		T23	1		T19	1
valid_sources[0x12]	1616	1			T5	3		T6	2		T12	1
valid_sources[0x13]	1632	1			T10	1		T59	6		T125	1
valid_sources[0x14]	2427	1			T6	4		T7	2		T73	2
valid_sources[0x15]	2801	1			T7	3		T73	1		T59	3
valid_sources[0x16]	1933	1			T17	1		T6	6		T25	1
valid_sources[0x17]	1601	1			T2	3		T7	2		T18	13
valid_sources[0x18]	1775	1			T2	4		T10	2		T7	1
valid_sources[0x19]	1960	1			T2	4		T6	5		T10	1
valid_sources[0x1a]	1636	1			T17	1		T10	1		T59	2
valid_sources[0x1b]	1851	1			T67	1		T23	1		T32	1
valid_sources[0x1c]	2609	1			T17	1		T6	1		T10	1
valid_sources[0x1d]	2079	1			T17	1		T22	1		T109	1
valid_sources[0x1e]	1767	1			T21	1		T59	1		T18	1
valid_sources[0x1f]	2782	1			T26	21		T59	4		T125	1
valid_sources[0x20]	1625	1			T59	2		T22	2		T18	2
valid_sources[0x21]	1520	1			T21	1		T18	1		T19	2
valid_sources[0x22]	2027	1			T1	29		T10	1		T7	4
valid_sources[0x23]	2318	1			T22	1		T109	2		T13	137
valid_sources[0x24]	1619	1			T59	4		T23	1		T43	2
valid_sources[0x25]	1720	1			T2	17		T59	1		T109	1
valid_sources[0x26]	1924	1			T10	2		T73	2		T59	5
valid_sources[0x27]	1887	1			T27	2		T16	1		T59	6
valid_sources[0x28]	1907	1			T6	3		T59	1		T18	24
valid_sources[0x29]	1902	1			T10	1		T7	3		T21	5
valid_sources[0x2a]	2408	1			T6	16		T75	1		T55	8
valid_sources[0x2b]	1937	1			T17	1		T18	1		T66	1
valid_sources[0x2c]	1516	1			T6	2		T25	2		T10	1
valid_sources[0x2d]	1643	1			T10	1		T16	1		T59	2
valid_sources[0x2e]	1572	1			T6	4		T12	1		T16	1
valid_sources[0x2f]	1940	1			T6	5		T10	1		T59	1
valid_sources[0x30]	1962	1			T6	8		T22	1		T109	1
valid_sources[0x31]	2199	1			T6	2		T16	1		T59	5
valid_sources[0x32]	1670	1			T17	1		T25	1		T7	2
valid_sources[0x33]	1965	1			T17	3		T16	1		T59	3
valid_sources[0x34]	1409	1			T59	1		T125	1		T67	1
valid_sources[0x35]	1689	1			T59	2		T254	1		T23	1
valid_sources[0x36]	2057	1			T18	21		T355	4		T20	4
valid_sources[0x37]	1586	1			T6	4		T10	1		T59	2
valid_sources[0x38]	1790	1			T7	1		T59	9		T30	5
valid_sources[0x39]	1666	1			T5	1		T6	2		T59	2
valid_sources[0x3a]	1864	1			T17	1		T6	3		T109	1
valid_sources[0x3b]	1946	1			T59	1		T18	3		T20	2
valid_sources[0x3c]	1515	1			T10	1		T59	3		T23	2
valid_sources[0x3d]	1924	1			T17	1		T6	6		T73	2
valid_sources[0x3e]	1747	1			T4	26		T18	16		T19	6
valid_sources[0x3f]	2169	1			T65	476		T23	2		T85	1
valid_sources[0x40]	2016	1			T10	1		T70	33		T59	3
valid_sources[0x41]	2095	1			T17	1		T10	1		T59	1
valid_sources[0x42]	1728	1			T6	2		T73	1		T18	5
valid_sources[0x43]	1876	1			T25	2		T10	2		T73	1
valid_sources[0x44]	2645	1			T73	1		T22	5		T30	2
valid_sources[0x45]	2771	1			T17	1		T30	2		T23	1
valid_sources[0x46]	2146	1			T59	1		T109	1		T19	5
valid_sources[0x47]	1871	1			T10	1		T59	2		T18	13
valid_sources[0x48]	1849	1			T73	1		T30	1		T40	37
valid_sources[0x49]	1387	1			T21	1		T59	1		T109	1
valid_sources[0x4a]	1558	1			T2	16		T10	1		T7	1
valid_sources[0x4b]	1460	1			T17	1		T7	1		T16	1
valid_sources[0x4c]	1532	1			T3	51		T6	4		T125	1
valid_sources[0x4d]	1715	1			T6	6		T10	1		T21	1
valid_sources[0x4e]	1826	1			T10	2		T16	1		T59	1
valid_sources[0x4f]	1933	1			T7	2		T125	1		T18	3
valid_sources[0x50]	2186	1			T25	1		T10	1		T7	1
valid_sources[0x51]	2188	1			T2	3		T6	2		T10	1
valid_sources[0x52]	1839	1			T17	1		T59	1		T30	1
valid_sources[0x53]	1775	1			T6	1		T10	1		T7	2
valid_sources[0x54]	1999	1			T10	1		T7	2		T59	1
valid_sources[0x55]	2410	1			T6	2		T55	4		T72	4
valid_sources[0x56]	2193	1			T17	7		T6	1		T10	2
valid_sources[0x57]	2003	1			T6	1		T125	1		T308	1
valid_sources[0x58]	1918	1			T6	1		T30	1		T255	1
valid_sources[0x59]	2024	1			T6	1		T16	1		T59	1
valid_sources[0x5a]	1744	1			T10	2		T73	1		T59	1
valid_sources[0x5b]	2335	1			T6	11		T59	1		T18	7
valid_sources[0x5c]	2452	1			T59	2		T22	1		T18	14
valid_sources[0x5d]	1924	1			T29	1		T12	1		T21	1
valid_sources[0x5e]	2120	1			T6	2		T59	9		T67	2
valid_sources[0x5f]	2174	1			T59	1		T23	2		T43	1
valid_sources[0x60]	1842	1			T16	2		T21	3		T67	1
valid_sources[0x61]	1375	1			T59	2		T19	6		T97	1
valid_sources[0x62]	1692	1			T7	2		T22	1		T23	1
valid_sources[0x63]	2405	1			T59	1		T18	3		T19	8
valid_sources[0x64]	1880	1			T7	1		T59	2		T18	3
valid_sources[0x65]	1828	1			T17	1		T16	1		T21	1
valid_sources[0x66]	1886	1			T16	1		T73	1		T66	1
valid_sources[0x67]	1467	1			T6	5		T7	1		T59	3
valid_sources[0x68]	1734	1			T6	2		T25	1		T59	3
valid_sources[0x69]	1591	1			T6	6		T7	1		T73	1
valid_sources[0x6a]	1604	1			T25	1		T59	7		T22	2
valid_sources[0x6b]	1806	1			T59	4		T22	1		T109	1
valid_sources[0x6c]	1748	1			T2	1		T24	7		T6	8
valid_sources[0x6d]	2007	1			T10	1		T7	3		T59	4
valid_sources[0x6e]	2282	1			T21	2		T59	5		T71	8
valid_sources[0x6f]	1640	1			T59	1		T18	6		T23	1
valid_sources[0x70]	1575	1			T59	2		T97	1		T355	1
valid_sources[0x71]	1497	1			T10	1		T16	1		T59	2
valid_sources[0x72]	1992	1			T59	3		T255	1		T23	3
valid_sources[0x73]	1777	1			T6	4		T10	1		T73	1
valid_sources[0x74]	1934	1			T59	6		T22	1		T109	1
valid_sources[0x75]	1921	1			T17	1		T6	2		T10	1
valid_sources[0x76]	1746	1			T16	1		T73	2		T125	1
valid_sources[0x77]	2042	1			T16	2		T18	16		T43	6
valid_sources[0x78]	1811	1			T59	8		T67	1		T97	3
valid_sources[0x79]	2073	1			T57	182		T67	1		T19	3
valid_sources[0x7a]	1950	1			T6	2		T55	1		T43	1
valid_sources[0x7b]	2002	1			T16	1		T59	8		T75	1
valid_sources[0x7c]	2581	1			T16	2		T73	2		T21	3
valid_sources[0x7d]	1488	1			T5	2		T7	2		T67	1
valid_sources[0x7e]	2162	1			T59	2		T23	1		T69	328
valid_sources[0x7f]	1593	1			T5	4		T10	1		T16	1
valid_sources[0x80]	2016	1			T10	2		T16	1		T59	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

89628

1

T1

4

T2

3

T3

8

values[0x0]

all_enables

biggest_size

121035

1

T1

4

T2

3

T3

6

values[0x1]

all_enables

biggest_size

117851

1

T1

1

T2

1

T3

3