Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
62.50	62.50	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	62.50	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.50	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	24	28	53.85

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	24	28	53.85	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1748	1			T3	1		T6	3		T10	4
non_zero_bins[1]	1274	1			T10	2		T21	2		T59	3
zero	6189	1			T1	3		T2	3		T3	4

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	301	1			T57	1		T59	2		T60	3
uni	2155	1			T1	1		T2	1		T3	2
gen	3202	1			T1	1		T2	1		T3	1
res	653	1			T6	1		T10	4		T11	2
ins	2900	1			T1	1		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

5794

1

T1

2

T2

2

T3

1

mubi_true

3417

1

T1

1

T2

1

T3

4

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

34

1

T30

1

T131

1

T76

1

pass

9177

1

T1

3

T2

3

T3

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	24	28	53.85	24
Automatically Generated Cross Bins	52	24	28	53.85	24
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[uni]	[zero]	[fail]	*	--	--	2
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	*	[fail]	*	--	--	6

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	69	1			T59	1		T123	1		T116	1
upd	non_zero_bins[0]	pass	mubi_true	82	1			T59	1		T60	2		T37	2
upd	non_zero_bins[1]	pass	mubi_false	47	1			T60	1		T118	1		T290	1
upd	non_zero_bins[1]	pass	mubi_true	46	1			T69	1		T128	1		T241	1
upd	zero	pass	mubi_false	22	1			T291	1		T292	1		T293	1
upd	zero	pass	mubi_true	35	1			T57	1		T38	2		T236	3
uni	zero	pass	mubi_false	1622	1			T3	1		T6	4		T25	1
uni	zero	pass	mubi_true	533	1			T1	1		T2	1		T3	1
gen	non_zero_bins[0]	pass	mubi_false	346	1			T11	3		T60	2		T13	8
gen	non_zero_bins[0]	pass	mubi_true	373	1			T6	1		T57	1		T59	1
gen	non_zero_bins[1]	pass	mubi_false	241	1			T59	2		T65	1		T69	2
gen	non_zero_bins[1]	pass	mubi_true	284	1			T59	1		T60	2		T40	1
gen	zero	fail	mubi_false	26	1			T30	1		T76	1		T132	1
gen	zero	pass	mubi_false	1250	1			T1	1		T2	1		T17	1
gen	zero	pass	mubi_true	682	1			T3	1		T17	2		T24	2
res	non_zero_bins[0]	pass	mubi_false	132	1			T6	1		T65	1		T48	4
res	non_zero_bins[0]	pass	mubi_true	153	1			T10	2		T11	2		T22	3
res	non_zero_bins[1]	pass	mubi_false	96	1			T10	2		T60	1		T55	1
res	non_zero_bins[1]	pass	mubi_true	110	1			T21	2		T13	2		T65	1
res	zero	fail	mubi_false	8	1			T131	1		T172	1		T173	1
res	zero	pass	mubi_false	93	1			T59	2		T294	1		T89	1
res	zero	pass	mubi_true	61	1			T84	2		T160	3		T52	1
ins	non_zero_bins[0]	pass	mubi_false	294	1			T10	1		T59	1		T22	1
ins	non_zero_bins[0]	pass	mubi_true	299	1			T3	1		T6	1		T10	1
ins	non_zero_bins[1]	pass	mubi_false	217	1			T60	1		T40	1		T65	1
ins	non_zero_bins[1]	pass	mubi_true	233	1			T60	2		T65	1		T69	1
ins	zero	pass	mubi_false	1331	1			T1	1		T2	1		T17	1
ins	zero	pass	mubi_true	526	1			T3	1		T17	1		T5	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded