Line Coverage for Module : edn_main_sm
Cond Coverage for Module : edn_main_sm
FSM Coverage for Module : edn_main_sm
State, Transition and Sequence Details for FSM :: state_q
Branch Coverage for Module : edn_main_sm
Branches:
Branches:
Branches:
Assert Coverage for Module : edn_main_sm
Assertion Details
ErrorStStable_A
FpvSecCmErrorStEscalate_A
u_state_regs_A
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| TOTAL | 108 | 108 | 100.00 | |
| ALWAYS | 42 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| ALWAYS | 47 | 104 | 104 | 100.00 |
4142 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Idle) Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Idle): 42.1 `ifdef SIMULATION 42.2 prim_sparse_fsm_flop #( 42.3 .StateEnumT(state_e), 42.4 .Width($bits(state_e)), 42.5 .ResetValue($bits(state_e)'(Idle)), 42.6 .EnableAlertTriggerSVA(1), 42.7 .CustomForceName("state_q") 42.8 ) u_state_regs ( 42.9 .clk_i ( clk_i ), 42.10 .rst_ni ( rst_ni ), 42.11 .state_i ( state_d ), 42.12 .state_o ( ) 42.13 ); 42.14 always_ff @(posedge clk_i or negedge rst_ni) begin 42.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3 42.16 1/1 state_q <= Idle; Tests: T1 T2 T3 42.17 end else begin 42.18 1/1 state_q <= state_d; Tests: T1 T2 T3 42.19 end 42.20 end 42.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 42.22 else begin 42.23 `ifdef UVM 42.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 42.25 "../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv", 42, "", 1); 42.26 `else 42.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 42.28 `PRIM_STRINGIFY(u_state_regs_A)); 42.29 `endif 42.30 end 42.31 `else 42.32 prim_sparse_fsm_flop #( 42.33 .StateEnumT(state_e), 42.34 .Width($bits(state_e)), 42.35 .ResetValue($bits(state_e)'(Idle)), 42.36 .EnableAlertTriggerSVA(1) 42.37 ) u_state_regs ( 42.38 .clk_i ( `PRIM_FLOP_CLK ), 42.39 .rst_ni ( `PRIM_FLOP_RST ), 42.40 .state_i ( state_d ), 42.41 .state_o ( state_q ) 42.42 ); 42.43 `endif43 44 1/1 assign main_sm_state_o = state_q; Tests: T1 T2 T3 45 46 always_comb begin 47 1/1 state_d = state_q; Tests: T1 T2 T3 48 1/1 boot_wr_ins_cmd_o = 1'b0; Tests: T1 T2 T3 49 1/1 boot_send_ins_cmd_o = 1'b0; Tests: T1 T2 T3 50 1/1 boot_wr_gen_cmd_o = 1'b0; Tests: T1 T2 T3 51 1/1 boot_wr_uni_cmd_o = 1'b0; Tests: T1 T2 T3 52 1/1 accept_sw_cmds_pulse_o = 1'b0; Tests: T1 T2 T3 53 1/1 auto_req_mode_busy_o = 1'b0; Tests: T1 T2 T3 54 1/1 capt_gencmd_fifo_cnt_o = 1'b0; Tests: T1 T2 T3 55 1/1 send_gencmd_o = 1'b0; Tests: T1 T2 T3 56 1/1 capt_rescmd_fifo_cnt_o = 1'b0; Tests: T1 T2 T3 57 1/1 send_rescmd_o = 1'b0; Tests: T1 T2 T3 58 1/1 main_sm_done_pulse_o = 1'b0; Tests: T1 T2 T3 59 1/1 main_sm_err_o = 1'b0; Tests: T1 T2 T3 60 1/1 reject_csrng_entropy_o = 1'b0; Tests: T1 T2 T3 61 1/1 sw_cmd_mode_o = 1'b0; Tests: T1 T2 T3 62 1/1 unique case (state_q) Tests: T1 T2 T3 63 Idle: begin 64 1/1 if (boot_req_mode_i && edn_enable_i) begin Tests: T1 T2 T3 65 1/1 state_d = BootLoadIns; Tests: T17 T5 T24 66 1/1 end else if (auto_req_mode_i && edn_enable_i) begin Tests: T1 T2 T3 67 1/1 accept_sw_cmds_pulse_o = 1'b1; Tests: T17 T10 T11 68 1/1 sw_cmd_mode_o = 1'b1; Tests: T17 T10 T11 69 1/1 state_d = AutoLoadIns; Tests: T17 T10 T11 70 1/1 end else if (edn_enable_i) begin Tests: T1 T2 T3 71 1/1 main_sm_done_pulse_o = 1'b1; Tests: T1 T2 T3 72 1/1 accept_sw_cmds_pulse_o = 1'b1; Tests: T1 T2 T3 73 1/1 sw_cmd_mode_o = 1'b1; Tests: T1 T2 T3 74 1/1 state_d = SWPortMode; Tests: T1 T2 T3 75 end MISSING_ELSE 76 end 77 BootLoadIns: begin 78 1/1 boot_wr_ins_cmd_o = 1'b1; Tests: T17 T5 T24 79 1/1 boot_send_ins_cmd_o = 1'b1; Tests: T17 T5 T24 80 1/1 state_d = BootInsAckWait; Tests: T17 T5 T24 81 end 82 BootInsAckWait: begin 83 1/1 boot_send_ins_cmd_o = 1'b1; Tests: T17 T5 T24 84 1/1 if (csrng_cmd_ack_i) begin Tests: T17 T5 T24 85 1/1 state_d = BootLoadGen; Tests: T17 T5 T24 86 end MISSING_ELSE 87 end 88 BootLoadGen: begin 89 1/1 boot_wr_gen_cmd_o = 1'b1; Tests: T17 T5 T24 90 1/1 state_d = BootGenAckWait; Tests: T17 T5 T24 91 end 92 BootGenAckWait: begin 93 1/1 if (csrng_cmd_ack_i) begin Tests: T17 T5 T24 94 1/1 state_d = BootPulse; Tests: T17 T5 T24 95 end MISSING_ELSE 96 end 97 BootPulse: begin 98 1/1 state_d = BootDone; Tests: T17 T5 T24 99 end 100 BootDone: begin 101 1/1 if (!boot_req_mode_i) begin Tests: T17 T5 T24 102 1/1 state_d = BootLoadUni; Tests: T17 T12 T75 103 end MISSING_ELSE 104 end 105 BootLoadUni: begin 106 1/1 boot_wr_uni_cmd_o = 1'b1; Tests: T17 T12 T75 107 1/1 state_d = BootUniAckWait; Tests: T17 T12 T75 108 end 109 BootUniAckWait: begin 110 1/1 if (csrng_cmd_ack_i) begin Tests: T12 T75 T30 111 1/1 main_sm_done_pulse_o = 1'b1; Tests: T40 T109 T53 112 1/1 state_d = Idle; Tests: T40 T109 T53 113 end MISSING_ELSE 114 end 115 //----------------------------------- 116 AutoLoadIns: begin 117 1/1 sw_cmd_mode_o = 1'b1; Tests: T17 T10 T11 118 1/1 if (sw_cmd_req_load_i) begin Tests: T17 T10 T11 119 1/1 state_d = AutoFirstAckWait; Tests: T10 T11 T12 120 end MISSING_ELSE 121 end 122 AutoFirstAckWait: begin 123 1/1 sw_cmd_mode_o = 1'b1; Tests: T10 T11 T12 124 1/1 if (csrng_cmd_ack_i) begin Tests: T10 T11 T12 125 1/1 state_d = AutoDispatch; Tests: T10 T11 T12 126 end MISSING_ELSE 127 end 128 AutoAckWait: begin 129 1/1 auto_req_mode_busy_o = 1'b1; Tests: T10 T11 T7 130 1/1 if (csrng_cmd_ack_i) begin Tests: T10 T11 T7 131 1/1 state_d = AutoDispatch; Tests: T10 T11 T7 132 end MISSING_ELSE 133 end 134 AutoDispatch: begin 135 1/1 auto_req_mode_busy_o = 1'b1; Tests: T10 T11 T12 136 1/1 if (!auto_req_mode_i) begin Tests: T10 T11 T12 137 1/1 main_sm_done_pulse_o = 1'b1; Tests: T11 T13 T43 138 1/1 state_d = Idle; Tests: T11 T13 T43 139 end else begin 140 1/1 if (max_reqs_cnt_zero_i) begin Tests: T10 T11 T12 141 1/1 state_d = AutoCaptReseedCnt; Tests: T10 T11 T7 142 end else begin 143 1/1 state_d = AutoCaptGenCnt; Tests: T10 T11 T12 144 end 145 end 146 end 147 AutoCaptGenCnt: begin 148 1/1 auto_req_mode_busy_o = 1'b1; Tests: T10 T11 T12 149 1/1 capt_gencmd_fifo_cnt_o = 1'b1; Tests: T10 T11 T12 150 1/1 state_d = AutoSendGenCmd; Tests: T10 T11 T12 151 end 152 AutoSendGenCmd: begin 153 1/1 auto_req_mode_busy_o = 1'b1; Tests: T10 T11 T12 154 1/1 send_gencmd_o = 1'b1; Tests: T10 T11 T12 155 1/1 if (cmd_sent_i) begin Tests: T10 T11 T12 156 1/1 state_d = AutoAckWait; Tests: T10 T11 T12 157 end MISSING_ELSE 158 end 159 AutoCaptReseedCnt: begin 160 1/1 auto_req_mode_busy_o = 1'b1; Tests: T10 T11 T7 161 1/1 capt_rescmd_fifo_cnt_o = 1'b1; Tests: T10 T11 T7 162 1/1 state_d = AutoSendReseedCmd; Tests: T10 T11 T7 163 end 164 AutoSendReseedCmd: begin 165 1/1 auto_req_mode_busy_o = 1'b1; Tests: T10 T11 T21 166 1/1 send_rescmd_o = 1'b1; Tests: T10 T11 T21 167 1/1 if (cmd_sent_i) begin Tests: T10 T11 T21 168 1/1 state_d = AutoAckWait; Tests: T10 T11 T21 169 end MISSING_ELSE 170 end 171 SWPortMode: begin 172 1/1 sw_cmd_mode_o = 1'b1; Tests: T1 T2 T3 173 end 174 RejectCsrngEntropy: begin 175 1/1 reject_csrng_entropy_o = 1'b1; Tests: T17 T12 T30 176 end 177 Error: begin 178 1/1 main_sm_err_o = 1'b1; Tests: T5 T7 T16 179 end 180 default: begin 181 state_d = Error; 182 main_sm_err_o = 1'b1; 183 end 184 endcase 185 186 1/1 if (local_escalate_i || csrng_ack_err_i) begin Tests: T1 T2 T3 187 // Either move into RejectCsrngEntropy or Error but don't move out of Error as it's terminal. 188 1/1 state_d = local_escalate_i ? Error : Tests: T17 T5 T12 189 state_q == Error ? Error : RejectCsrngEntropy; 190 // Tie off outputs, except for main_sm_err_o, auto_req_mode_busy_o, boot_send_ins_cmd_o, 191 // sw_cmd_mode_o and reject_csrng_entropy_o. 192 1/1 boot_wr_ins_cmd_o = 1'b0; Tests: T17 T5 T12 193 1/1 boot_wr_gen_cmd_o = 1'b0; Tests: T17 T5 T12 194 1/1 boot_wr_uni_cmd_o = 1'b0; Tests: T17 T5 T12 195 1/1 accept_sw_cmds_pulse_o = 1'b0; Tests: T17 T5 T12 196 1/1 capt_gencmd_fifo_cnt_o = 1'b0; Tests: T17 T5 T12 197 1/1 send_gencmd_o = 1'b0; Tests: T17 T5 T12 198 1/1 capt_rescmd_fifo_cnt_o = 1'b0; Tests: T17 T5 T12 199 1/1 send_rescmd_o = 1'b0; Tests: T17 T5 T12 200 1/1 main_sm_done_pulse_o = 1'b0; Tests: T17 T5 T12 201 1/1 end else if (!edn_enable_i && state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, Tests: T1 T2 T3 202 BootGenAckWait, BootLoadUni, BootUniAckWait, 203 BootPulse, BootDone, 204 AutoLoadIns, AutoFirstAckWait, AutoAckWait, 205 AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, 206 AutoCaptReseedCnt, AutoSendReseedCmd, 207 SWPortMode, RejectCsrngEntropy 208 }) begin 209 // Only go to idle if the state is legal and not Idle or Error. 210 // Even when disabled, illegal states must result in a transition to Error. 211 1/1 state_d = Idle; Tests: T17 T4 T5 212 // Tie off outputs, except for main_sm_err_o. 213 1/1 boot_wr_ins_cmd_o = 1'b0; Tests: T17 T4 T5 214 1/1 boot_send_ins_cmd_o = 1'b0; Tests: T17 T4 T5 215 1/1 boot_wr_gen_cmd_o = 1'b0; Tests: T17 T4 T5 216 1/1 boot_wr_uni_cmd_o = 1'b0; Tests: T17 T4 T5 217 1/1 accept_sw_cmds_pulse_o = 1'b0; Tests: T17 T4 T5 218 1/1 auto_req_mode_busy_o = 1'b0; Tests: T17 T4 T5 219 1/1 capt_gencmd_fifo_cnt_o = 1'b0; Tests: T17 T4 T5 220 1/1 send_gencmd_o = 1'b0; Tests: T17 T4 T5 221 1/1 capt_rescmd_fifo_cnt_o = 1'b0; Tests: T17 T4 T5 222 1/1 send_rescmd_o = 1'b0; Tests: T17 T4 T5 223 1/1 sw_cmd_mode_o = 1'b0; Tests: T17 T4 T5 224 1/1 reject_csrng_entropy_o = 1'b0; Tests: T17 T4 T5 225 1/1 main_sm_done_pulse_o = 1'b1; Tests: T17 T4 T5 226 end MISSING_ELSE
Cond Coverage for Module : edn_main_sm
| Total | Covered | Percent | |
|---|---|---|---|
| Conditions | 18 | 17 | 94.44 |
| Logical | 18 | 17 | 94.44 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 |
LINE 64
EXPRESSION (boot_req_mode_i && edn_enable_i)
-------1------- ------2-----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T24,T29 |
| 1 | 1 | Covered | T17,T5,T24 |
LINE 66
EXPRESSION (auto_req_mode_i && edn_enable_i)
-------1------- ------2-----
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T7,T21 |
| 1 | 1 | Covered | T17,T10,T11 |
LINE 186
EXPRESSION (local_escalate_i || csrng_ack_err_i)
--------1------- -------2-------
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T17,T12,T30 |
| 1 | 0 | Covered | T5,T7,T16 |
LINE 188
EXPRESSION (local_escalate_i ? Error : ((state_q == Error) ? Error : RejectCsrngEntropy))
--------1-------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T17,T12,T30 |
| 1 | Covered | T5,T7,T16 |
LINE 188
SUB-EXPRESSION ((state_q == Error) ? Error : RejectCsrngEntropy)
---------1--------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T17,T12,T30 |
| 1 | Not Covered |
LINE 188
SUB-EXPRESSION (state_q == Error)
---------1--------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T17,T5,T12 |
| 1 | Covered | T5,T7,T16 |
LINE 201
EXPRESSION
Number Term
1 ((!edn_enable_i)) &&
2 (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T17,T4,T5 |
FSM Coverage for Module : edn_main_sm
| Total | Covered | Percent | ||
|---|---|---|---|---|
| States | 20 | 20 | 100.00 | (Not included in score) |
| Transitions | 74 | 72 | 97.30 | |
| Sequences | 0 | 0 |
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| AutoAckWait | 156 | Covered | T10,T11,T7 |
| AutoCaptGenCnt | 143 | Covered | T10,T11,T12 |
| AutoCaptReseedCnt | 141 | Covered | T10,T11,T7 |
| AutoDispatch | 125 | Covered | T10,T11,T12 |
| AutoFirstAckWait | 119 | Covered | T10,T11,T12 |
| AutoLoadIns | 69 | Covered | T17,T10,T11 |
| AutoSendGenCmd | 150 | Covered | T10,T11,T12 |
| AutoSendReseedCmd | 162 | Covered | T10,T11,T21 |
| BootDone | 98 | Covered | T17,T5,T24 |
| BootGenAckWait | 90 | Covered | T17,T5,T24 |
| BootInsAckWait | 80 | Covered | T17,T5,T24 |
| BootLoadGen | 85 | Covered | T17,T5,T24 |
| BootLoadIns | 65 | Covered | T17,T5,T24 |
| BootLoadUni | 102 | Covered | T17,T12,T75 |
| BootPulse | 94 | Covered | T17,T5,T24 |
| BootUniAckWait | 107 | Covered | T12,T75,T30 |
| Error | 188 | Covered | T5,T7,T16 |
| Idle | 112 | Covered | T1,T2,T3 |
| RejectCsrngEntropy | 188 | Covered | T17,T12,T30 |
| SWPortMode | 74 | Covered | T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| AutoAckWait->AutoDispatch | 131 | Covered | T10,T11,T7 |
| AutoAckWait->Error | 188 | Covered | T8,T140,T110 |
| AutoAckWait->Idle | 211 | Covered | T10,T21,T22 |
| AutoAckWait->RejectCsrngEntropy | 188 | Covered | T30,T76,T132 |
| AutoCaptGenCnt->AutoSendGenCmd | 150 | Covered | T10,T11,T12 |
| AutoCaptGenCnt->Error | 188 | Covered | T141,T142,T143 |
| AutoCaptGenCnt->Idle | 211 | Covered | T115,T144,T145 |
| AutoCaptGenCnt->RejectCsrngEntropy | 188 | Covered | T67,T96,T146 |
| AutoCaptReseedCnt->AutoSendReseedCmd | 162 | Covered | T10,T11,T21 |
| AutoCaptReseedCnt->Error | 188 | Covered | T7,T147,T148 |
| AutoCaptReseedCnt->Idle | 211 | Covered | T23,T149,T150 |
| AutoCaptReseedCnt->RejectCsrngEntropy | 188 | Covered | T151,T152,T153 |
| AutoDispatch->AutoCaptGenCnt | 143 | Covered | T10,T11,T12 |
| AutoDispatch->AutoCaptReseedCnt | 141 | Covered | T10,T11,T7 |
| AutoDispatch->Error | 188 | Covered | T154 |
| AutoDispatch->Idle | 138 | Covered | T11,T13,T43 |
| AutoDispatch->RejectCsrngEntropy | 188 | Covered | T155,T156,T157 |
| AutoFirstAckWait->AutoDispatch | 125 | Covered | T10,T11,T12 |
| AutoFirstAckWait->Error | 188 | Covered | T158,T159 |
| AutoFirstAckWait->Idle | 211 | Covered | T22,T55,T160 |
| AutoFirstAckWait->RejectCsrngEntropy | 188 | Covered | T161,T162,T163 |
| AutoLoadIns->AutoFirstAckWait | 119 | Covered | T10,T11,T12 |
| AutoLoadIns->Error | 188 | Covered | T9,T164,T165 |
| AutoLoadIns->Idle | 211 | Covered | T17,T7,T21 |
| AutoLoadIns->RejectCsrngEntropy | 188 | Covered | T166,T167,T168 |
| AutoSendGenCmd->AutoAckWait | 156 | Covered | T10,T11,T7 |
| AutoSendGenCmd->Error | 188 | Not Covered | |
| AutoSendGenCmd->Idle | 211 | Covered | T10,T84,T169 |
| AutoSendGenCmd->RejectCsrngEntropy | 188 | Covered | T12,T134,T105 |
| AutoSendReseedCmd->AutoAckWait | 168 | Covered | T10,T11,T21 |
| AutoSendReseedCmd->Error | 188 | Covered | T170,T171,T136 |
| AutoSendReseedCmd->Idle | 211 | Covered | T97,T124,T95 |
| AutoSendReseedCmd->RejectCsrngEntropy | 188 | Covered | T131,T172,T173 |
| BootDone->BootLoadUni | 102 | Covered | T17,T12,T75 |
| BootDone->Error | 188 | Covered | T174,T175,T176 |
| BootDone->Idle | 211 | Covered | T81,T177,T56 |
| BootDone->RejectCsrngEntropy | 188 | Covered | T178,T179,T180 |
| BootGenAckWait->BootPulse | 94 | Covered | T17,T5,T24 |
| BootGenAckWait->Error | 188 | Covered | T181,T182 |
| BootGenAckWait->Idle | 211 | Covered | T24,T29,T101 |
| BootGenAckWait->RejectCsrngEntropy | 188 | Covered | T47,T82,T183 |
| BootInsAckWait->BootLoadGen | 85 | Covered | T17,T5,T24 |
| BootInsAckWait->Error | 188 | Covered | T5,T177,T184 |
| BootInsAckWait->Idle | 211 | Covered | T5,T75,T66 |
| BootInsAckWait->RejectCsrngEntropy | 188 | Covered | T133,T58,T185 |
| BootLoadGen->BootGenAckWait | 90 | Covered | T17,T5,T24 |
| BootLoadGen->Error | 188 | Covered | T186,T187,T188 |
| BootLoadGen->Idle | 211 | Covered | T98,T90,T189 |
| BootLoadGen->RejectCsrngEntropy | 188 | Covered | T100,T190,T191 |
| BootLoadIns->BootInsAckWait | 80 | Covered | T17,T5,T24 |
| BootLoadIns->Error | 188 | Covered | T192,T193,T194 |
| BootLoadIns->Idle | 211 | Covered | T77,T195,T196 |
| BootLoadIns->RejectCsrngEntropy | 188 | Covered | T197,T198,T199 |
| BootLoadUni->BootUniAckWait | 107 | Covered | T12,T75,T30 |
| BootLoadUni->Error | 188 | Covered | T200,T201,T202 |
| BootLoadUni->Idle | 211 | Not Covered | |
| BootLoadUni->RejectCsrngEntropy | 188 | Covered | T17,T203,T204 |
| BootPulse->BootDone | 98 | Covered | T17,T5,T24 |
| BootPulse->Error | 188 | Covered | T205 |
| BootPulse->Idle | 211 | Covered | T42,T99,T83 |
| BootPulse->RejectCsrngEntropy | 188 | Covered | T206,T207,T208 |
| BootUniAckWait->Error | 188 | Covered | T209 |
| BootUniAckWait->Idle | 112 | Covered | T12,T30,T40 |
| BootUniAckWait->RejectCsrngEntropy | 188 | Covered | T109,T86,T210 |
| Idle->AutoLoadIns | 69 | Covered | T17,T10,T11 |
| Idle->BootLoadIns | 65 | Covered | T17,T5,T24 |
| Idle->Error | 188 | Covered | T18,T19,T20 |
| Idle->RejectCsrngEntropy | 188 | Covered | T12,T30,T58 |
| Idle->SWPortMode | 74 | Covered | T1,T2,T3 |
| RejectCsrngEntropy->Error | 188 | Covered | T211,T212,T213 |
| RejectCsrngEntropy->Idle | 211 | Covered | T17,T12,T30 |
| SWPortMode->Error | 188 | Covered | T16,T18,T64 |
| SWPortMode->Idle | 211 | Covered | T4,T6,T59 |
| SWPortMode->RejectCsrngEntropy | 188 | Covered | T17,T109,T67 |
Branch Coverage for Module : edn_main_sm
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| Branches | 42 | 41 | 97.62 | |
| IF | 42 | 2 | 2 | 100.00 |
| CASE | 62 | 35 | 35 | 100.00 |
| IF | 186 | 5 | 4 | 80.00 |
42 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Idle) -1- ==> ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
62 unique case (state_q) -1- 63 Idle: begin 64 if (boot_req_mode_i && edn_enable_i) begin -2- 65 state_d = BootLoadIns; ==> 66 end else if (auto_req_mode_i && edn_enable_i) begin -3- 67 accept_sw_cmds_pulse_o = 1'b1; ==> 68 sw_cmd_mode_o = 1'b1; 69 state_d = AutoLoadIns; 70 end else if (edn_enable_i) begin -4- 71 main_sm_done_pulse_o = 1'b1; ==> 72 accept_sw_cmds_pulse_o = 1'b1; 73 sw_cmd_mode_o = 1'b1; 74 state_d = SWPortMode; 75 end MISSING_ELSE ==> 76 end 77 BootLoadIns: begin 78 boot_wr_ins_cmd_o = 1'b1; ==> 79 boot_send_ins_cmd_o = 1'b1; 80 state_d = BootInsAckWait; 81 end 82 BootInsAckWait: begin 83 boot_send_ins_cmd_o = 1'b1; 84 if (csrng_cmd_ack_i) begin -5- 85 state_d = BootLoadGen; ==> 86 end MISSING_ELSE ==> 87 end 88 BootLoadGen: begin 89 boot_wr_gen_cmd_o = 1'b1; ==> 90 state_d = BootGenAckWait; 91 end 92 BootGenAckWait: begin 93 if (csrng_cmd_ack_i) begin -6- 94 state_d = BootPulse; ==> 95 end MISSING_ELSE ==> 96 end 97 BootPulse: begin 98 state_d = BootDone; ==> 99 end 100 BootDone: begin 101 if (!boot_req_mode_i) begin -7- 102 state_d = BootLoadUni; ==> 103 end MISSING_ELSE ==> 104 end 105 BootLoadUni: begin 106 boot_wr_uni_cmd_o = 1'b1; ==> 107 state_d = BootUniAckWait; 108 end 109 BootUniAckWait: begin 110 if (csrng_cmd_ack_i) begin -8- 111 main_sm_done_pulse_o = 1'b1; ==> 112 state_d = Idle; 113 end MISSING_ELSE ==> 114 end 115 //----------------------------------- 116 AutoLoadIns: begin 117 sw_cmd_mode_o = 1'b1; 118 if (sw_cmd_req_load_i) begin -9- 119 state_d = AutoFirstAckWait; ==> 120 end MISSING_ELSE ==> 121 end 122 AutoFirstAckWait: begin 123 sw_cmd_mode_o = 1'b1; 124 if (csrng_cmd_ack_i) begin -10- 125 state_d = AutoDispatch; ==> 126 end MISSING_ELSE ==> 127 end 128 AutoAckWait: begin 129 auto_req_mode_busy_o = 1'b1; 130 if (csrng_cmd_ack_i) begin -11- 131 state_d = AutoDispatch; ==> 132 end MISSING_ELSE ==> 133 end 134 AutoDispatch: begin 135 auto_req_mode_busy_o = 1'b1; 136 if (!auto_req_mode_i) begin -12- 137 main_sm_done_pulse_o = 1'b1; ==> 138 state_d = Idle; 139 end else begin 140 if (max_reqs_cnt_zero_i) begin -13- 141 state_d = AutoCaptReseedCnt; ==> 142 end else begin 143 state_d = AutoCaptGenCnt; ==> 144 end 145 end 146 end 147 AutoCaptGenCnt: begin 148 auto_req_mode_busy_o = 1'b1; ==> 149 capt_gencmd_fifo_cnt_o = 1'b1; 150 state_d = AutoSendGenCmd; 151 end 152 AutoSendGenCmd: begin 153 auto_req_mode_busy_o = 1'b1; 154 send_gencmd_o = 1'b1; 155 if (cmd_sent_i) begin -14- 156 state_d = AutoAckWait; ==> 157 end MISSING_ELSE ==> 158 end 159 AutoCaptReseedCnt: begin 160 auto_req_mode_busy_o = 1'b1; ==> 161 capt_rescmd_fifo_cnt_o = 1'b1; 162 state_d = AutoSendReseedCmd; 163 end 164 AutoSendReseedCmd: begin 165 auto_req_mode_busy_o = 1'b1; 166 send_rescmd_o = 1'b1; 167 if (cmd_sent_i) begin -15- 168 state_d = AutoAckWait; ==> 169 end MISSING_ELSE ==> 170 end 171 SWPortMode: begin 172 sw_cmd_mode_o = 1'b1; ==> 173 end 174 RejectCsrngEntropy: begin 175 reject_csrng_entropy_o = 1'b1; ==> 176 end 177 Error: begin 178 main_sm_err_o = 1'b1; ==> 179 end 180 default: begin 181 state_d = Error; ==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | -14- | -15- | Status | Tests |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Idle | 1 | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T17,T5,T24 |
| Idle | 0 | 1 | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T17,T10,T11 |
| Idle | 0 | 0 | 1 | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| Idle | 0 | 0 | 0 | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| BootLoadIns | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T17,T5,T24 |
| BootInsAckWait | - | - | - | 1 | - | - | - | - | - | - | - | - | - | - | Covered | T17,T5,T24 |
| BootInsAckWait | - | - | - | 0 | - | - | - | - | - | - | - | - | - | - | Covered | T17,T5,T24 |
| BootLoadGen | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T17,T5,T24 |
| BootGenAckWait | - | - | - | - | 1 | - | - | - | - | - | - | - | - | - | Covered | T17,T5,T24 |
| BootGenAckWait | - | - | - | - | 0 | - | - | - | - | - | - | - | - | - | Covered | T17,T5,T24 |
| BootPulse | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T17,T5,T24 |
| BootDone | - | - | - | - | - | 1 | - | - | - | - | - | - | - | - | Covered | T17,T12,T75 |
| BootDone | - | - | - | - | - | 0 | - | - | - | - | - | - | - | - | Covered | T5,T24,T29 |
| BootLoadUni | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T17,T12,T75 |
| BootUniAckWait | - | - | - | - | - | - | 1 | - | - | - | - | - | - | - | Covered | T40,T109,T53 |
| BootUniAckWait | - | - | - | - | - | - | 0 | - | - | - | - | - | - | - | Covered | T12,T75,T30 |
| AutoLoadIns | - | - | - | - | - | - | - | 1 | - | - | - | - | - | - | Covered | T10,T11,T12 |
| AutoLoadIns | - | - | - | - | - | - | - | 0 | - | - | - | - | - | - | Covered | T17,T10,T11 |
| AutoFirstAckWait | - | - | - | - | - | - | - | - | 1 | - | - | - | - | - | Covered | T10,T11,T12 |
| AutoFirstAckWait | - | - | - | - | - | - | - | - | 0 | - | - | - | - | - | Covered | T10,T11,T12 |
| AutoAckWait | - | - | - | - | - | - | - | - | - | 1 | - | - | - | - | Covered | T10,T11,T7 |
| AutoAckWait | - | - | - | - | - | - | - | - | - | 0 | - | - | - | - | Covered | T10,T11,T7 |
| AutoDispatch | - | - | - | - | - | - | - | - | - | - | 1 | - | - | - | Covered | T11,T13,T43 |
| AutoDispatch | - | - | - | - | - | - | - | - | - | - | 0 | 1 | - | - | Covered | T10,T11,T7 |
| AutoDispatch | - | - | - | - | - | - | - | - | - | - | 0 | 0 | - | - | Covered | T10,T11,T12 |
| AutoCaptGenCnt | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T10,T11,T12 |
| AutoSendGenCmd | - | - | - | - | - | - | - | - | - | - | - | - | 1 | - | Covered | T10,T11,T12 |
| AutoSendGenCmd | - | - | - | - | - | - | - | - | - | - | - | - | 0 | - | Covered | T10,T11,T12 |
| AutoCaptReseedCnt | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T10,T11,T7 |
| AutoSendReseedCmd | - | - | - | - | - | - | - | - | - | - | - | - | - | 1 | Covered | T10,T11,T21 |
| AutoSendReseedCmd | - | - | - | - | - | - | - | - | - | - | - | - | - | 0 | Covered | T10,T11,T21 |
| SWPortMode | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T1,T2,T3 |
| RejectCsrngEntropy | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T17,T12,T30 |
| Error | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T5,T7,T16 |
| default | - | - | - | - | - | - | - | - | - | - | - | - | - | - | Covered | T74,T75,T18 |
186 if (local_escalate_i || csrng_ack_err_i) begin -1- 187 // Either move into RejectCsrngEntropy or Error but don't move out of Error as it's terminal. 188 state_d = local_escalate_i ? Error : -2- ==> 189 state_q == Error ? Error : RejectCsrngEntropy; -3- ==> ==> 190 // Tie off outputs, except for main_sm_err_o, auto_req_mode_busy_o, boot_send_ins_cmd_o, 191 // sw_cmd_mode_o and reject_csrng_entropy_o. 192 boot_wr_ins_cmd_o = 1'b0; 193 boot_wr_gen_cmd_o = 1'b0; 194 boot_wr_uni_cmd_o = 1'b0; 195 accept_sw_cmds_pulse_o = 1'b0; 196 capt_gencmd_fifo_cnt_o = 1'b0; 197 send_gencmd_o = 1'b0; 198 capt_rescmd_fifo_cnt_o = 1'b0; 199 send_rescmd_o = 1'b0; 200 main_sm_done_pulse_o = 1'b0; 201 end else if (!edn_enable_i && state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, -4- 202 BootGenAckWait, BootLoadUni, BootUniAckWait, 203 BootPulse, BootDone, 204 AutoLoadIns, AutoFirstAckWait, AutoAckWait, 205 AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, 206 AutoCaptReseedCnt, AutoSendReseedCmd, 207 SWPortMode, RejectCsrngEntropy 208 }) begin 209 // Only go to idle if the state is legal and not Idle or Error. 210 // Even when disabled, illegal states must result in a transition to Error. 211 state_d = Idle; ==> 212 // Tie off outputs, except for main_sm_err_o. 213 boot_wr_ins_cmd_o = 1'b0; 214 boot_send_ins_cmd_o = 1'b0; 215 boot_wr_gen_cmd_o = 1'b0; 216 boot_wr_uni_cmd_o = 1'b0; 217 accept_sw_cmds_pulse_o = 1'b0; 218 auto_req_mode_busy_o = 1'b0; 219 capt_gencmd_fifo_cnt_o = 1'b0; 220 send_gencmd_o = 1'b0; 221 capt_rescmd_fifo_cnt_o = 1'b0; 222 send_rescmd_o = 1'b0; 223 sw_cmd_mode_o = 1'b0; 224 reject_csrng_entropy_o = 1'b0; 225 main_sm_done_pulse_o = 1'b1; 226 end MISSING_ELSE ==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
|---|---|---|---|---|---|
| 1 | 1 | - | - | Covered | T5,T7,T16 |
| 1 | 0 | 1 | - | Not Covered | |
| 1 | 0 | 0 | - | Covered | T17,T12,T30 |
| 0 | - | - | 1 | Covered | T17,T4,T5 |
| 0 | - | - | 0 | Covered | T1,T2,T3 |
Assert Coverage for Module : edn_main_sm
| Total | Attempted | Percent | Succeeded/Matched | Percent | |
|---|---|---|---|---|---|
| Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
| Cover properties | 0 | 0 | 0 | ||
| Cover sequences | 0 | 0 | 0 | ||
| Total | 3 | 3 | 100.00 | 3 | 100.00 |
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
| ErrorStStable_A | 12472250 | 161129 | 0 | 0 |
| FpvSecCmErrorStEscalate_A | 12472250 | 162433 | 0 | 0 |
| u_state_regs_A | 12433103 | 12236372 | 0 | 0 |
ErrorStStable_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 12472250 | 161129 | 0 | 0 |
| T5 | 652 | 352 | 0 | 0 |
| T6 | 10597 | 0 | 0 | 0 |
| T7 | 0 | 602 | 0 | 0 |
| T8 | 0 | 1174 | 0 | 0 |
| T10 | 2468 | 0 | 0 | 0 |
| T11 | 4162 | 0 | 0 | 0 |
| T12 | 2180 | 0 | 0 | 0 |
| T16 | 0 | 738 | 0 | 0 |
| T18 | 0 | 14975 | 0 | 0 |
| T19 | 0 | 14816 | 0 | 0 |
| T24 | 1402 | 0 | 0 | 0 |
| T25 | 1337 | 0 | 0 | 0 |
| T26 | 1206 | 0 | 0 | 0 |
| T27 | 827 | 0 | 0 | 0 |
| T29 | 776 | 0 | 0 | 0 |
| T64 | 0 | 186 | 0 | 0 |
| T66 | 0 | 582 | 0 | 0 |
| T74 | 0 | 1058 | 0 | 0 |
| T75 | 0 | 350 | 0 | 0 |
FpvSecCmErrorStEscalate_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 12472250 | 162433 | 0 | 0 |
| T5 | 652 | 353 | 0 | 0 |
| T6 | 10597 | 0 | 0 | 0 |
| T7 | 0 | 603 | 0 | 0 |
| T8 | 0 | 1175 | 0 | 0 |
| T10 | 2468 | 0 | 0 | 0 |
| T11 | 4162 | 0 | 0 | 0 |
| T12 | 2180 | 0 | 0 | 0 |
| T16 | 0 | 739 | 0 | 0 |
| T18 | 0 | 15235 | 0 | 0 |
| T19 | 0 | 15076 | 0 | 0 |
| T24 | 1402 | 0 | 0 | 0 |
| T25 | 1337 | 0 | 0 | 0 |
| T26 | 1206 | 0 | 0 | 0 |
| T27 | 827 | 0 | 0 | 0 |
| T29 | 776 | 0 | 0 | 0 |
| T64 | 0 | 187 | 0 | 0 |
| T66 | 0 | 583 | 0 | 0 |
| T74 | 0 | 1059 | 0 | 0 |
| T75 | 0 | 351 | 0 | 0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 12433103 | 12236372 | 0 | 0 |
| T1 | 1872 | 1815 | 0 | 0 |
| T2 | 1509 | 1421 | 0 | 0 |
| T3 | 2534 | 2469 | 0 | 0 |
| T4 | 1675 | 1530 | 0 | 0 |
| T5 | 529 | 404 | 0 | 0 |
| T6 | 10597 | 10289 | 0 | 0 |
| T17 | 2262 | 2203 | 0 | 0 |
| T24 | 1402 | 1319 | 0 | 0 |
| T25 | 1337 | 1238 | 0 | 0 |
| T26 | 1206 | 1107 | 0 | 0 |