Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.31	100.00	91.03			98.23	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T1 T2 T3 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T1 T2 T3 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
80         1/1                    state_d = AckPls;
           Tests:       T1 T2 T3 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T1 T2 T3 
85         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T7 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T7 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T7 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T7 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T7 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T17 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T17 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T17 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T17 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T4,T5

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T7,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T99,T83,T94
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T10,T115,T90
DataWait->Error	99	Covered	T75,T66,T9
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T59,T65,T48
EndPointClear->Error	99	Covered	T18,T19,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T5,T7,T16

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T5,T7,T16
default	-	-	-	-	Covered	T18,T64,T19

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T16
0	1	Covered	T17,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	87305750	1140703	0	0
FpvSecCmErrorStEscalate_A	87305750	1149831	0	0
u_state_regs_A	87266603	85889486	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87305750	1140703	0	0
T5	4564	2464	0	0
T6	74179	0	0	0
T7	0	4214	0	0
T8	0	8218	0	0
T10	17276	0	0	0
T11	29134	0	0	0
T12	15260	0	0	0
T16	0	5166	0	0
T18	0	104825	0	0
T19	0	103712	0	0
T24	9814	0	0	0
T25	9359	0	0	0
T26	8442	0	0	0
T27	5789	0	0	0
T29	5432	0	0	0
T64	0	1252	0	0
T66	0	4424	0	0
T74	0	7756	0	0
T75	0	2800	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87305750	1149831	0	0
T5	4564	2471	0	0
T6	74179	0	0	0
T7	0	4221	0	0
T8	0	8225	0	0
T10	17276	0	0	0
T11	29134	0	0	0
T12	15260	0	0	0
T16	0	5173	0	0
T18	0	106645	0	0
T19	0	105532	0	0
T24	9814	0	0	0
T25	9359	0	0	0
T26	8442	0	0	0
T27	5789	0	0	0
T29	5432	0	0	0
T64	0	1259	0	0
T66	0	4431	0	0
T74	0	7763	0	0
T75	0	2807	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87266603	85889486	0	0
T1	13104	12705	0	0
T2	10563	9947	0	0
T3	17738	17283	0	0
T4	11905	10890	0	0
T5	4441	3566	0	0
T6	74179	72023	0	0
T17	15834	15421	0	0
T24	9814	9233	0	0
T25	9359	8666	0	0
T26	8442	7749	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T1 T2 T3 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T1 T2 T3 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T1 T2 T3 
80         1/1                    state_d = AckPls;
           Tests:       T1 T2 T3 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T1 T2 T3 
85         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T7 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T7 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T7 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T7 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T7 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T17 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T17 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T17 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T17 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T3
DataWait	75	Covered	T1,T2,T3
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T7,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T3
DataWait->AckPls	80	Covered	T1,T2,T3
DataWait->Disabled	107	Covered	T115,T189,T214
DataWait->Error	99	Covered	T75,T177,T215
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T59,T65,T48
EndPointClear->Error	99	Covered	T18,T19,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T3
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T5,T7,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T5,T7,T16
default	-	-	-	-	Covered	T18,T64,T19

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T16
0	1	Covered	T17,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12472250	161329	0	0
FpvSecCmErrorStEscalate_A	12472250	162633	0	0
u_state_regs_A	12433103	12236372	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	161329	0	0
T5	652	352	0	0
T6	10597	0	0	0
T7	0	602	0	0
T8	0	1174	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	738	0	0
T18	0	14975	0	0
T19	0	14816	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	136	0	0
T66	0	632	0	0
T74	0	1108	0	0
T75	0	400	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	162633	0	0
T5	652	353	0	0
T6	10597	0	0	0
T7	0	603	0	0
T8	0	1175	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	739	0	0
T18	0	15235	0	0
T19	0	15076	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	137	0	0
T66	0	633	0	0
T74	0	1109	0	0
T75	0	401	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12433103	12236372	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1675	1530	0	0
T5	529	404	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T10 T22 T40 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T10 T22 T40 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T10 T22 T40 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T10 T22 T40 
80         1/1                    state_d = AckPls;
           Tests:       T10 T22 T40 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T10 T22 T40 
85         1/1                  state_d = Idle;
           Tests:       T10 T22 T40 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T7 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T7 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T7 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T7 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T7 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T17 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T17 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T17 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T17 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T22,T40
DataWait	75	Covered	T10,T22,T40
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T7,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T22,T40
DataWait->AckPls	80	Covered	T10,T22,T40
DataWait->Disabled	107	Covered	T10,T145,T216
DataWait->Error	99	Covered	T66,T9,T217
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T59,T65,T48
EndPointClear->Error	99	Covered	T18,T19,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T10,T22,T40
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T5,T7,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T22,T40
Idle	-	1	0	-	Covered	T10,T22,T40
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T22,T40
DataWait	-	-	-	0	Covered	T10,T22,T40
AckPls	-	-	-	-	Covered	T10,T22,T40
Error	-	-	-	-	Covered	T5,T7,T16
default	-	-	-	-	Covered	T18,T19,T20

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T16
0	1	Covered	T17,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12472250	163229	0	0
FpvSecCmErrorStEscalate_A	12472250	164533	0	0
u_state_regs_A	12472250	12275519	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	163229	0	0
T5	652	352	0	0
T6	10597	0	0	0
T7	0	602	0	0
T8	0	1174	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	738	0	0
T18	0	14975	0	0
T19	0	14816	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	186	0	0
T66	0	632	0	0
T74	0	1108	0	0
T75	0	400	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	164533	0	0
T5	652	353	0	0
T6	10597	0	0	0
T7	0	603	0	0
T8	0	1175	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	739	0	0
T18	0	15235	0	0
T19	0	15076	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	187	0	0
T66	0	633	0	0
T74	0	1109	0	0
T75	0	401	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T5 T29 T30 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T29 T30 T13 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T5 T29 T30 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T29 T30 T13 
80         1/1                    state_d = AckPls;
           Tests:       T29 T30 T13 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T29 T30 T13 
85         1/1                  state_d = Idle;
           Tests:       T29 T30 T13 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T7 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T7 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T7 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T7 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T7 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T17 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T17 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T17 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T17 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T29,T30,T13
DataWait	75	Covered	T29,T30,T13
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T7,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T29,T30,T13
DataWait->AckPls	80	Covered	T29,T30,T13
DataWait->Disabled	107	Covered	T90,T144,T218
DataWait->Error	99	Covered	T219,T143,T165
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T59,T65,T48
EndPointClear->Error	99	Covered	T18,T19,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T29,T30,T13
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T5,T7,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T29,T30,T13
Idle	-	1	0	-	Covered	T5,T29,T30
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T29,T30,T13
DataWait	-	-	-	0	Covered	T29,T30,T13
AckPls	-	-	-	-	Covered	T29,T30,T13
Error	-	-	-	-	Covered	T5,T7,T16
default	-	-	-	-	Covered	T18,T19,T20

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T16
0	1	Covered	T17,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12472250	163229	0	0
FpvSecCmErrorStEscalate_A	12472250	164533	0	0
u_state_regs_A	12472250	12275519	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	163229	0	0
T5	652	352	0	0
T6	10597	0	0	0
T7	0	602	0	0
T8	0	1174	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	738	0	0
T18	0	14975	0	0
T19	0	14816	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	186	0	0
T66	0	632	0	0
T74	0	1108	0	0
T75	0	400	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	164533	0	0
T5	652	353	0	0
T6	10597	0	0	0
T7	0	603	0	0
T8	0	1175	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	739	0	0
T18	0	15235	0	0
T19	0	15076	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	187	0	0
T66	0	633	0	0
T74	0	1109	0	0
T75	0	401	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T13 T43 T47 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T13 T43 T47 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T13 T43 T47 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T13 T43 T47 
80         1/1                    state_d = AckPls;
           Tests:       T13 T43 T47 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T13 T43 T47 
85         1/1                  state_d = Idle;
           Tests:       T13 T43 T47 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T7 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T7 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T7 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T7 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T7 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T17 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T17 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T17 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T17 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T13,T43,T47
DataWait	75	Covered	T13,T43,T47
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T7,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T83,T220
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T13,T43,T47
DataWait->AckPls	80	Covered	T13,T43,T47
DataWait->Disabled	107	Covered	T221,T222,T223
DataWait->Error	99	Covered	T224,T181,T142
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T59,T65,T48
EndPointClear->Error	99	Covered	T18,T19,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T13,T43,T47
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T5,T7,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T13,T43,T47
Idle	-	1	0	-	Covered	T13,T43,T47
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T13,T43,T47
DataWait	-	-	-	0	Covered	T13,T43,T47
AckPls	-	-	-	-	Covered	T13,T43,T47
Error	-	-	-	-	Covered	T5,T7,T16
default	-	-	-	-	Covered	T18,T19,T20

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T16
0	1	Covered	T17,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12472250	163229	0	0
FpvSecCmErrorStEscalate_A	12472250	164533	0	0
u_state_regs_A	12472250	12275519	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	163229	0	0
T5	652	352	0	0
T6	10597	0	0	0
T7	0	602	0	0
T8	0	1174	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	738	0	0
T18	0	14975	0	0
T19	0	14816	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	186	0	0
T66	0	632	0	0
T74	0	1108	0	0
T75	0	400	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	164533	0	0
T5	652	353	0	0
T6	10597	0	0	0
T7	0	603	0	0
T8	0	1175	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	739	0	0
T18	0	15235	0	0
T19	0	15076	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	187	0	0
T66	0	633	0	0
T74	0	1109	0	0
T75	0	401	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T24 T13 T23 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T24 T13 T23 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T24 T13 T23 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T24 T13 T23 
80         1/1                    state_d = AckPls;
           Tests:       T24 T13 T23 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T24 T13 T23 
85         1/1                  state_d = Idle;
           Tests:       T24 T13 T23 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T7 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T7 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T7 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T7 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T7 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T17 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T17 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T17 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T17 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24,T13,T23
DataWait	75	Covered	T24,T13,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T7,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T94
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24,T13,T23
DataWait->AckPls	80	Covered	T24,T13,T23
DataWait->Disabled	107	Covered	T24,T225
DataWait->Error	99	Covered	T176,T184,T158
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T59,T65,T48
EndPointClear->Error	99	Covered	T18,T19,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T24,T13,T23
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T5,T7,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T24,T13,T23
Idle	-	1	0	-	Covered	T24,T13,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T24,T13,T23
DataWait	-	-	-	0	Covered	T24,T13,T23
AckPls	-	-	-	-	Covered	T24,T13,T23
Error	-	-	-	-	Covered	T5,T7,T16
default	-	-	-	-	Covered	T18,T19,T20

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T16
0	1	Covered	T17,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12472250	163229	0	0
FpvSecCmErrorStEscalate_A	12472250	164533	0	0
u_state_regs_A	12472250	12275519	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	163229	0	0
T5	652	352	0	0
T6	10597	0	0	0
T7	0	602	0	0
T8	0	1174	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	738	0	0
T18	0	14975	0	0
T19	0	14816	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	186	0	0
T66	0	632	0	0
T74	0	1108	0	0
T75	0	400	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	164533	0	0
T5	652	353	0	0
T6	10597	0	0	0
T7	0	603	0	0
T8	0	1175	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	739	0	0
T18	0	15235	0	0
T19	0	15076	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	187	0	0
T66	0	633	0	0
T74	0	1109	0	0
T75	0	401	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T10 T41 T8 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T10 T41 T13 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T10 T41 T8 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T10 T41 T8 
80         1/1                    state_d = AckPls;
           Tests:       T10 T41 T13 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T10 T41 T13 
85         1/1                  state_d = Idle;
           Tests:       T10 T41 T13 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T7 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T7 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T7 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T7 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T7 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T17 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T17 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T17 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T17 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T10,T41,T13
DataWait	75	Covered	T10,T41,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T7,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T99
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T10,T41,T13
DataWait->AckPls	80	Covered	T10,T41,T13
DataWait->Disabled	107	Covered	T98,T101,T226
DataWait->Error	99	Covered	T8,T174,T227
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T59,T65,T48
EndPointClear->Error	99	Covered	T18,T19,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T10,T41,T8
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T5,T7,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T41,T13
Idle	-	1	0	-	Covered	T10,T41,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T41,T13
DataWait	-	-	-	0	Covered	T10,T41,T8
AckPls	-	-	-	-	Covered	T10,T41,T13
Error	-	-	-	-	Covered	T5,T7,T16
default	-	-	-	-	Covered	T18,T19,T20

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T16
0	1	Covered	T17,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12472250	163229	0	0
FpvSecCmErrorStEscalate_A	12472250	164533	0	0
u_state_regs_A	12472250	12275519	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	163229	0	0
T5	652	352	0	0
T6	10597	0	0	0
T7	0	602	0	0
T8	0	1174	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	738	0	0
T18	0	14975	0	0
T19	0	14816	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	186	0	0
T66	0	632	0	0
T74	0	1108	0	0
T75	0	400	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	164533	0	0
T5	652	353	0	0
T6	10597	0	0	0
T7	0	603	0	0
T8	0	1175	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	739	0	0
T18	0	15235	0	0
T19	0	15076	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	187	0	0
T66	0	633	0	0
T74	0	1109	0	0
T75	0	401	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

51                      
52         3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled):
52.1                    `ifdef SIMULATION                                   
52.2                        prim_sparse_fsm_flop #(                           
52.3                          .StateEnumT(state_e),                            
52.4                          .Width($bits(state_e)),                          
52.5                          .ResetValue($bits(state_e)'(Disabled)),          
52.6                          .EnableAlertTriggerSVA(1), 
52.7                          .CustomForceName("state_q")          
52.8                        ) u_state_regs (                                        
52.9                          .clk_i   ( clk_i   ),                           
52.10                         .rst_ni  ( rst_ni ),                           
52.11                         .state_i ( state_d     ),                           
52.12                         .state_o (         )                            
52.13                       );                                                
52.14                       always_ff @(posedge clk_i or negedge rst_ni) begin 
52.15      1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
52.16      1/1                state_q <= Disabled;                                
           Tests:       T1 T2 T3 
52.17                       end else begin                                    
52.18      1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
52.19                       end                                               
52.20                     end  
52.21                       u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
52.22                       else begin                                                                           
52.23                         `ifdef UVM                                                                               
52.24                     uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
52.25                                               "../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv", 52, "", 1);                                
52.26                   `else                                                                                    
52.27                     $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
52.28                            `PRIM_STRINGIFY(u_state_regs_A));                                                       
52.29                   `endif                                                              
52.30                       end 
52.31                     `else                                               
52.32                       prim_sparse_fsm_flop #(                           
52.33                         .StateEnumT(state_e),                            
52.34                         .Width($bits(state_e)),                          
52.35                         .ResetValue($bits(state_e)'(Disabled)),          
52.36                         .EnableAlertTriggerSVA(1)  
52.37                       ) u_state_regs (                                        
52.38                         .clk_i   ( `PRIM_FLOP_CLK   ),                           
52.39                         .rst_ni  ( `PRIM_FLOP_RST ),                           
52.40                         .state_i ( state_d     ),                           
52.41                         .state_o ( state_q     )                            
52.42                       );                                                
52.43                     `endif53                      
54                        always_comb begin
55         1/1              state_d      = state_q;
           Tests:       T1 T2 T3 
56         1/1              ack_o        = 1'b0;
           Tests:       T1 T2 T3 
57         1/1              fifo_clr_o   = 1'b0;
           Tests:       T1 T2 T3 
58         1/1              fifo_pop_o   = 1'b0;
           Tests:       T1 T2 T3 
59         1/1              ack_sm_err_o = 1'b0;
           Tests:       T1 T2 T3 
60         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
61                            Disabled: begin
62         1/1                  if (enable_i) begin
           Tests:       T1 T2 T3 
63         1/1                    state_d = EndPointClear;
           Tests:       T1 T2 T3 
64         1/1                    fifo_clr_o = 1'b1;
           Tests:       T1 T2 T3 
65                              end
                        MISSING_ELSE
66                            end
67                            EndPointClear: begin
68         1/1                  state_d = Idle;
           Tests:       T1 T2 T3 
69                            end
70                            Idle: begin
71         1/1                  if (req_i) begin
           Tests:       T1 T2 T3 
72         1/1                    if (fifo_not_empty_i) begin
           Tests:       T7 T21 T42 
73         1/1                      fifo_pop_o = 1'b1;
           Tests:       T7 T21 T42 
74                                end
                        MISSING_ELSE
75         1/1                    state_d = DataWait;
           Tests:       T7 T21 T42 
76                              end
                        MISSING_ELSE
77                            end
78                            DataWait: begin
79         1/1                  if (fifo_not_empty_i) begin
           Tests:       T7 T21 T42 
80         1/1                    state_d = AckPls;
           Tests:       T7 T21 T42 
81                              end
                        MISSING_ELSE
82                            end
83                            AckPls: begin
84         1/1                  ack_o = 1'b1;
           Tests:       T7 T21 T42 
85         1/1                  state_d = Idle;
           Tests:       T7 T21 T42 
86                            end
87                            Error: begin
88         1/1                  ack_sm_err_o = 1'b1;
           Tests:       T5 T7 T16 
89                            end
90                            default: begin
91                              ack_sm_err_o = 1'b1;
92                              state_d = Error;
93                            end
94                          endcase // unique case (state_q)
95                      
96                          // If local escalation is seen, transition directly to
97                          // error state.
98         1/1              if (local_escalate_i) begin
           Tests:       T1 T2 T3 
99         1/1                state_d = Error;
           Tests:       T5 T7 T16 
100                           // Tie off outputs, except for ack_sm_err_o.
101        1/1                ack_o      = 1'b0;
           Tests:       T5 T7 T16 
102        1/1                fifo_clr_o = 1'b0;
           Tests:       T5 T7 T16 
103        1/1                fifo_pop_o = 1'b0;
           Tests:       T5 T7 T16 
104        1/1              end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
           Tests:       T1 T2 T3 
105                           // Only disable if state is legal and not Disabled or Error.
106                           // Even when disabled, illegal states must result in a transition to Error.
107        1/1                state_d = Disabled;
           Tests:       T17 T4 T5 
108                           // Tie off all outputs, except for ack_sm_err_o.
109        1/1                ack_o        = 1'b0;
           Tests:       T17 T4 T5 
110        1/1                fifo_pop_o   = 1'b0;
           Tests:       T17 T4 T5 
111        1/1                fifo_clr_o   = 1'b0;
           Tests:       T17 T4 T5 
112                         end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T4,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T7,T21,T42
DataWait	75	Covered	T7,T21,T42
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T5,T7,T16
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T106
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T7,T21,T42
DataWait->AckPls	80	Covered	T7,T21,T42
DataWait->Disabled	107	Covered	T84,T169
DataWait->Error	99	Covered	T228,T229
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T18,T19,T20
EndPointClear->Disabled	107	Covered	T59,T65,T48
EndPointClear->Error	99	Covered	T18,T19,T20
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T7,T21,T42
Idle->Disabled	107	Covered	T17,T4,T5
Idle->Error	99	Covered	T5,T7,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

52           `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, Disabled)
             -1-                                                                        
             ==>                                                                        
             ==>                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

60             unique case (state_q)
                      -1-  
61               Disabled: begin
62                 if (enable_i) begin
                   -2-  
63                   state_d = EndPointClear;
                     ==>
64                   fifo_clr_o = 1'b1;
65                 end
                   MISSING_ELSE
                   ==>
66               end
67               EndPointClear: begin
68                 state_d = Idle;
                   ==>
69               end
70               Idle: begin
71                 if (req_i) begin
                   -3-  
72                   if (fifo_not_empty_i) begin
                     -4-     
73                     fifo_pop_o = 1'b1;
                       ==>
74                   end
                     MISSING_ELSE
                     ==>
75                   state_d = DataWait;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78               DataWait: begin
79                 if (fifo_not_empty_i) begin
                   -5-     
80                   state_d = AckPls;
                     ==>
81                 end
                   MISSING_ELSE
                   ==>
82               end
83               AckPls: begin
84                 ack_o = 1'b1;
                   ==>
85                 state_d = Idle;
86               end
87               Error: begin
88                 ack_sm_err_o = 1'b1;
                   ==>
89               end
90               default: begin
91                 ack_sm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T7,T21,T42
Idle	-	1	0	-	Covered	T7,T21,T42
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T7,T21,T42
DataWait	-	-	-	0	Covered	T7,T21,T42
AckPls	-	-	-	-	Covered	T7,T21,T42
Error	-	-	-	-	Covered	T5,T7,T16
default	-	-	-	-	Covered	T18,T19,T20

98             if (local_escalate_i) begin
               -1-  
99               state_d = Error;
                 ==>
100              // Tie off outputs, except for ack_sm_err_o.
101              ack_o      = 1'b0;
102              fifo_clr_o = 1'b0;
103              fifo_pop_o = 1'b0;
104            end else if (!enable_i && state_q inside {EndPointClear, Idle, DataWait, AckPls}) begin
                        -2-  
105              // Only disable if state is legal and not Disabled or Error.
106              // Even when disabled, illegal states must result in a transition to Error.
107              state_d = Disabled;
                 ==>
108              // Tie off all outputs, except for ack_sm_err_o.
109              ack_o        = 1'b0;
110              fifo_pop_o   = 1'b0;
111              fifo_clr_o   = 1'b0;
112            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T16
0	1	Covered	T17,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	12472250	163229	0	0
FpvSecCmErrorStEscalate_A	12472250	164533	0	0
u_state_regs_A	12472250	12275519	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	163229	0	0
T5	652	352	0	0
T6	10597	0	0	0
T7	0	602	0	0
T8	0	1174	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	738	0	0
T18	0	14975	0	0
T19	0	14816	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	186	0	0
T66	0	632	0	0
T74	0	1108	0	0
T75	0	400	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	164533	0	0
T5	652	353	0	0
T6	10597	0	0	0
T7	0	603	0	0
T8	0	1175	0	0
T10	2468	0	0	0
T11	4162	0	0	0
T12	2180	0	0	0
T16	0	739	0	0
T18	0	15235	0	0
T19	0	15076	0	0
T24	1402	0	0	0
T25	1337	0	0	0
T26	1206	0	0	0
T27	827	0	0	0
T29	776	0	0	0
T64	0	187	0	0
T66	0	633	0	0
T74	0	1109	0	0
T75	0	401	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12472250	12275519	0	0
T1	1872	1815	0	0
T2	1509	1421	0	0
T3	2534	2469	0	0
T4	1705	1560	0	0
T5	652	527	0	0
T6	10597	10289	0	0
T17	2262	2203	0	0
T24	1402	1319	0	0
T25	1337	1238	0	0
T26	1206	1107	0	0