Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T17 T5 T10
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T17 T5 T10
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T17 T5 T10
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
|---|
| Conditions | 14 | 11 | 78.57 |
| Logical | 14 | 11 | 78.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T10,T11 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T5,T10 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T31,T32,T33 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T17,T5,T10 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T34,T35,T36 |
| 1 | 0 | 1 | Covered | T17,T5,T10 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T10,T11,T12 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T5,T10 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
24119598 |
1028765 |
0 |
0 |
| T4 |
724 |
0 |
0 |
0 |
| T5 |
198 |
0 |
0 |
0 |
| T6 |
21194 |
0 |
0 |
0 |
| T7 |
0 |
83 |
0 |
0 |
| T10 |
4936 |
2272 |
0 |
0 |
| T11 |
8324 |
5721 |
0 |
0 |
| T12 |
0 |
301 |
0 |
0 |
| T17 |
4524 |
520 |
0 |
0 |
| T21 |
0 |
2479 |
0 |
0 |
| T22 |
0 |
2683 |
0 |
0 |
| T24 |
2804 |
0 |
0 |
0 |
| T25 |
2674 |
0 |
0 |
0 |
| T26 |
2412 |
0 |
0 |
0 |
| T27 |
1654 |
0 |
0 |
0 |
| T30 |
0 |
615 |
0 |
0 |
| T55 |
0 |
1992 |
0 |
0 |
| T109 |
0 |
245 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
24944500 |
24551038 |
0 |
0 |
| T1 |
3744 |
3630 |
0 |
0 |
| T2 |
3018 |
2842 |
0 |
0 |
| T3 |
5068 |
4938 |
0 |
0 |
| T4 |
3410 |
3120 |
0 |
0 |
| T5 |
1304 |
1054 |
0 |
0 |
| T6 |
21194 |
20578 |
0 |
0 |
| T17 |
4524 |
4406 |
0 |
0 |
| T24 |
2804 |
2638 |
0 |
0 |
| T25 |
2674 |
2476 |
0 |
0 |
| T26 |
2412 |
2214 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
24944500 |
24551038 |
0 |
0 |
| T1 |
3744 |
3630 |
0 |
0 |
| T2 |
3018 |
2842 |
0 |
0 |
| T3 |
5068 |
4938 |
0 |
0 |
| T4 |
3410 |
3120 |
0 |
0 |
| T5 |
1304 |
1054 |
0 |
0 |
| T6 |
21194 |
20578 |
0 |
0 |
| T17 |
4524 |
4406 |
0 |
0 |
| T24 |
2804 |
2638 |
0 |
0 |
| T25 |
2674 |
2476 |
0 |
0 |
| T26 |
2412 |
2214 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
24944500 |
24551038 |
0 |
0 |
| T1 |
3744 |
3630 |
0 |
0 |
| T2 |
3018 |
2842 |
0 |
0 |
| T3 |
5068 |
4938 |
0 |
0 |
| T4 |
3410 |
3120 |
0 |
0 |
| T5 |
1304 |
1054 |
0 |
0 |
| T6 |
21194 |
20578 |
0 |
0 |
| T17 |
4524 |
4406 |
0 |
0 |
| T24 |
2804 |
2638 |
0 |
0 |
| T25 |
2674 |
2476 |
0 |
0 |
| T26 |
2412 |
2214 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
24478606 |
1122979 |
0 |
0 |
| T4 |
3410 |
0 |
0 |
0 |
| T5 |
1304 |
222 |
0 |
0 |
| T6 |
21194 |
0 |
0 |
0 |
| T7 |
0 |
1074 |
0 |
0 |
| T10 |
4936 |
2272 |
0 |
0 |
| T11 |
8324 |
5721 |
0 |
0 |
| T12 |
0 |
301 |
0 |
0 |
| T17 |
4524 |
520 |
0 |
0 |
| T21 |
0 |
2479 |
0 |
0 |
| T22 |
0 |
2683 |
0 |
0 |
| T24 |
2804 |
0 |
0 |
0 |
| T25 |
2674 |
0 |
0 |
0 |
| T26 |
2412 |
0 |
0 |
0 |
| T27 |
1654 |
0 |
0 |
0 |
| T30 |
0 |
615 |
0 |
0 |
| T75 |
0 |
314 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T17 T5 T10
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T17 T5 T10
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T17 T5 T10
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Total | Covered | Percent |
|---|
| Conditions | 14 | 11 | 78.57 |
| Logical | 14 | 11 | 78.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T10,T8,T18 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T5,T10 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T110 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T17,T5,T10 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T111,T112 |
| 1 | 0 | 1 | Covered | T17,T5,T10 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T10,T11,T7 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T5,T10 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12059799 |
508625 |
0 |
0 |
| T4 |
362 |
0 |
0 |
0 |
| T5 |
99 |
0 |
0 |
0 |
| T6 |
10597 |
0 |
0 |
0 |
| T7 |
0 |
29 |
0 |
0 |
| T10 |
2468 |
1105 |
0 |
0 |
| T11 |
4162 |
2855 |
0 |
0 |
| T12 |
0 |
249 |
0 |
0 |
| T17 |
2262 |
207 |
0 |
0 |
| T21 |
0 |
1155 |
0 |
0 |
| T22 |
0 |
1316 |
0 |
0 |
| T24 |
1402 |
0 |
0 |
0 |
| T25 |
1337 |
0 |
0 |
0 |
| T26 |
1206 |
0 |
0 |
0 |
| T27 |
827 |
0 |
0 |
0 |
| T30 |
0 |
314 |
0 |
0 |
| T55 |
0 |
955 |
0 |
0 |
| T109 |
0 |
109 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12472250 |
12275519 |
0 |
0 |
| T1 |
1872 |
1815 |
0 |
0 |
| T2 |
1509 |
1421 |
0 |
0 |
| T3 |
2534 |
2469 |
0 |
0 |
| T4 |
1705 |
1560 |
0 |
0 |
| T5 |
652 |
527 |
0 |
0 |
| T6 |
10597 |
10289 |
0 |
0 |
| T17 |
2262 |
2203 |
0 |
0 |
| T24 |
1402 |
1319 |
0 |
0 |
| T25 |
1337 |
1238 |
0 |
0 |
| T26 |
1206 |
1107 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12472250 |
12275519 |
0 |
0 |
| T1 |
1872 |
1815 |
0 |
0 |
| T2 |
1509 |
1421 |
0 |
0 |
| T3 |
2534 |
2469 |
0 |
0 |
| T4 |
1705 |
1560 |
0 |
0 |
| T5 |
652 |
527 |
0 |
0 |
| T6 |
10597 |
10289 |
0 |
0 |
| T17 |
2262 |
2203 |
0 |
0 |
| T24 |
1402 |
1319 |
0 |
0 |
| T25 |
1337 |
1238 |
0 |
0 |
| T26 |
1206 |
1107 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12472250 |
12275519 |
0 |
0 |
| T1 |
1872 |
1815 |
0 |
0 |
| T2 |
1509 |
1421 |
0 |
0 |
| T3 |
2534 |
2469 |
0 |
0 |
| T4 |
1705 |
1560 |
0 |
0 |
| T5 |
652 |
527 |
0 |
0 |
| T6 |
10597 |
10289 |
0 |
0 |
| T17 |
2262 |
2203 |
0 |
0 |
| T24 |
1402 |
1319 |
0 |
0 |
| T25 |
1337 |
1238 |
0 |
0 |
| T26 |
1206 |
1107 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12239303 |
555129 |
0 |
0 |
| T4 |
1705 |
0 |
0 |
0 |
| T5 |
652 |
112 |
0 |
0 |
| T6 |
10597 |
0 |
0 |
0 |
| T7 |
0 |
519 |
0 |
0 |
| T10 |
2468 |
1105 |
0 |
0 |
| T11 |
4162 |
2855 |
0 |
0 |
| T12 |
0 |
249 |
0 |
0 |
| T17 |
2262 |
207 |
0 |
0 |
| T21 |
0 |
1155 |
0 |
0 |
| T22 |
0 |
1316 |
0 |
0 |
| T24 |
1402 |
0 |
0 |
0 |
| T25 |
1337 |
0 |
0 |
0 |
| T26 |
1206 |
0 |
0 |
0 |
| T27 |
827 |
0 |
0 |
0 |
| T30 |
0 |
314 |
0 |
0 |
| T75 |
0 |
158 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 14 | 14 | 100.00 |
| ALWAYS | 69 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T17 T5 T10
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T17 T5 T10
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T17 T5 T10
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Total | Covered | Percent |
|---|
| Conditions | 14 | 11 | 78.57 |
| Logical | 14 | 11 | 78.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T17,T10,T11 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T17,T5,T10 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T31,T32,T33 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T17,T5,T10 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T34,T35,T36 |
| 1 | 0 | 1 | Covered | T17,T5,T10 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T10,T11,T12 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
| Branches |
|
5 |
5 |
100.00 |
| IF |
69 |
3 |
3 |
100.00 |
| IF |
123 |
2 |
2 |
100.00 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T17,T5,T10 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Assertion Details
DataKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12059799 |
520140 |
0 |
0 |
| T4 |
362 |
0 |
0 |
0 |
| T5 |
99 |
0 |
0 |
0 |
| T6 |
10597 |
0 |
0 |
0 |
| T7 |
0 |
54 |
0 |
0 |
| T10 |
2468 |
1167 |
0 |
0 |
| T11 |
4162 |
2866 |
0 |
0 |
| T12 |
0 |
52 |
0 |
0 |
| T17 |
2262 |
313 |
0 |
0 |
| T21 |
0 |
1324 |
0 |
0 |
| T22 |
0 |
1367 |
0 |
0 |
| T24 |
1402 |
0 |
0 |
0 |
| T25 |
1337 |
0 |
0 |
0 |
| T26 |
1206 |
0 |
0 |
0 |
| T27 |
827 |
0 |
0 |
0 |
| T30 |
0 |
301 |
0 |
0 |
| T55 |
0 |
1037 |
0 |
0 |
| T109 |
0 |
136 |
0 |
0 |
DepthKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12472250 |
12275519 |
0 |
0 |
| T1 |
1872 |
1815 |
0 |
0 |
| T2 |
1509 |
1421 |
0 |
0 |
| T3 |
2534 |
2469 |
0 |
0 |
| T4 |
1705 |
1560 |
0 |
0 |
| T5 |
652 |
527 |
0 |
0 |
| T6 |
10597 |
10289 |
0 |
0 |
| T17 |
2262 |
2203 |
0 |
0 |
| T24 |
1402 |
1319 |
0 |
0 |
| T25 |
1337 |
1238 |
0 |
0 |
| T26 |
1206 |
1107 |
0 |
0 |
RvalidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12472250 |
12275519 |
0 |
0 |
| T1 |
1872 |
1815 |
0 |
0 |
| T2 |
1509 |
1421 |
0 |
0 |
| T3 |
2534 |
2469 |
0 |
0 |
| T4 |
1705 |
1560 |
0 |
0 |
| T5 |
652 |
527 |
0 |
0 |
| T6 |
10597 |
10289 |
0 |
0 |
| T17 |
2262 |
2203 |
0 |
0 |
| T24 |
1402 |
1319 |
0 |
0 |
| T25 |
1337 |
1238 |
0 |
0 |
| T26 |
1206 |
1107 |
0 |
0 |
WreadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12472250 |
12275519 |
0 |
0 |
| T1 |
1872 |
1815 |
0 |
0 |
| T2 |
1509 |
1421 |
0 |
0 |
| T3 |
2534 |
2469 |
0 |
0 |
| T4 |
1705 |
1560 |
0 |
0 |
| T5 |
652 |
527 |
0 |
0 |
| T6 |
10597 |
10289 |
0 |
0 |
| T17 |
2262 |
2203 |
0 |
0 |
| T24 |
1402 |
1319 |
0 |
0 |
| T25 |
1337 |
1238 |
0 |
0 |
| T26 |
1206 |
1107 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
12239303 |
567850 |
0 |
0 |
| T4 |
1705 |
0 |
0 |
0 |
| T5 |
652 |
110 |
0 |
0 |
| T6 |
10597 |
0 |
0 |
0 |
| T7 |
0 |
555 |
0 |
0 |
| T10 |
2468 |
1167 |
0 |
0 |
| T11 |
4162 |
2866 |
0 |
0 |
| T12 |
0 |
52 |
0 |
0 |
| T17 |
2262 |
313 |
0 |
0 |
| T21 |
0 |
1324 |
0 |
0 |
| T22 |
0 |
1367 |
0 |
0 |
| T24 |
1402 |
0 |
0 |
0 |
| T25 |
1337 |
0 |
0 |
0 |
| T26 |
1206 |
0 |
0 |
0 |
| T27 |
827 |
0 |
0 |
0 |
| T30 |
0 |
301 |
0 |
0 |
| T75 |
0 |
156 |
0 |
0 |