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Module Instance : tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_auto_req_mode_field_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_cmd_fifo_rst_field_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_edn_bus_cmp_alert


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_recov_alert_sts_csrng_ack_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_recov_alert_sts_csrng_ack_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_sfifo_rescmd_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_sfifo_rescmd_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_sfifo_gencmd_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_sfifo_gencmd_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_edn_ack_sm_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_edn_ack_sm_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_edn_main_sm_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_edn_main_sm_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_edn_cntr_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_edn_cntr_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_fifo_write_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_fifo_write_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_fifo_read_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_fifo_read_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_fifo_state_err.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_fifo_state_err


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_err_code_test.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_err_code_test


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_main_sm_state.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
65.24 85.71 50.00 60.00 u_main_sm_state


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb
tb.dut.u_reg.u_recov_alert_sts_csrng_ack_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_sfifo_rescmd_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_sfifo_gencmd_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_edn_ack_sm_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_edn_main_sm_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_edn_cntr_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_fifo_write_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_fifo_read_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_fifo_state_err.wr_en_data_arb
tb.dut.u_reg.u_err_code_test.wr_en_data_arb
tb.dut.u_reg.u_main_sm_state.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T1 T2 T3  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_auto_req_mode_field_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T133,T58
10CoveredT17,T12,T30

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT12,T133,T58
11CoveredT12,T133,T58

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T133,T58

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T12,T30
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T1 T2 T3  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_cmd_fifo_rst_field_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T30,T82
10CoveredT17,T12,T30

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T30,T82
11CoveredT17,T30,T82

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T30,T82

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T12,T30
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T3 T17 T6  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_edn_bus_cmp_alert.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T12,T30
10CoveredT17,T12,T30

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T12,T30
11CoveredT17,T12,T30

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T12,T30

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T12,T30
Line Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_csrng_ack_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T17 T12 T30  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_recov_alert_sts_csrng_ack_err.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT17,T12,T30
10CoveredT17,T12,T30

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT17,T12,T30
11CoveredT17,T12,T30

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T12,T30

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T12,T30
Line Coverage for Instance : tb.dut.u_reg.u_err_code_sfifo_rescmd_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN4311100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 0/1 ==> assign wr_data = d; 45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_sfifo_gencmd_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN4311100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 0/1 ==> assign wr_data = d; 45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_edn_ack_sm_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN4311100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 0/1 ==> assign wr_data = d; 45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_edn_main_sm_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN4311100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 0/1 ==> assign wr_data = d; 45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_edn_cntr_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN4311100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 0/1 ==> assign wr_data = d; 45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_fifo_write_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN4311100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 0/1 ==> assign wr_data = d; 45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_fifo_read_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN4311100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 0/1 ==> assign wr_data = d; 45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_fifo_state_err.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN4311100.00
CONT_ASSIGN44100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 1/1 assign wr_en = de; Tests: T1 T2 T3  44 0/1 ==> assign wr_data = d; 45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_err_code_test.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T2 T3 T17  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_err_code_test.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T17

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T17

Branch Coverage for Instance : tb.dut.u_reg.u_err_code_test.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T2,T3,T17
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_main_sm_state.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%